https://bugs.freedesktop.org/show_bug.cgi?id=112079
Bug ID: 112079
Summary: X lockups with HWCursor enabled - Navi 5700 XT
Product: DRI
Version: DRI git
Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
On 2019/10/21 上午7:41, Parav Pandit wrote:
-Original Message-
From: Jason Wang
Sent: Thursday, October 17, 2019 5:49 AM
To: k...@vger.kernel.org; linux-s...@vger.kernel.org; linux-
ker...@vger.kernel.org; dri-devel@lists.freedesktop.org; intel-
g...@lists.freedesktop.org;
On 2019/10/18 下午10:20, Cornelia Huck wrote:
On Thu, 17 Oct 2019 18:48:35 +0800
Jason Wang wrote:
This patch introduces a new mdev transport for virtio. This is used to
use kernel virtio driver to drive the mediated device that is capable
of populating virtqueue directly.
A new virtio-mdev
> -Original Message-
> From: Ville Syrjälä
> Sent: Monday, October 14, 2019 10:42 PM
> To: Lin, Wayne
> Cc: dri-devel@lists.freedesktop.org; intel-...@lists.freedesktop.org
> Subject: Re: [PATCH 4/4] drm/edid: Prep for HDMI VIC aspect ratio (WIP)
>
> On Mon, Oct 14, 2019 at 09:27:07AM
On Fri, Oct 18, 2019 at 05:31:19PM -0400, Lyude Paul wrote:
> On Tue, 2019-10-15 at 16:35 +0200, Thierry Reding wrote:
> > From: Thierry Reding
> >
> > Use microsecond sleeps for the clock recovery and channel equalization
> > delays during link training. The duration of these delays can be from
On Fri, Oct 18, 2019 at 06:03:27PM +0530, Kiran Gunda wrote:
> WLED4 peripheral is present on some PMICs like pmi8998 and
> pm660l. It has a different register map and configurations
> are also different. Add support for it.
>
> Signed-off-by: Kiran Gunda
> Reviewed-by: Bjorn Andersson
https://bugs.freedesktop.org/show_bug.cgi?id=111229
--- Comment #11 from Eugene Shatsky ---
Since last comment I've used this for a dozen times for switching between Linux
desktop and Windows VM, one time amdgpu crashed after resume from suspend but
I'm not sure if it was related to this bug and
Add a new helper function drm_color_ctm_s31_32_to_qm_n() for driver to
convert S31.32 sign-magnitude to Qm.n 2's complement that supported by
hardware.
V4: Address Mihai, Daniel and Ilia's review comments.
V5: Includes the sign bit in the value of m (Qm.n).
V6: Allows m == 0 according to Mihail's
This function is used to convert drm color lut to komeda HW required curve
coeffs values.
Signed-off-by: james qian wang (Arm Technology China)
Reviewed-by: Mihail Atanassov
---
.../arm/display/komeda/komeda_color_mgmt.c| 52 +++
.../arm/display/komeda/komeda_color_mgmt.h
On Mon, Oct 21, 2019 at 4:14 AM Alex Hung wrote:
>
> We have done some tests on three of Intel + nVidia configuration
> systems with OEM _OSI strings removed - while some bugs are still
> observed, ex. one out of three has suspend/resume issues, no system
> crashes were observed - the biggest
On Mon, 21 Oct 2019 13:59:23 +0800
Jason Wang wrote:
> On 2019/10/18 下午10:20, Cornelia Huck wrote:
> > On Thu, 17 Oct 2019 18:48:35 +0800
> > Jason Wang wrote:
> >
> >> This patch introduces a new mdev transport for virtio. This is used to
> >> use kernel virtio driver to drive the mediated
On Sat, Oct 19, 2019 at 10:35:50AM +0200, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski
>
> The GPIO backlight driver currently requests the line 'as is', without
> acively setting its direction. This can lead to problems: if the line
> is in input mode by default, we won't be able to
ecify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url:
https://github.com/0day-ci/linux/commits/Guido-G-nther/dt-bindings-display-bridge-Add-binding-for-NWL-mipi-dsi-host-controller/20191021-180825
base: https://git.kernel.org/pub/scm/linux/kernel/git/tor
On Fri, Oct 18, 2019 at 05:33:12PM -0400, Lyude Paul wrote:
> This also seems like maybe it should just go into the previous patch?
I suppose they could both be merged, but I think it's better to keep
them separate. In fact, I'm having second thoughts about the new helper
because it doesn't
On Sat, Oct 19, 2019 at 09:41:27AM -0400, Andrew F. Davis wrote:
> On 10/18/19 2:57 PM, Ayan Halder wrote:
> > On Fri, Oct 18, 2019 at 11:49:22AM -0700, John Stultz wrote:
> >> On Fri, Oct 18, 2019 at 11:41 AM Ayan Halder wrote:
> >>> On Fri, Oct 18, 2019 at 09:55:17AM +, Brian Starkey wrote:
On Tue, Oct 15, 2019 at 04:07:26PM +0200, Daniel Vetter wrote:
> On Mon, Oct 14, 2019 at 06:13:26PM +0200, Johan Hovold wrote:
> > On Mon, Oct 14, 2019 at 10:48:47AM +0200, Daniel Vetter wrote:
> > > Do you have a legit usecase for interruptible sleeps in fops->release?
> >
> > The tty layer
On Fri, Oct 18, 2019 at 06:03:29PM +0530, Kiran Gunda wrote:
> The auto string detection algorithm checks if the current WLED
> sink configuration is valid. It tries enabling every sink and
> checks if the OVP fault is observed. Based on this information
> it detects and enables the valid sink
On Thu, Oct 17, 2019 at 10:06:38AM +0300, Andy Shevchenko wrote:
> On Thu, Oct 17, 2019 at 08:44:26AM +0200, Daniel Vetter wrote:
> > In DMA mode we have a maximum transfer size, past that the driver
> > falls back to PIO (see the check at the top of pxa2xx_spi_transfer_one).
> > Falling back to
The Amlogic VPU embeds a "Register DMA" that can write a sequence of registers
on the VPU AHB bus, either manually or triggered by an internal IRQ event like
VSYNC or a line input counter.
This adds the register defines.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/meson/meson_registers.h
Finally, setup the VIU registers and start the AFBC decoder to support
displaying AFBC encoded buffers on Amlogic GXM and G12A SoCs.
The RDMA is used here to reset and program the AFBC decoder unit
on each vsync without involving the interrupt handler that can
be masked for a long period of time,
The Amlogic G12A AFBC Decoder pixel input need to be routed diferently
than the Amlogic GXM AFBC decoder, this adds support for routing the
VIU OSD1 pixel source to the AFBC "Mali Unpack" module.
This "Mali Unpack" module is also configured with a static RGBA mapping
for now until we support more
When using an AFBC encoded frame, the AFBC Decoder must be resetted,
configured and enabled at each vsync IRQ.
To leave time for that, use the maximum lines hold time to give time
for AFBC setup and avoid visual glitches.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/meson/meson_viu.c | 2
The VPU embeds a "Register DMA" that can write a sequence of registers
on the VPU AHB bus, either manually or triggered by an internal IRQ
event like VSYNC or a line input counter.
The initial implementation handles a single channel (over 8), triggered
by the VSYNC irq and does not handle the
Add the registers used to program the ARM Framebuffer Compression decoders
used in the Amlogic GXM and G12A SoCs families.
This also adds the routing and pipeline configuration bits and registers
needed to enable AFBC support.
Signed-off-by: Neil Armstrong
---
This adds the driver for the ARM Framebuffer Compression decoders found
in the Amlogic GXM and G12A SoCs.
The Amlogic GXM and G12A AFBC decoder are totally different, the GXM only
handling only the AFBC v1.0 modes and the G12A decoder handling the
AFBC v1.2 modes.
The G12A AFBC decoder is an
This adds all the OSD configuration plumbing to support the AFBC decoders
path to display of the OSD1 plane.
The Amlogic GXM and G12A AFBC decoders are integrated very differently.
The Amlogic GXM has a direct output path to the OSD1 VIU pixel input,
because the GXM AFBC decoder seem to be a
On Sat, Oct 19, 2019 at 10:35:49AM +0200, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski
>
> Remove a double newline from the driver.
>
> Signed-off-by: Bartosz Golaszewski
Reviewed-by: Daniel Thompson
(wow! that one was easy ;-) )
> ---
> drivers/video/backlight/gpio_backlight.c
https://bugs.freedesktop.org/show_bug.cgi?id=111481
--- Comment #119 from Daniel Suarez ---
(In reply to Andrew Sheldon from comment #118)
> (In reply to Daniel Suarez from comment #117)
> > Test out kernel 5.4rc4, it should have addressed this I believe.
> If you're referring to:
https://bugs.freedesktop.org/show_bug.cgi?id=110674
--- Comment #168 from line...@xcpp.org ---
Created attachment 145784
--> https://bugs.freedesktop.org/attachment.cgi?id=145784=edit
5.3.7: Fence fallback timer expired on ring
Here is a freeze which went a bit differently.
This time the
On Mon, Oct 21, 2019 at 10:48 AM Karol Herbst wrote:
>
> fyi: I decided to go for a different workaround to fix the runpm
> issues observed with nvidia gpus with nouveau in the "pci: prevent
> putting nvidia GPUs into lower device states on certain intel bridges"
> thread
OK, I've seen that.
>
On Fri, 18 Oct 2019 at 17:43, Arnd Bergmann wrote:
>
> The mach/hardware.h is included in lots of places, and it provides
> three different things on pxa:
>
> - the cpu_is_pxa* macros
> - an indirect inclusion of mach/addr-map.h
> - the __REG() and io_pv2() helper macros
>
> Split it up into
On Fri, Oct 18, 2019 at 05:27:59PM -0400, Lyude Paul wrote:
> On Tue, 2019-10-15 at 16:35 +0200, Thierry Reding wrote:
> > From: Thierry Reding
> >
> > Store the AUX read interval from DPCD, so that it can be used to wait
> > for the durations given in the specification during link training.
> >
Hi,
On 18/10/2019 23:11, Sean Paul wrote:
On Fri, Oct 18, 2019 at 9:46 AM Tomi Valkeinen wrote:
Hi Sean,
On 17/10/2019 22:26, Sean Paul wrote:
concern for those. The omap OMAP_BO_MEM_* changes though I don't think have
really reached non-TI eyes. There's no link in the commit message to a
fyi: I decided to go for a different workaround to fix the runpm
issues observed with nvidia gpus with nouveau in the "pci: prevent
putting nvidia GPUs into lower device states on certain intel bridges"
thread
that's on the pci and pm mailing list. Maybe it makes sense to wait
for that to land
On Wed, Oct 16, 2019 at 10:55 AM Jacopo Mondi wrote:
> Add CMM units to Renesas R-Car Gen3 SoC that support it, and reference them
> from the Display Unit they are connected to.
>
> Sort the 'vsps', 'renesas,cmm' and 'status' properties in the DU unit
> consistently in all the involved DTS.
>
>
Also store the framebuffer width in the private common struct
to be used by the AFBC decoder module driver when committing the AFBC
plane.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/meson/meson_drv.h | 1 +
drivers/gpu/drm/meson/meson_plane.c | 1 +
2 files changed, 2 insertions(+)
This adds support for the ARM Framebuffer Compression decoders found
in the Amlogic GXM and G12A SoCs.
This patchset is a merge of v2 "drm/meson: add AFBC support" at [3] and v2
"drm/meson: implement RDMA for AFBC reset on vsync" at [4].
The VPU embeds a "Register DMA" that can write a sequence
On Fri, Oct 18, 2019 at 11:26:52AM -0700, John Stultz wrote:
> On Fri, Oct 18, 2019 at 4:18 AM Brian Starkey wrote:
> > On Fri, Oct 18, 2019 at 05:23:19AM +, John Stultz wrote:
> >
> > As in v3:
> >
> > * Avoid EXPORT_SYMBOL until we finalize modules (suggested by
> >Brian)
>
> Heh. I
Hi Karol,
Sorry for commenting late, I just came back from vacation.
On Wed, Oct 16, 2019 at 04:44:49PM +0200, Karol Herbst wrote:
> Fixes state transitions of Nvidia Pascal GPUs from D3cold into higher device
> states.
>
> v2: convert to pci_dev quirk
> put a proper technical explanation
On Mon, Oct 21, 2019 at 1:40 PM Mika Westerberg
wrote:
>
> Hi Karol,
>
> Sorry for commenting late, I just came back from vacation.
>
> On Wed, Oct 16, 2019 at 04:44:49PM +0200, Karol Herbst wrote:
> > Fixes state transitions of Nvidia Pascal GPUs from D3cold into higher device
> > states.
> >
>
On Mon, Oct 21, 2019 at 10:48 AM Pekka Paalanen wrote:
>
> On Fri, 18 Oct 2019 17:47:49 +0200
> Daniel Vetter wrote:
>
> > On Fri, Oct 18, 2019 at 4:34 PM Pekka Paalanen wrote:
> > >
> > > On Fri, 18 Oct 2019 16:19:33 +0200
> > > Daniel Vetter wrote:
> > >
> > > > On Fri, Oct 18, 2019 at 3:43
On Wednesday, 16 October 2019 09:23:03 BST james qian wang (Arm Technology
China) wrote:
> On Mon, Sep 30, 2019 at 12:23:07PM +, Mihail Atanassov wrote:
> > Fix both the string and the struct member being printed.
> >
> > Changes since v1:
> > - Now with a bonus grammar fix, too.
> >
> >
On Mon, Oct 21, 2019 at 02:08:57PM +0300, Andy Shevchenko wrote:
> Mark, can be this applied?
b2662a164f9dc48d
Please don't send content free pings and please allow a reasonable time
for review. People get busy, go on holiday, attend conferences and so
on so unless there is some reason for
https://bugs.freedesktop.org/show_bug.cgi?id=111481
--- Comment #120 from Daniel Suarez ---
Am I correct in assuming that there's no other patches or commits waiting to be
upstreamed? Great, Mesa 19.2.2 will release this Wednesday and again be a other
release that's unusable. Same goes for
On Mon, Oct 21, 2019 at 03:02:23PM +0200, Karol Herbst wrote:
> > No, just block runtime PM from the device in nouveau driver.
>
> but that's not what the patch does. It only skips the PCI PM reg
> write, but still let the ACPI method be invoked to put the device into
> D3cold
Oh, indeed it
On Wed, Oct 16, 2019 at 11:48:22PM +0200, Karol Herbst wrote:
> On Wed, Oct 16, 2019 at 11:37 PM Bjorn Helgaas wrote:
> >
> > [+cc linux-acpi]
> >
> > On Wed, Oct 16, 2019 at 09:18:32PM +0200, Karol Herbst wrote:
> > > but setting the PCI_DEV_FLAGS_NO_D3 flag does prevent using the
> > > platform
On Fri, Oct 11, 2019 at 01:18:10PM +0200, Andrzej Pietrasiewicz wrote:
> These are useful for other users of afbc, e.g. rockchip.
>
> Signed-off-by: Andrzej Pietrasiewicz
Hi Andrzej,
Thanks a lot for doing this. Much appreciated. :)
It was on our TODO list for a long time.
I have cc-ed
Add an DMA-buf export implementation independent of the DRM helpers.
This not only avoids the caching of DMA-buf mappings, but also
allows us to use the new dynamic locking approach.
This is also a prerequisite of unpinned DMA-buf handling.
v2: fix unintended recursion, remove debugging
This patch is a stripped down version of the locking changes
necessary to support dynamic DMA-buf handling.
It adds a dynamic flag for both importers as well as exporters
so that drivers can choose if they want the reservation object
locked or unlocked during mapping of attachments.
For
The attachment list is now protected by the dma_resv object.
So we can drop holding this lock to allow concurrent attach
and detach operations.
Signed-off-by: Christian König
---
drivers/dma-buf/dma-buf.c | 16
1 file changed, 16 deletions(-)
diff --git
Instead of relying on the DRM functions just implement our own import
functions. This prepares support for taking care of unpinned DMA-buf.
v2: enable for all exporters, not just amdgpu, fix invalidation
handling, lock reservation object while setting callback
v3: change to new dma_buf attach
On 19/10/2019 08:28, Yi Wang wrote:
> We get these warnings when build kernel W=1:
> drivers/gpu/drm/panfrost/panfrost_perfcnt.c:35:6: warning: no previous
> prototype for ‘panfrost_perfcnt_clean_cache_done’ [-Wmissing-prototypes]
> drivers/gpu/drm/panfrost/panfrost_perfcnt.c:40:6: warning: no
On Mon, Oct 21, 2019 at 03:54:09PM +0200, Karol Herbst wrote:
> > I really would like to provide you more information about such
> > workaround but I'm not aware of any ;-) I have not seen any issues like
> > this when D3cold is properly implemented in the platform. That's why
> > I'm bit
On 10/18/19 3:49 PM, Thomas Hellström (VMware) wrote:
Hi, Christian,
On 10/16/19 11:30 AM, Christian König wrote:
Am 25.09.19 um 14:10 schrieb Christian König:
Am 25.09.19 um 14:06 schrieb Thomas Hellström (VMware):
On 9/25/19 12:55 PM, Christian König wrote:
This allows blocking for BOs
On Mon, Oct 21, 2019 at 2:06 PM Mika Westerberg
wrote:
>
> On Mon, Oct 21, 2019 at 02:00:46PM +0200, Karol Herbst wrote:
> > On Mon, Oct 21, 2019 at 1:40 PM Mika Westerberg
> > wrote:
> > >
> > > Hi Karol,
> > >
> > > Sorry for commenting late, I just came back from vacation.
> > >
> > > On Wed,
On Mon, Oct 21, 2019 at 3:33 PM Mika Westerberg
wrote:
>
> On Wed, Oct 16, 2019 at 11:48:22PM +0200, Karol Herbst wrote:
> > On Wed, Oct 16, 2019 at 11:37 PM Bjorn Helgaas wrote:
> > >
> > > [+cc linux-acpi]
> > >
> > > On Wed, Oct 16, 2019 at 09:18:32PM +0200, Karol Herbst wrote:
> > > > but
On Wednesday, 16 October 2019 09:21:24 BST james qian wang (Arm Technology
China) wrote:
> On Thu, Oct 10, 2019 at 10:30:07AM +, Mihail Atanassov wrote:
> > HW doesn't allow flushing inactive pipes and raises an MERR interrupt
> > if you try to do so. Stop triggering the MERR interrupt in the
On Mon, Oct 21, 2019 at 02:00:46PM +0200, Karol Herbst wrote:
> On Mon, Oct 21, 2019 at 1:40 PM Mika Westerberg
> wrote:
> >
> > Hi Karol,
> >
> > Sorry for commenting late, I just came back from vacation.
> >
> > On Wed, Oct 16, 2019 at 04:44:49PM +0200, Karol Herbst wrote:
> > > Fixes state
On Wednesday, 16 October 2019 09:17:39 BST james qian wang (Arm Technology
China) wrote:
> On Tue, Oct 15, 2019 at 11:00:01AM +, Mihail Atanassov wrote:
> > Signed-off-by: Mihail Atanassov
> > ---
> > .../gpu/drm/arm/display/komeda/d71/d71_component.c | 14 +-
> > 1 file
From: Thierry Reding
Hi,
Following up on the discussion about the usefulness of the drm_dp_link
helpers, here's a new series that adds a couple of new DPCD parser
functions and then pushes the drm_dp_link helpers down into drivers.
For most drivers this was pretty easy to do since they didn't
From: Thierry Reding
During the discussion of patches that enhance the drm_dp_link helpers it
was concluded that these helpers aren't very useful to begin with. Start
pushing the equivalent code into individual drivers to ultimately remove
them.
Signed-off-by: Thierry Reding
---
From: Thierry Reding
During the discussion of patches that enhance the drm_dp_link helpers it
was concluded that these helpers aren't very useful to begin with. Start
pushing the equivalent code into individual drivers to ultimately remove
them.
Signed-off-by: Thierry Reding
---
From: Thierry Reding
During the discussion of patches that enhance the drm_dp_link helpers it
was concluded that these helpers aren't very useful to begin with. After
all other drivers have been converted not to use these helpers anymore,
move these helpers into the last remaining user: Tegra
From: Thierry Reding
During the discussion of patches that enhance the drm_dp_link helpers it
was concluded that these helpers aren't very useful to begin with. Start
pushing the equivalent code into individual drivers to ultimately remove
them.
v3: make link rate unsigned int to avoid overflow
From: Thierry Reding
If the transmitter supports pre-emphasis post cursor2 the sink will
request adjustments in a similar way to how it requests adjustments to
the voltage swing and pre-emphasis settings.
Add a helper to extract these adjustments on a per-lane basis from the
DPCD link status.
From: Thierry Reding
Use microsecond sleeps for the clock recovery and channel equalization
delays during link training. The duration of these delays can be from
100 us up to 16 ms. It is rude to busy-loop for that amount of time.
While at it, also convert to standard coding style by putting
From: Thierry Reding
Add a helper that checks for the fast training capability given the DPCD
receiver capabilities blob.
Reviewed-by: Lyude Paul
Signed-off-by: Thierry Reding
---
include/drm/drm_dp_helper.h | 7 +++
1 file changed, 7 insertions(+)
diff --git
From: Thierry Reding
Add a helper to check if the sink supports the eDP alternate scrambler
reset value of 0xfffe.
Reviewed-by: Lyude Paul
Signed-off-by: Thierry Reding
---
include/drm/drm_dp_helper.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/include/drm/drm_dp_helper.h
From: Thierry Reding
It's idiomatic to check the return value of a function call immediately
after the function call, without any blank lines in between, to make it
more obvious that the two lines belong together.
Reviewed-by: Lyude Paul
Signed-off-by: Thierry Reding
---
From: Thierry Reding
Keeping the list sorted alphabetically makes it much easier to determine
where to add new includes.
Reviewed-by: Lyude Paul
Signed-off-by: Thierry Reding
---
include/drm/drm_dp_helper.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
From: Thierry Reding
Add a helper to check whether the sink supports ANSI 8B/10B channel
coding capability as specified in ANSI X3.230-1994, clause 11.
Reviewed-by: Lyude Paul
Signed-off-by: Thierry Reding
---
include/drm/drm_dp_helper.h | 7 +++
1 file changed, 7 insertions(+)
diff
From: Thierry Reding
During the discussion of patches that enhance the drm_dp_link helpers it
was concluded that these helpers aren't very useful to begin with. Start
pushing the equivalent code into individual drivers to ultimately remove
them.
Signed-off-by: Thierry Reding
---
From: Thierry Reding
The DP specification uses the term "default framing" instead of "non-
enhanced framing".
Reviewed-by: Andrzej Hajda
Signed-off-by: Thierry Reding
---
drivers/gpu/drm/bridge/tc358767.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
With nouveau fixed all ttm-using drives have the correct nesting of
mmap_sem vs dma_resv, and we can just lock the buffer.
Assuming I didn't screw up anything with my audit of course.
v2:
- Dont forget wu_mutex (Christian König)
- Keep the mmap_sem-less wait optimization (Thomas)
- Use
Full audit of everyone:
- i915, radeon, amdgpu should be clean per their maintainers.
- vram helpers should be fine, they don't do command submission, so
really no business holding struct_mutex while doing copy_*_user. But
I haven't checked them all.
- panfrost seems to dma_resv_lock only
Remove unneeded indentation in blank line and space at end of line.
Signed-off-by: Krzysztof Kozlowski
---
Documentation/devicetree/bindings/display/st,stm32-dsi.yaml | 2 +-
Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
The DSI PHY regulator supports two regulator modes: LDO and DCDC.
This mode can be selected using the "qcom,dsi-phy-regulator-ldo-mode"
device tree property.
However, at the moment only the 20nm PHY driver actually implements
that option. Add a check in the 28nm PHY driver to program the
Am 21.10.19 um 15:57 schrieb Jason Gunthorpe:
> On Sun, Oct 20, 2019 at 02:21:42PM +, Koenig, Christian wrote:
>> Am 18.10.19 um 22:36 schrieb Jason Gunthorpe:
>>> On Thu, Oct 17, 2019 at 04:47:20PM +, Koenig, Christian wrote:
>>> [SNIP]
>>>
So again how are they serialized?
>>>
On Fri, Oct 18, 2019 at 1:24 PM Linus Walleij wrote:
>
> This adds a starting point for processing and defining generic
> bindings used by DSI panels. We just define one single bool
> property to force the panel into video mode for now.
>
> Cc: devicet...@vger.kernel.org
> Suggested-by: Rob
On Fri, Oct 18, 2019 at 1:46 PM H. Nikolaus Schaller wrote:
>
> The Imagination PVR/SGX GPU is part of several SoC from
> multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo
> and others.
>
> Here we describe how the SGX processor is interfaced to
> the SoC (registers, interrupt etc.).
On Mon, Oct 21, 2019 at 4:11 AM Tomi Valkeinen wrote:
>
> Hi,
>
> On 18/10/2019 23:11, Sean Paul wrote:
> > On Fri, Oct 18, 2019 at 9:46 AM Tomi Valkeinen
> > wrote:
> >>
> >> Hi Sean,
> >>
> >> On 17/10/2019 22:26, Sean Paul wrote:
> >>
> >>> concern for those. The omap OMAP_BO_MEM_* changes
Extra detail (normally off) almost never hurts.
Signed-off-by: Mihail Atanassov
---
drivers/gpu/drm/arm/display/komeda/komeda_dev.h | 11 +++
drivers/gpu/drm/arm/display/komeda/komeda_event.c | 4
2 files changed, 15 insertions(+)
diff --git
On 10/21/19 4:50 PM, Daniel Vetter wrote:
> Full audit of everyone:
>
> - i915, radeon, amdgpu should be clean per their maintainers.
>
> - vram helpers should be fine, they don't do command submission, so
> really no business holding struct_mutex while doing copy_*_user. But
> I haven't
Hi Andrzej,
On Monday, 21 October 2019 14:50:14 BST Ayan Halder wrote:
> On Fri, Oct 11, 2019 at 01:18:10PM +0200, Andrzej Pietrasiewicz wrote:
> > These are useful for other users of afbc, e.g. rockchip.
> >
> > Signed-off-by: Andrzej Pietrasiewicz
>
> Hi Andrzej,
>
> Thanks a lot for doing
I'll be the main point of contact.
Cc: James Qian Wang (Arm Technology China)
Cc: Liviu Dudau
Signed-off-by: Mihail Atanassov
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 94fb077c0817..d32f263f0022 100644
--- a/MAINTAINERS
+++
On 2019-10-21 11:03 a.m., Siqueira, Rodrigo wrote:
> Commit d7cd0e05 introduced a change at DP_DSC_THROUGHPUT_MODE_0_170
> which is not aligned with the spec. This commit replace 15 << 4 by
> 15 << 0 for DP_DSC_THROUGHPUT_MODE_0_170 in order to make it follow the
> specification.
>
> Cc: Harry
Now that there's a debugfs node to control the same, remove the
config option.
Signed-off-by: Mihail Atanassov
---
drivers/gpu/drm/arm/display/Kconfig | 6 --
drivers/gpu/drm/arm/display/komeda/Makefile | 5 ++---
drivers/gpu/drm/arm/display/komeda/komeda_dev.h | 6 --
3
Hi everyone,
This is a smallish series that tries to remove some build-time
configurability in komeda and replace it with a debugfs control. Later
patches in the series add some extra functionality which I found useful
during my debugging sessions, so I figured I'd bake it in.
I've preserved the
Named 'err_verbosity', currently with only 1 active bit in that
replicates the existing level - print error events once per flip.
Signed-off-by: Mihail Atanassov
---
drivers/gpu/drm/arm/display/komeda/komeda_dev.c | 4
drivers/gpu/drm/arm/display/komeda/komeda_dev.h | 14
It's potentially useful information when diagnosing error/warn IRQs, so
dump it to dmesg with a drm_info_printer. Hide this extra debug dumping
behind another komeda_dev->err_verbosity bit.
Note that there's not much sense in dumping it for INFO events,
since the VSYNC event will swamp the log.
It's possible to get multiple events in a single frame/flip, so add an
option to print them all.
Signed-off-by: Mihail Atanassov
---
drivers/gpu/drm/arm/display/komeda/komeda_dev.h | 2 ++
drivers/gpu/drm/arm/display/komeda/komeda_event.c | 3 ++-
2 files changed, 4 insertions(+), 1
On Mon, Oct 21, 2019 at 4:09 PM Mika Westerberg
wrote:
>
> On Mon, Oct 21, 2019 at 03:54:09PM +0200, Karol Herbst wrote:
> > > I really would like to provide you more information about such
> > > workaround but I'm not aware of any ;-) I have not seen any issues like
> > > this when D3cold is
Commit d7cd0e05 introduced a change at DP_DSC_THROUGHPUT_MODE_0_170
which is not aligned with the spec. This commit replace 15 << 4 by
15 << 0 for DP_DSC_THROUGHPUT_MODE_0_170 in order to make it follow the
specification.
Cc: Harry Wentland
Cc: Leo Li
Cc: Alex Deucher
Cc: Nikola Cornij
Cc:
Hi Rob,
> Am 21.10.2019 um 17:07 schrieb Rob Herring :
>
> On Fri, Oct 18, 2019 at 1:46 PM H. Nikolaus Schaller
> wrote:
>>
>> The Imagination PVR/SGX GPU is part of several SoC from
>> multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo
>> and others.
>>
>> Here we describe how
Convert Samsung PWM (S3C, S5P and Exynos SoCs) bindings to DT schema
format using json-schema.
Signed-off-by: Krzysztof Kozlowski
Reviewed-by: Rob Herring
---
Changes since v3:
1. Add reviewed-by.
Changes since v2:
1. Add additionalProperties: false.
Changes since v1:
1. Indent example with
Convert generic PWM controller bindings to DT schema format using
json-schema. The consumer bindings are provided by dt-schema.
Signed-off-by: Krzysztof Kozlowski
Acked-by: Stephen Boyd
Acked-by: Paul Walmsley
---
Changes since v3:
1. Remove pwm-consumers.yaml as they do not give anything
On Sun, Oct 20, 2019 at 08:19:33PM +0200, Hans de Goede wrote:
> Since commit 051a6d8d3ca0 ("drm/i915: Move LUT programming to happen after
> vblank waits"), I am seeing an ugly colored flash of the first few display
> lines on 2 Cherry Trail devices when the gamma table gets set for the first
>
We can't copy_*_user while holding reservations, that will (soon even
for nouveau) lead to deadlocks. And it breaks the cross-driver
contract around dma_resv.
Fix this by adding a slowpath for when we need relocations, and by
pushing the writeback of the new presumed offsets to the very end.
Hi all,
Essentially just a resend of the latest revision, since the series is
stuck on the nouveau patch. Ilia tried it on an nv5 and it didn't explode,
but he noticed some instability. No call yet on whether that was just the
kernel upgrade of a few versions, or my patch.
So yeah I need to get
On Mon, Oct 21, 2019 at 04:49:09PM +0200, Karol Herbst wrote:
> On Mon, Oct 21, 2019 at 4:09 PM Mika Westerberg
> wrote:
> >
> > On Mon, Oct 21, 2019 at 03:54:09PM +0200, Karol Herbst wrote:
> > > > I really would like to provide you more information about such
> > > > workaround but I'm not
1 - 100 of 187 matches
Mail list logo
