TWIMC: this mail is primarily send for documentation purposes and for
regzbot, my Linux kernel regression tracking bot. These mails usually
contain '#forregzbot' in the subject, to make them easy to spot and filter.
[TLDR: I'm adding this regression report to the list of tracked
regressions; all
On Mon, Sep 26, 2022 at 11:17:20AM -0700, Abhinav Kumar wrote:
> On 9/13/2022 1:53 AM, Johan Hovold wrote:
> > Drop the overly defensive modeset sanity checks of function parameters
> > which have already been checked or used by the callers.
> >
> > Reviewed-by: Dmitry Baryshkov
> >
On Mon, 2022-09-26 at 11:47 +0200, Ulf Hansson wrote:
> On Fri, 23 Sept 2022 at 17:23, Liu Ying wrote:
> > On Fri, 2022-09-23 at 15:48 +0200, Ulf Hansson wrote:
> > > On Fri, 23 Sept 2022 at 14:47, Liu Ying wrote:
> > > > After a device transitions to sleep state through it's system
> > > >
On Tue, Sep 27, 2022 at 09:25:54AM +0200, Maxime Ripard wrote:
> Hi Stefan,
>
> On Mon, Sep 26, 2022 at 08:50:12PM +0200, Stefan Wahren wrote:
> > Am 26.09.22 um 14:47 schrieb Maxime Ripard:
> > > On Mon, Sep 26, 2022 at 02:40:48PM +0200, Marc Kleine-Budde wrote:
> > > > On 26.09.2022 14:08:04,
> -Original Message-
> From: Javier Martinez Canillas
> Sent: Tuesday, September 27, 2022 2:33 PM
> To: Vinod Polimera ;
> dmitry.barysh...@linaro.org; Vinod Polimera (QUIC)
> ; dri-devel@lists.freedesktop.org; linux-arm-
> m...@vger.kernel.org; freedr...@lists.freedesktop.org;
>
Add support for the BOE - NT116WHM-N4C (HW: V8.1) panel.
Signed-off-by: Sean Hong
---
drivers/gpu/drm/panel/panel-edp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/panel/panel-edp.c
b/drivers/gpu/drm/panel/panel-edp.c
index 102ab9f5d40a..03a4a49e4ecb 100644
---
On Mon, Sep 26, 2022 at 11:21:38AM -0700, Abhinav Kumar wrote:
>
>
> On 9/13/2022 1:53 AM, Johan Hovold wrote:
> > Drop the overly defensive modeset sanity checks of function parameters
> > which have already been checked or used by the callers.
> >
> > Reviewed-by: Dmitry Baryshkov
> >
On 26/09/2022 18:09, Niranjana Vishwanathapura wrote:
On Mon, Sep 26, 2022 at 05:26:12PM +0100, Tvrtko Ursulin wrote:
On 24/09/2022 05:30, Niranjana Vishwanathapura wrote:
On Fri, Sep 23, 2022 at 09:40:20AM +0100, Tvrtko Ursulin wrote:
On 21/09/2022 08:09, Niranjana Vishwanathapura wrote:
On Mon, Sep 26, 2022, at 11:07 PM, Kees Cook wrote:
> On Mon, Sep 26, 2022 at 01:17:18PM -0700, Nick Desaulniers wrote:
>> + Arnd
>>
>> On Mon, Sep 26, 2022 at 12:11 PM Kees Cook wrote:
>> > ---
>> > v2:
>> > - fix comment typo
>> > - wrap clang pragma to avoid GCC warnings
>> > - style nit
On Mon, 2022-09-26 at 16:54 -0500, Rob Herring wrote:
> On Mon, Sep 26, 2022 at 10:52:04AM +0800, liangxu.xu wrote:
> > On Fri, 2022-09-23 at 13:16 +0200, Krzysztof Kozlowski wrote:
> > > On 23/09/2022 03:39, liangxu...@mediatek.com wrote:
> > > > From: liangxu xu
> > > >
> > > > Add dt-binding
Hi Kees,
Thanks for update it to v2.
I'm leaving a comment because the patches this patch depends on aren't
part of one of the series.
If this patch alone is forwarded to the intel-gfx mailing, it will
report a build issue.
If this patch is only for review, please ignore my comments.
In order
Synchronize CPU access to GEM BOs with other drivers when updating the
screen buffer. Imported DMA buffers might otherwise contain stale data.
Suggested-by: Thomas Zimmermann
Signed-off-by: Javier Martinez Canillas
---
drivers/gpu/drm/solomon/ssd130x.c | 7 +++
1 file changed, 7
Hi Stefan,
On Mon, Sep 26, 2022 at 08:50:12PM +0200, Stefan Wahren wrote:
> Am 26.09.22 um 14:47 schrieb Maxime Ripard:
> > On Mon, Sep 26, 2022 at 02:40:48PM +0200, Marc Kleine-Budde wrote:
> > > On 26.09.2022 14:08:04, Stefan Wahren wrote:
> > > > Hi Marc,
> > > >
> > > > Am 26.09.22 um 12:21
On Mon, 2022-09-26 at 14:53 +0200, Krzysztof Kozlowski wrote:
> On 26/09/2022 14:12, liangxu.xu wrote:
> >
> > Can I modify it to the following form:
> > properties:
> > compatible:
> > oneOf:
> > - enum:
> > - mediatek,mt2701-dpi
> > - mediatek,mt7623-dpi
> >
> -Original Message-
> From: Dmitry Baryshkov
> Sent: Friday, August 26, 2022 2:11 PM
> To: Vinod Polimera (QUIC) ; dri-
> de...@lists.freedesktop.org; linux-arm-...@vger.kernel.org;
> freedr...@lists.freedesktop.org; devicet...@vger.kernel.org
> Cc: linux-ker...@vger.kernel.org;
Hello Vinod and Dmitry,
On 9/27/22 09:31, Vinod Polimera wrote:
>> -Original Message-
>> From: Dmitry Baryshkov
>> Sent: Friday, August 26, 2022 2:11 PM
>> To: Vinod Polimera (QUIC) ; dri-
>> de...@lists.freedesktop.org; linux-arm-...@vger.kernel.org;
>> freedr...@lists.freedesktop.org;
When the avdd-0v9 or avdd-1v8 supply are not yet available, EPROBE_DEFER
is returned by rockchip_hdmi_parse_dt(). This causes the following error
message to be printed multiple times:
dwhdmi-rockchip fe0a.hdmi: [drm:dw_hdmi_rockchip_bind [rockchipdrm]]
*ERROR* Unable to parse OF data
Hi Maxime,
Am 27.09.22 um 09:25 schrieb Maxime Ripard:
Hi Stefan,
On Mon, Sep 26, 2022 at 08:50:12PM +0200, Stefan Wahren wrote:
Am 26.09.22 um 14:47 schrieb Maxime Ripard:
On Mon, Sep 26, 2022 at 02:40:48PM +0200, Marc Kleine-Budde wrote:
On 26.09.2022 14:08:04, Stefan Wahren wrote:
Hi
On 23-09-2022 03:41, Daniele Ceraolo Spurio wrote:
> On MTL the primary GT doesn't have any media capabilities, so no video
> engines and no HuC. We must therefore skip the HuC fetch and load on
> that specific case. Given that other multi-GT platforms might have HuC
> on the primary GT, we
In this series added GEN12 RPSTAT (0x1381b4) to get Current Actual
Graphics frequency of GT
To review saperately the patch in this series split from
https://patchwork.freedesktop.org/series/108156/#rev3
Test-with: 20220927062839.2718582-1-ashutosh.di...@intel.com
v2: Fix review comments
On Tue, 20 Sep 2022 14:22, AngeloGioacchino Del Regno
wrote:
>Il 19/09/22 18:56, Guillaume Ranquet ha scritto:
>> Add the DPI1 hdmi path support in mtk dpi driver
>>
>> Signed-off-by: Guillaume Ranquet
>>
>> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
>> b/drivers/gpu/drm/mediatek/mtk_dpi.c
On Thu, 22 Sep 2022 09:22, Krzysztof Kozlowski
wrote:
>On 19/09/2022 18:56, Guillaume Ranquet wrote:
>> Add the DPI1 hdmi path support in mtk dpi driver
>>
>> Signed-off-by: Guillaume Ranquet
>>
>> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
>> b/drivers/gpu/drm/mediatek/mtk_dpi.c
>> index
On 27/09/2022 15:54, Guillaume Ranquet wrote:
> On Thu, 22 Sep 2022 09:18, Krzysztof Kozlowski
> wrote:
>> On 19/09/2022 18:56, Guillaume Ranquet wrote:
>>> Add mt8195 SoC bindings for hdmi and hdmi-ddc
>>>
>>> Make port1 optional for mt8195 as it only supports HDMI tx for now.
>>> Requires a
Am 27.09.22 um 11:42 schrieb Maxime Ripard:
On Tue, Sep 27, 2022 at 09:25:54AM +0200, Maxime Ripard wrote:
Hi Stefan,
On Mon, Sep 26, 2022 at 08:50:12PM +0200, Stefan Wahren wrote:
Am 26.09.22 um 14:47 schrieb Maxime Ripard:
On Mon, Sep 26, 2022 at 02:40:48PM +0200, Marc Kleine-Budde wrote:
Hi
Am 27.09.22 um 11:52 schrieb Javier Martinez Canillas:
Synchronize CPU access to GEM BOs with other drivers when updating the
screen buffer. Imported DMA buffers might otherwise contain stale data.
Suggested-by: Thomas Zimmermann
Signed-off-by: Javier Martinez Canillas
Reviewed-by:
On Tue, Sep 27, 2022 at 01:12:35PM +0200, Stefan Wahren wrote:
> Am 27.09.22 um 11:42 schrieb Maxime Ripard:
> > On Tue, Sep 27, 2022 at 09:25:54AM +0200, Maxime Ripard wrote:
> > > Hi Stefan,
> > >
> > > On Mon, Sep 26, 2022 at 08:50:12PM +0200, Stefan Wahren wrote:
> > > > Am 26.09.22 um 14:47
On Tue, Sep 27, 2022 at 01:42:40PM +0200, Maxime Ripard wrote:
> On Tue, Sep 27, 2022 at 01:12:35PM +0200, Stefan Wahren wrote:
> > Am 27.09.22 um 11:42 schrieb Maxime Ripard:
> > > On Tue, Sep 27, 2022 at 09:25:54AM +0200, Maxime Ripard wrote:
> > > > Hi Stefan,
> > > >
> > > > On Mon, Sep 26,
On Tue, 20 Sep 2022 09:46, Chunfeng Yun wrote:
>On Mon, 2022-09-19 at 18:56 +0200, Guillaume Ranquet wrote:
>> Add basic support for the mediatek hdmi phy on MT8195 SoC
>>
>> Signed-off-by: Guillaume Ranquet
>>
>> diff --git a/drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.c
>>
On Thu, 22 Sep 2022 09:18, Krzysztof Kozlowski
wrote:
>On 19/09/2022 18:56, Guillaume Ranquet wrote:
>> Add mt8195 SoC bindings for hdmi and hdmi-ddc
>>
>> Make port1 optional for mt8195 as it only supports HDMI tx for now.
>> Requires a ddc-i2c-bus phandle.
>> Requires a power-domains phandle.
On Tue, Sep 27, 2022 at 11:31:38AM +0800, Yang Yingliang wrote:
> In the probe path, dev_err() can be replaced with dev_err_probe()
> which will check if error code is -EPROBE_DEFER and prints the
> error name. It also sets the defer probe reason which can be
> checked later through debugfs. It's
On Tue, 20 Sep 2022 13:11, AngeloGioacchino Del Regno
wrote:
>Il 19/09/22 18:56, Guillaume Ranquet ha scritto:
>> Add HDMI audio support for mt8195
>>
>> Signed-off-by: Guillaume Ranquet
>>
>> diff --git a/drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.c
>>
On Tue, 20 Sep 2022 14:17, AngeloGioacchino Del Regno
wrote:
>Il 19/09/22 18:56, Guillaume Ranquet ha scritto:
>> Add basic support for the mediatek hdmi phy on MT8195 SoC
>>
>> Signed-off-by: Guillaume Ranquet
>>
>> diff --git a/drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.c
>>
On Tue, Sep 27, 2022 at 03:15:17PM +0200, Maxime Ripard wrote:
> On Tue, Sep 27, 2022 at 02:25:12PM +0200, Maxime Ripard wrote:
> > On Tue, Sep 27, 2022 at 01:42:40PM +0200, Maxime Ripard wrote:
> > > On Tue, Sep 27, 2022 at 01:12:35PM +0200, Stefan Wahren wrote:
> > > > Am 27.09.22 um 11:42
Am Sonntag, dem 25.09.2022 um 15:43 +0200 schrieb Christophe JAILLET:
> There is already a SPDX-License-Identifier tag, so the corresponding
> license text can be removed.
>
> Signed-off-by: Christophe JAILLET
For the etnaviv part:
Acked-by: Lucas Stach
Regards,
Lucas
> ---
>
On 9/27/22 13:18, Thomas Zimmermann wrote:
> Hi
>
> Am 27.09.22 um 11:52 schrieb Javier Martinez Canillas:
>> Synchronize CPU access to GEM BOs with other drivers when updating the
>> screen buffer. Imported DMA buffers might otherwise contain stale data.
>>
>> Suggested-by: Thomas Zimmermann
>>
On Thu, 22 Sep 2022 09:20, Krzysztof Kozlowski
wrote:
>On 19/09/2022 18:56, Guillaume Ranquet wrote:
>> Add dpi support to enable the HDMI path.
>>
>> Signed-off-by: Guillaume Ranquet
>>
>> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
>> b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
>> index
On Tue, 20 Sep 2022 12:25, AngeloGioacchino Del Regno
wrote:
>Il 19/09/22 18:56, Guillaume Ranquet ha scritto:
>> Create a common "framework" that can be used to add support for
>> different hdmi IPs within the mediatek range of products.
>>
>> Signed-off-by: Guillaume Ranquet
>>
>> diff --git
On 9/26/2022 11:22 PM, Badal Nilawar wrote:
From: Dale B Stimson
Use i915 HWMON to display/modify dGfx power PL1 limit and TDP setting.
v2:
- Fix review comments (Ashutosh)
- Do not restore power1_max upon module unload/load sequence
because on production systems modules are
Hi Dmitry,
On 9/26/22 01:39, Dmitry Osipenko wrote:
> 25.08.2022 17:36, Hans de Goede пишет:
>> Before this commit when we want userspace to use the acpi_video backlight
>> device we register both the GPU's native backlight device and acpi_video's
>> firmware acpi_video# backlight device. This
On Tue, Sep 27, 2022 at 9:47 AM Liu Ying wrote:
>
> On Mon, 2022-09-26 at 11:47 +0200, Ulf Hansson wrote:
> > On Fri, 23 Sept 2022 at 17:23, Liu Ying wrote:
> > > On Fri, 2022-09-23 at 15:48 +0200, Ulf Hansson wrote:
> > > > On Fri, 23 Sept 2022 at 14:47, Liu Ying wrote:
> > > > > After a
On 9/26/22 09:24, Thomas Zimmermann wrote:
>
>
> Am 23.09.22 um 10:34 schrieb Javier Martinez Canillas:
>> The struct drm_plane .state shouldn't be accessed directly but instead the
>> drm_atomic_get_new_plane_state() helper function should be used.
>>
>> This is based on a similar patch from
On 27.09.2022 13:12:35, Stefan Wahren wrote:
> > > > yes the issue is only triggered without HDMI connected. I was able to
> > > > reproduce with an older vc4 firmware from 2020 (don't want to upgrade
> > > > yet).
> > > > Kernel was also an arm64 build with defconfig.
> > > >
> > > > Here some
On Tue, Sep 27, 2022 at 02:25:12PM +0200, Maxime Ripard wrote:
> On Tue, Sep 27, 2022 at 01:42:40PM +0200, Maxime Ripard wrote:
> > On Tue, Sep 27, 2022 at 01:12:35PM +0200, Stefan Wahren wrote:
> > > Am 27.09.22 um 11:42 schrieb Maxime Ripard:
> > > > On Tue, Sep 27, 2022 at 09:25:54AM +0200,
On 9/26/2022 11:22 PM, Badal Nilawar wrote:
From: Ashutosh Dixit
Expose power1_max_interval, that is the tau corresponding to PL1, as a
custom hwmon attribute. Some bit manipulation is needed because of the
format of PKG_PWR_LIM_1_TIME in
GT0_PACKAGE_RAPL_LIMIT register (1.x * power(2,y)).
On Thu, 22 Sep 2022 09:19, Krzysztof Kozlowski
wrote:
>On 19/09/2022 18:56, Guillaume Ranquet wrote:
>> In order to share register with a dedicated ddc driver, set the hdmi
>> compatible to syscon.
>>
>> Signed-off-by: Guillaume Ranquet
>>
>> diff --git
>>
From: Don Hiatt
On GEN12 and above use GEN12_RPSTAT register to get Current
Actual Graphics Frequency of GT
v2:
- Fixed review comments(Ashutosh)
- Added function intel_rps_read_rpstat_fw to read RPSTAT without
forcewake, required especially for GEN6_RPSTAT1 (Ashutosh, Tvrtko)
Cc: Don
On Tue, 20 Sep 2022 12:18, AngeloGioacchino Del Regno
wrote:
>Il 19/09/22 18:56, Guillaume Ranquet ha scritto:
>> To prepare support for newer chips that need to share their address
>> range with a dedicated ddc driver, move to a syscon.
>>
>> Signed-off-by: Guillaume Ranquet
>>
>> diff --git
After commit 64ff18911878("drm/omap: Enable COLOR_ENCODING and COLOR_RANGE
properties for planes"), no one use struct csc_coef_rgb2yuv, so remove it.
Signed-off-by: Yuan Can
---
drivers/gpu/drm/omapdrm/dss/dispc.c | 5 -
1 file changed, 5 deletions(-)
diff --git
After commit 5a8132b9f606("drm/amd/display: remove dead dc vbios code"), no one
use struct i2c_id_config_access, so remove it.
Signed-off-by: Yuan Can
---
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 7 ---
1 file changed, 7 deletions(-)
diff --git
On 27/09/2022 15:04, Guillaume Ranquet wrote:
> On Thu, 22 Sep 2022 09:20, Krzysztof Kozlowski
> wrote:
>> On 19/09/2022 18:56, Guillaume Ranquet wrote:
>>> Add dpi support to enable the HDMI path.
>>>
>>> Signed-off-by: Guillaume Ranquet
>>>
>>> diff --git
TTM owns the pages it uses for backing buffer objects with system
memory. Because of this it is absolutely illegal to mess around with
the reference count of those pages.
So make sure that nobody ever tries to grab an extra reference on
pages allocated through the page pool.
v2: handle DMA pages
On 9/8/2022 10:44 AM, T.J. Mercier wrote:
On Tue, Aug 16, 2022 at 1:39 PM Jeffrey Hugo wrote:
Hello cgroup experts,
I have a GPU device [1] that supports organizing its resources for the
purposes of supporting containers. I am attempting to determine how to
represent this in the upstream
1. Add mt8195 driver data with compatible "mediatek-mt8195-vdosys0".
2. Add mt8195 routing table settings of vdosys0.
Signed-off-by: Jason-JH.Lin
---
drivers/soc/mediatek/mt8195-mmsys.h | 370
drivers/soc/mediatek/mtk-mmsys.c| 11 +
2 files changed, 381
For previous MediaTek SoCs, such as MT8173, there are 2 display HW
pipelines binding to 1 mmsys with the same power domain, the same
clock driver and the same mediatek-drm driver.
For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to
2 different power domains, different clock
This reverts commit 7266e90a51a32722a94daa3cb5b8fa278059e49e.
Due to the compatible changing of mt8195 from "mediatek,mt8195-mmsys"
to "mediatek,mt8195-vdosys0", we have to revert this patch and send a
new patch with the new compatible.
Signed-off-by: Jason-JH.Lin
---
Address the following error:
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stream.c: In function
‘dc_stream_remove_writeback’:
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stream.c:527:55: error: array
subscript [0, 0] is outside array bounds of ‘struct dc_writeback_info[1]’
[AMD Official Use Only - General]
Reviewed-by: Aurabindo Pillai
--
Regards,
Jay
From: Mahfooz, Hamza
Sent: Tuesday, September 27, 2022 3:12 PM
To: linux-ker...@vger.kernel.org
Cc: Mahfooz, Hamza ; Wentland, Harry
; Li, Sun peng (Leo) ; Siqueira,
Rodrigo ;
On Fri, Sep 16, 2022 at 01:48:23PM -0700, Ashutosh Dixit wrote:
> From: Chris Wilson
>
> If attempting to perform a GT reset takes long than 5 seconds (including
> resetting the display for gen3/4), then we declare all hope lost and
> discard all user work and wedge the device to prevent
Hi Maxime,
Am 27.09.22 um 15:15 schrieb Maxime Ripard:
On Tue, Sep 27, 2022 at 02:25:12PM +0200, Maxime Ripard wrote:
On Tue, Sep 27, 2022 at 01:42:40PM +0200, Maxime Ripard wrote:
On Tue, Sep 27, 2022 at 01:12:35PM +0200, Stefan Wahren wrote:
Am 27.09.22 um 11:42 schrieb Maxime Ripard:
On
On 9/27/2022 12:14 AM, Johan Hovold wrote:
On Mon, Sep 26, 2022 at 11:17:20AM -0700, Abhinav Kumar wrote:
On 9/13/2022 1:53 AM, Johan Hovold wrote:
Drop the overly defensive modeset sanity checks of function parameters
which have already been checked or used by the callers.
Reviewed-by:
On 9/27/2022 12:16 AM, Johan Hovold wrote:
On Mon, Sep 26, 2022 at 11:21:38AM -0700, Abhinav Kumar wrote:
On 9/13/2022 1:53 AM, Johan Hovold wrote:
Drop the overly defensive modeset sanity checks of function parameters
which have already been checked or used by the callers.
Reviewed-by:
On Tue, 2022-09-13 at 16:22 -0700, Ceraolo Spurio, Daniele wrote:
> Wait on the fence to be signalled to avoid the submissions finding HuC
> not yet loaded.
>
> v2: use dedicaded wait_queue_entry for waiting in HuC load, as submitq
> can't be re-used for it.
>
> Signed-off-by: Daniele Ceraolo
Hi,
On Mon, Sep 26, 2022 at 7:10 PM Sean Hong
wrote:
>
> This panel has the same delay timing as N116BCA-EA1. So, fix the
> delay timing from delay_200_500_p2e80 to delay_200_500_e80_d50.
>
> Signed-off-by: Sean Hong
> ---
> drivers/gpu/drm/panel/panel-edp.c | 2 +-
> 1 file changed, 1
On Sat, Sep 24, 2022 at 09:27:10PM +0300, Dmitry Baryshkov wrote:
> Hi,
>
> On Sat, 24 Sept 2022 at 20:23, Krzysztof Kozlowski
> wrote:
> >
> > On Sat, 24 Sep 2022 15:36:00 +0300, Dmitry Baryshkov wrote:
> > > Split Mobile Display SubSystem (MDSS) root node bindings to the separate
> > > yaml
It turns out that on production DG2/ATS HW we should have support for
PS64. This feature allows to provide a 64K TLB hint at the PTE level,
which is a lot more flexible than the current method of enabling 64K GTT
pages for the entire page-table, since that leads to all kinds of
annoying
On some platforms we potentially have different alignment restrictions
depending on the memory type. We also now have different alignment
restrictions for the same region across different kernel versions.
Extend the region query to return the minimum required GTT alignment.
Testcase:
On Fri, Aug 19, 2022 at 01:48:37AM +0530, Akhil P Oommen wrote:
> Add a reset op compatible function to poll for gdsc collapse.
>
> Signed-off-by: Akhil P Oommen
> ---
>
> (no changes since v2)
>
> Changes in v2:
> - Minor update to function prototype
>
> drivers/clk/qcom/gdsc.c | 23
virtqueue needs to be flushed and removed before VM goes into sleep or
hibernation then should be reinitialized again upon wake-up.
Cc: Gerd Hoffmann
Cc: Vivek Kasireddy
Signed-off-by: Dongwon Kim
---
drivers/gpu/drm/virtio/virtgpu_drv.c | 53 +++-
virtio-gpu host(e.g. QEMU) deletes all virtio-gpu resourses when guest
is suspended then resumed. This behavior is invisible to the guest. As
a result, the guest can send out virtio-gpu commands for those deleted
resources with an assumption they are still there on host's side when
the guest wakes
Hi,
On Mon, Sep 26, 2022 at 7:18 PM Sean Hong
wrote:
>
> This panel has the same delay timing as N116BCA-EA1. So, fix the
> delay timing from delay_200_500_p2e80 to delay_200_500_e80_d50.
>
> Signed-off-by: Sean Hong
> ---
> drivers/gpu/drm/panel/panel-edp.c | 2 +-
> 1 file changed, 1
This reverts commit b804923b7ccb9c9629703364e927b48cd02a9254.
Due to the compatible changing of mt8195 from "mediatek,mt8195-mmsys"
to "mediatek,mt8195-vdosys0", we have to revert this patch and send a
new patch with the new compatible.
Signed-off-by: Jason-JH.Lin
---
After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0,
mmsys header can remove the useless DDP_COMPONENT_DITHER enum.
Signed-off-by: Jason-JH.Lin
Reviewed-by: AngeloGioacchino Del Regno
Reviewed-by: Rex-BC Chen
Acked-by: Matthias Brugger
---
include/linux/soc/mediatek/mtk-mmsys.h
For previous MediaTek SoCs, such as MT8173, there are 2 display HW
pipelines binding to 1 mmsys with the same power domain, the same
clock driver and the same mediatek-drm driver.
For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to
2 different power domains, different clock
Add driver data of mt8195 vdosys0 to mediatek-drm and the sub driver.
Signed-off-by: Jason-JH.Lin
---
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 28
2 files changed, 34 insertions(+)
diff --git
On Tue, Sep 27, 2022 at 10:28:03AM +0100, Tvrtko Ursulin wrote:
On 26/09/2022 18:09, Niranjana Vishwanathapura wrote:
On Mon, Sep 26, 2022 at 05:26:12PM +0100, Tvrtko Ursulin wrote:
On 24/09/2022 05:30, Niranjana Vishwanathapura wrote:
On Fri, Sep 23, 2022 at 09:40:20AM +0100, Tvrtko
From: Ville Syrjälä
Various improvements (mostly) related to the EDID
range descriptor handling.
v2:
- One patch got merged already
- Reorder the struct rename to be last
- Drop the "infer vrr range for eDP" for now. While we may
want it eventually for now I'm just thinking of adding all
Hi,
On Mon, Sep 26, 2022 at 11:35 PM Sean Hong
wrote:
>
> Add support for the BOE - NT116WHM-N4C (HW: V8.1) panel.
>
> Signed-off-by: Sean Hong
> ---
> drivers/gpu/drm/panel/panel-edp.c | 1 +
> 1 file changed, 1 insertion(+)
Wow, another panel?!?
Reviewed-by: Douglas Anderson
Pushed to
From: Ville Syrjälä
Since we only use the parsed vrefresh range to determine
if VRR should be supported we should only accept continuous
frequency displays here.
Cc: Manasi Navare
Cc: Nicholas Kazlauskas
Cc: Harry Wentland
Cc: Leo Li
Cc: Rodrigo Siqueira
Cc: amd-...@lists.freedesktop.org
From: Ville Syrjälä
Extract the GTF vs. GTF2 logic into a separate function.
We'll have a second user soon.
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_edid.c | 47 --
1 file changed, 30 insertions(+), 17 deletions(-)
From: Ville Syrjälä
For some resaon we only use the secondary GTF curve for the
standard timings. Use it for inferred modes as well.
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_edid.c | 35 ++-
1 file changed, 34
From: Ville Syrjälä
Prefer the timing formula indicated by the range
descriptor for generating the non-DMT standard timings.
Previously we just used CVT for all EDID 1.4 continuous
frequency displays without even checking if the range
descriptor indicates otherwise. Now we check the range
From: Ville Syrjälä
Replace a bunch of hex constants with proper definitions.
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_edid.c | 18 +-
include/drm/drm_edid.h | 14 +-
2 files changed, 18 insertions(+), 14 deletions(-)
diff
From: Ville Syrjälä
The current comment fails to clarify why we only accept
the "range limits only" variant of the range descriptor.
Reword it to make some actual sense.
Cc: Nicholas Kazlauskas
Cc: Harry Wentland
Cc: Leo Li
Cc: Rodrigo Siqueira
Cc: amd-...@lists.freedesktop.org
Reviewed-by:
From: Ville Syrjälä
For EDID 1.4 the first detailed timing is always preferred,
for older EDIDs there was a feature flag to indicate the same.
While correct, the code setting that up is rather confusing.
Restate it in a slightly more straightforward manner.
Reviewed-by: Jani Nikula
Fence signaling must be enabled to make sure that
the dma_fence_is_signaled() and dma_fence_is_signaled_locked()
function ever returns true. Since drivers and implementations
sometimes mess this up, this ensures correct behaviour when
DEBUG_WW_MUTEX_SLOWPATH is used during debugging.
This should
This series is for adding virtio-gpu driver the support for the suspend and
resume
(or freeze and restore).
First patch adds virtio-dev hooks that adds .freeze and .restore hooks that
basically
flush and remove virtqueue before going into suspension then reinitialize them
upon
wake-up event.
Hi
Am 23.09.22 um 09:14 schrieb Geert Uytterhoeven:
Hi Thomas,
On Thu, Sep 22, 2022 at 1:33 PM Thomas Zimmermann wrote:
Open Firmware provides basic display output via the 'display' node.
DT platform code already provides a device that represents the node's
framebuffer. Add a DRM driver for
From: Ville Syrjälä
Rename info->monitor_range to info->vrr_range to actually
reflect its usage.
Cc: Nicholas Kazlauskas
Cc: Harry Wentland
Cc: Leo Li
Cc: Rodrigo Siqueira
Cc: amd-...@lists.freedesktop.org
Reviewed-by: Manasi Navare
Acked-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Get rid of the confusing version_greater() stuff and
simply compare edid->revision directly everwhere. Half
the places already did it this way, and since we actually
reject any EDID with edid->version!=1 it's a perfectly
sane thing to do.
Reviewed-by: Jani Nikula
Fence signaling must be enabled to make sure that
the dma_fence_is_signaled_locked() function ever returns true.
Since drivers and implementations sometimes mess this up,
this ensures correct behaviour when DMABUF_DEBUG_ENABLE_SIGNALING
is used during debugging.
This should make any implementation
Remove the extra signaled bit status check because
it is returning early when the fence is already signaled and
__dma_fence_enable_signaling is checking the status of signaled
bit again.
Signed-off-by: Arvind Yadav
---
drivers/dma-buf/dma-fence.c | 5 -
1 file changed, 5 deletions(-)
diff
Here's enabling software signaling on fence for sw_sync.
Signed-off-by: Arvind Yadav
---
drivers/dma-buf/sw_sync.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/dma-buf/sw_sync.c b/drivers/dma-buf/sw_sync.c
index 348b3a9170fa..d2a52ceac14e 100644
--- a/drivers/dma-buf/sw_sync.c
Add AFBC support to Mediatek DRM driver and enable on MT8195.
Tested on MT8195 and confirmed both correct video output and improved DRAM
bandwidth performance.
v2:
Marked mtk_ovl_set_afbc as static, reflowed some lines to fit column
limit.
Signed-off-by: Justin Green
---
On 9/28/22 01:38, Laurent Pinchart wrote:
A couple of the register macro values are incorrectly indented. Fix
them.
Signed-off-by: Laurent Pinchart
Reviewed-by: Marek Vasut
On 9/28/22 01:38, Laurent Pinchart wrote:
The BIT() macro is meant to represent a single bit. Don't use it for
values of register fields that span multiple bits.
Signed-off-by: Laurent Pinchart
---
drivers/gpu/drm/mxsfb/lcdif_regs.h | 28 ++--
1 file changed, 14
On Thu, Sep 22, 2022 at 03:11:17PM -0700, Daniele Ceraolo Spurio wrote:
> The render and media GuCs share the same interrupt enable register, so
> we can no longer disable interrupts when we disable communication for
> one of the GuCs as this would impact the other GuC. Instead, we keep the
>
On 9/28/22 01:38, Laurent Pinchart wrote:
Up to and including v1.3, HDMI supported limited quantization range only
for YCbCr. HDMI v1.4 introduced selectable quantization ranges, but this
features isn't supported in the dw-hdmi driver that is used in
conjunction with the LCDIF in the i.MX8MP.
On 9/28/22 01:38, Laurent Pinchart wrote:
Hi,
[...]
diff --git a/drivers/gpu/drm/mxsfb/lcdif_kms.c
b/drivers/gpu/drm/mxsfb/lcdif_kms.c
index ba84b51598b3..a97a5f512aae 100644
--- a/drivers/gpu/drm/mxsfb/lcdif_kms.c
+++ b/drivers/gpu/drm/mxsfb/lcdif_kms.c
[...]
@@ -37,9 +38,10 @@ static
Hi Marek,
On Wed, Sep 28, 2022 at 02:10:26AM +0200, Marek Vasut wrote:
> On 9/28/22 01:38, Laurent Pinchart wrote:
> > The BIT() macro is meant to represent a single bit. Don't use it for
> > values of register fields that span multiple bits.
> >
> > Signed-off-by: Laurent Pinchart
> > ---
> >
Hi Marek,
On Wed, Sep 28, 2022 at 02:12:19AM +0200, Marek Vasut wrote:
> On 9/28/22 01:38, Laurent Pinchart wrote:
> > Up to and including v1.3, HDMI supported limited quantization range only
> > for YCbCr. HDMI v1.4 introduced selectable quantization ranges, but this
> > features isn't supported
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