Well first of all don't expose the VMID to userspace.
The UMD doesn't know (and shouldn't know) which VMID is used for a
submission since this is dynamically assigned and can change at any time.
For debugging there is an interface to use an reserved VMID for your
debugged process which
On Thu, Apr 27, 2023 at 10:28:13AM +0200, Thomas Hellström wrote:
>
> On 4/26/23 22:57, Rodrigo Vivi wrote:
> > The goal is to use devcoredump infrastructure to report error states
> > captured at the crash time.
> >
> > The error state will contain useful information for GPU hang debug, such
>
On Wed, Apr 26, 2023 at 04:57:12PM -0400, Rodrigo Vivi wrote:
> The goal is to allow for a snapshot capture to be taken at the time
> of the crash, while the print out can happen at a later time through
> the exposed devcoredump virtual device.
>
> Signed-off-by: Rodrigo Vivi
Also thinking out
This series adds support for GAMMA IP requiring and/or supporting
a 12-bits LUT using a slightly different register layout and programming
sequence for multiple LUT banks: this IP version is currently found
on a number of SoCs, not only including the Chromebook/IoT oriented
Kompanio 1200/1380
From: "Jason-JH.Lin"
Adjust the parameters in mtk_drm_gamma_set_common()
- add (struct device *dev) to get lut_diff from gamma's driver data
- remove (bool lut_diff) and use false as default value in the function
Signed-off-by: Jason-JH.Lin
Signed-off-by: AngeloGioacchino Del Regno
---
On 02.05.2023 03:07, Adam Ford wrote:
> This series fixes the blanking pack size and the PMS calculation. It then
> adds support to allows the DSIM to dynamically DPHY clocks, and support
> non-burst mode while allowing the removal of the hard-coded clock values
> for the PLL for imx8m
Daniel Vetter writes:
> On Mon, Jul 11, 2022 at 11:32:39PM -0400, Zack Rusin wrote:
>> From: Zack Rusin
>>
>> Cursor planes on virtualized drivers have special meaning and require
>> that the clients handle them in specific ways, e.g. the cursor plane
>> should react to the mouse movement the
On Wed, Apr 26, 2023 at 04:57:06PM -0400, Rodrigo Vivi wrote:
> These structs and definitions are only used for the guc_submit
> and they were added specifically for the parallel submission.
>
> While doing that also delete the unused struct guc_wq_item.
>
> Cc: Matthew Brost
> Signed-off-by:
On Wed, 26 Apr 2023, Rodrigo Vivi wrote:
> + drm_info(>drm, "Check your
> /sys/class/drm/card/device/devcoredump/data\n");
Drive-by comment, could use %d and xe->drm.primary->index instead of
.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
On Tue, May 2, 2023 at 9:08 AM Adam Ford wrote:
>
> This series fixes the blanking pack size and the PMS calculation. It then
> adds support to allows the DSIM to dynamically DPHY clocks, and support
> non-burst mode while allowing the removal of the hard-coded clock values
> for the PLL for
On Sat, Apr 01, 2023 at 01:54:43PM +0200, Konrad Dybcio wrote:
> Some (particularly SMD_RPM, a.k.a non-RPMh) SoCs implement A6XX GPUs
> but don't implement the associated GMUs. This is due to the fact that
> the GMU directly pokes at RPMh. Sadly, this means we have to take care
> of enabling &
On Wed, Apr 26, 2023 at 04:56:59PM -0400, Rodrigo Vivi wrote:
> Xe needs to align with other drivers on the way that the error states are
> dumped, avoiding a Xe only error_state solution. The goal is to use
> devcoredump
> infrastructure to report error states, since it produces a standardized
On Thu, 20 Apr 2023, "Nautiyal, Ankit K" wrote:
> LGTM.
>
> Reviewed-by: Ankit Nautiyal
Thanks for the reviews, pushed these a week+ ago.
BR,
Jani.
>
> On 4/6/2023 7:16 PM, Jani Nikula wrote:
>> The operator precedence between << and & is wrong, leading to the high
>> byte being completely
New SoCs, like MT8195, not only may support bigger lookup tables, but
have got a different register layout to support bigger precision:
support specifying the number of `lut_bits` for each SoC and use it
in mtk_gamma_set_common() to perform the right calculation.
Signed-off-by: AngeloGioacchino
Disable relay mode at the end of LUT programming to make sure that the
processed image goes through.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
Add support for 12-bit gamma lookup tables and introduce the first
user for it: MT8195.
While at it, also reorder the variables in mtk_gamma_set_common()
and rename `lut_base` to `lut0_base` to improve readability.
Signed-off-by: AngeloGioacchino Del Regno
---
All of the SoCs that don't have dithering control in the gamma IP
have got a GAMMA_LUT_TYPE bit that tells to the IP if the LUT is
"descending" (bit set) or "rising" (bit cleared): make sure to set
it correctly after programming the LUT.
Signed-off-by: AngeloGioacchino Del Regno
---
Move the write to DISP_GAMMA_CFG to enable the Gamma LUT to after
programming the actual table to avoid potential visual glitches during
table modification.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 13 -
1 file changed, 8
Make the code more robust and improve readability by using bitfield
macros instead of open coding bit operations.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 40 ++-
1 file changed, 25 insertions(+), 15 deletions(-)
diff --git
Newer Gamma IP have got multiple LUT banks: support specifying the
size of the LUT banks and handle bank-switching before programming
the LUT in mtk_gamma_set_common() in preparation for adding support
for MT8195 and newer SoCs.
Suggested-by: Jason-JH.Lin
[Angelo: Refactored original commit]
Newer SoCs support a bigger Gamma LUT table: wire up a callback
to retrieve the correct LUT size for each different Gamma IP.
Co-developed-by: Jason-JH.Lin
Signed-off-by: Jason-JH.Lin
[Angelo: Rewritten commit message/description + porting]
Signed-off-by: AngeloGioacchino Del Regno
---
Use drm_color_lut_extract() to avoid open-coding the bits reduction
calculations for each color channel and use a struct drm_color_lut
to temporarily store the information instead of an array of u32.
Also, slightly improve the precision of the HW LUT calculation in the
LUT DIFF case by performing
Invert the check for state->gamma_lut and move it at the beginning
of the function to reduce indentation: this prepares the code for
keeping readability on later additions.
This commit brings no functional changes.
Signed-off-by: AngeloGioacchino Del Regno
---
On 2.05.2023 09:49, Akhil P Oommen wrote:
> On Sat, Apr 01, 2023 at 01:54:43PM +0200, Konrad Dybcio wrote:
>> Some (particularly SMD_RPM, a.k.a non-RPMh) SoCs implement A6XX GPUs
>> but don't implement the associated GMUs. This is due to the fact that
>> the GMU directly pokes at RPMh. Sadly,
On 4/30/2023 1:57 PM, Dmitry Baryshkov wrote:
The function dpu_plane_sspp_update_pipe() contains code to skip enabling
the QoS and OT limitis for CURSOR pipes. However all DPU since sdm845
repurpose DMA SSPP for the cursor planes because they lack the real
CURSOR SSPP. Fix the condition to
On 01.05.23 20:47, Alex Deucher wrote:
On Mon, May 1, 2023 at 2:44 PM Felix Richter wrote:
On 01.05.23 15:27, Alex Deucher wrote:
On Mon, May 1, 2023 at 3:20 AM Felix Richter wrote:
Hi,
I am running into an issue with the integrated GPU of the Ryzen 9 7950X. It
seems to be a regression
On 4/30/2023 1:57 PM, Dmitry Baryshkov wrote:
Get rid of intermediatory configuration structure and defines. Pass the
format and the enablement bit directly to the new helper. The
WB_CDP_CNTL register ignores BIT(2), so we can write it for both SSPP
and WB CDP settings.
Signed-off-by: Dmitry
On 01.05.23 15:27, Alex Deucher wrote:
On Mon, May 1, 2023 at 3:20 AM Felix Richter wrote:
Hi,
I am running into an issue with the integrated GPU of the Ryzen 9 7950X. It
seems to be a regression from kernel version 6.1 to 6.2.
The bug materializes in from of my monitor blinking, meaning it
This adds support for OTP area access on MX30LFxG18AC chip series.
Changelog:
v1 -> v2:
* Add slab.h include due to kernel test robot error.
v2 -> v3:
* Use 'uint64_t' as input argument for 'do_div()' instead
of 'unsigned long' due to kernel test robot error.
Signed-off-by: Arseniy
On 01/05/2023 20:51, Artur Weber wrote:
> Add bindings for the S6D7AA0 LCD panel controller, including the
> S6D7AA0-LSL080AL02 panel used in the Samsung Galaxy Tab 3 8.0 family
> of tablets, and the S6D7AA0-LSL080AL03 and S6D7AA0-LTL101AT01 panels
> used in the Samsung Galaxy Tab A 8.0 and 9.7
Am 02.05.23 um 03:26 schrieb André Almeida:
Em 01/05/2023 16:24, Alex Deucher escreveu:
On Mon, May 1, 2023 at 2:58 PM André Almeida
wrote:
I know that devcoredump is also used for this kind of information,
but I believe
that using an IOCTL is better for interfacing Mesa + Linux rather
On 01/05/2023 17:58, Rob Clark wrote:
On Fri, Apr 28, 2023 at 4:05 AM Tvrtko Ursulin
wrote:
On 27/04/2023 18:53, Rob Clark wrote:
From: Rob Clark
These are useful in particular for VM scenarios where the process which
has opened to drm device file is just a proxy for the real user in a
On Wed, Apr 26, 2023 at 04:57:12PM -0400, Rodrigo Vivi wrote:
> The goal is to allow for a snapshot capture to be taken at the time
> of the crash, while the print out can happen at a later time through
> the exposed devcoredump virtual device.
>
> Signed-off-by: Rodrigo Vivi
This is an example
On 28/04/2023 15:45, Rob Clark wrote:
On Fri, Apr 28, 2023 at 3:56 AM Tvrtko Ursulin
wrote:
On 27/04/2023 18:53, Rob Clark wrote:
From: Rob Clark
Add support to dump GEM stats to fdinfo.
v2: Fix typos, change size units to match docs, use div_u64
v3: Do it in core
v4: more kerneldoc
On Tue, May 2, 2023 at 11:12 AM Timur Kristóf wrote:
>
> Hi Christian,
>
> Christian König ezt írta (időpont: 2023. máj. 2.,
> Ke 9:59):
>>
>> Am 02.05.23 um 03:26 schrieb André Almeida:
>> > Em 01/05/2023 16:24, Alex Deucher escreveu:
>> >> On Mon, May 1, 2023 at 2:58 PM André Almeida
>> >>
Create vendor specific renesas directory and move renesas drivers
to that directory.
Signed-off-by: Biju Das
Acked-by: Kieran Bingham
Reviewed-by: Laurent Pinchart
---
v8->v9:
* Added Rb tag from Laurent and Acked-by tag from Kieran.
v8:
* New patch
---
MAINTAINERS
The RZ/G2L LCD controller is composed of Frame Compression Processor
(FCPVD), Video Signal Processor (VSPD), and Display Unit (DU).
The DU module supports the following hardware features
− Display Parallel Interface (DPI) and MIPI LINK Video Interface
− Display timing master
− Generates video
RZ/G2L LCD controller composed of Frame compression Processor(FCPVD), Video
signal processor (VSPD) and Display unit(DU). The output of LCDC is
connected to Display parallel interface and MIPI link video interface.
The output from DSI is connected to ADV7535.
Created a vendor specific directory
The panel-common schema does not define what "ports" property is, so
bring the definition to enforce the type. Panels can be single- or
dual-link, thus require only one port@0.
Signed-off-by: Krzysztof Kozlowski
---
Changes since v1:
1. Rework to add ports to device schema, not to
The panel-common schema does not define what "ports" property is, so
bring the definition to enforce the type. All panels described by
binding are dual-link, thus require both ports.
Signed-off-by: Krzysztof Kozlowski
---
Changes since v1:
1. Rework to add ports to device schema, not to
Hi Christian,
Thanks for your quick reply.
On Tue, 2 May 2023 13:36:07 +0200
Christian König wrote:
> Hi Boris,
>
> Am 02.05.23 um 13:19 schrieb Boris Brezillon:
> > Hello Christian, Alex,
> >
> > As part of our transition to drm_sched for the powervr GPU driver, we
> > realized
Hi
Am 02.05.23 um 14:59 schrieb Dan Carpenter:
The "unode" pointer cannot be NULL here and checking for it causes
Smatch warnings:
drivers/gpu/drm/udl/udl_main.c:259 udl_get_urb_locked()
warn: can 'unode' even be NULL?
Fortunately, it's just harmless dead code which can be removed.
On Tue, May 2, 2023 at 7:45 AM Linux regression tracking (Thorsten
Leemhuis) wrote:
>
> [CCing the regression list, as it should be in the loop for regressions:
> https://docs.kernel.org/admin-guide/reporting-regressions.html]
>
> [TLDR: I'm adding this report to the list of tracked Linux kernel
Document DU found in RZ/V2L SoC. The DU block is identical to RZ/G2L
SoC and therefore use RZ/G2L fallback to avoid any driver changes.
Signed-off-by: Biju Das
Reviewed-by: Rob Herring
Reviewed-by: Laurent Pinchart
Reviewed-by: Geert Uytterhoeven
---
V8->v9:
* Added Rb tag from Laurent and
On Sat, Apr 29, 2023 at 12:02:46AM +0800, Jianhua Lu wrote:
> The kinetic,ktz8866 is a I2C driver, so add the missing reg property.
> And update example to make it clear.
>
> Signed-off-by: Jianhua Lu
Reviewed-by: Daniel Thompson
The "unode" pointer cannot be NULL here and checking for it causes
Smatch warnings:
drivers/gpu/drm/udl/udl_main.c:259 udl_get_urb_locked()
warn: can 'unode' even be NULL?
Fortunately, it's just harmless dead code which can be removed. It's
left over from commit c5c354a3a472 ("drm/udl:
-mediatek-gamma-Adjust-mtk_drm_gamma_set_common-parameters/20230502-161758
base: git://anongit.freedesktop.org/drm/drm-misc drm-misc-next
patch link:
https://lore.kernel.org/r/20230502081650.25947-7-angelogioacchino.delregno%40collabora.com
patch subject: [PATCH 06/11] drm/mediatek: gamma: Use
Add my self as maintainer for RZ DU drivers.
While at it, update the entries for common parts, rcar-du and shmobile.
Signed-off-by: Biju Das
Reviewed-by: Laurent Pinchart
---
v8->v9:
* Added Rb tag from Laurent.
* Updated entries for common parts(Makefile and Kconfig).
v8:
* New patch
---
The LCD controller is composed of Frame Compression Processor (FCPVD),
Video Signal Processor (VSPD), and Display Unit (DU).
It has DPI/DSI interfaces and supports a maximum resolution of 1080p
along with 2 RPFs to support the blending of two picture layers and
raster operations (ROPs).
The DU
The LCD controller is composed of Frame Compression Processor (FCPVD),
Video Signal Processor (VSPD), and Display Unit (DU).
It has DPI/DSI interfaces and supports a maximum resolution of 1080p
along with 2 RPFs to support the blending of two picture layers and
raster operations (ROPs).
The DU
Add my self as maintainer for RZ DU drivers.
While at it, update the entries for common parts, rcar-du and shmobile.
Signed-off-by: Biju Das
Reviewed-by: Laurent Pinchart
---
v8->v9:
* Added Rb tag from Laurent.
* Updated entries for common parts(Makefile and Kconfig).
v8:
* New patch
---
Create vendor specific renesas directory and move renesas drivers
to that directory.
Signed-off-by: Biju Das
Acked-by: Kieran Bingham
Reviewed-by: Laurent Pinchart
---
v8->v9:
* Added Rb tag from Laurent and Acked-by tag from Kieran.
v8:
* New patch
---
MAINTAINERS
The RZ/G2L LCD controller is composed of Frame Compression Processor
(FCPVD), Video Signal Processor (VSPD), and Display Unit (DU).
The DU module supports the following hardware features
− Display Parallel Interface (DPI) and MIPI LINK Video Interface
− Display timing master
− Generates video
RZ/G2L LCD controller composed of Frame compression Processor(FCPVD), Video
signal processor (VSPD) and Display unit(DU). The output of LCDC is
connected to Display parallel interface and MIPI link video interface.
The output from DSI is connected to ADV7535.
Created a vendor specific directory
Document DU found in RZ/V2L SoC. The DU block is identical to RZ/G2L
SoC and therefore use RZ/G2L fallback to avoid any driver changes.
Signed-off-by: Biju Das
Reviewed-by: Rob Herring
Reviewed-by: Laurent Pinchart
Reviewed-by: Geert Uytterhoeven
---
V8->v9:
* Added Rb tag from Laurent and
Hi Timur,
Am 02.05.23 um 11:12 schrieb Timur Kristóf:
Hi Christian,
Christian König ezt írta (időpont: 2023.
máj. 2., Ke 9:59):
Am 02.05.23 um 03:26 schrieb André Almeida:
> Em 01/05/2023 16:24, Alex Deucher escreveu:
>> On Mon, May 1, 2023 at 2:58 PM André Almeida
>>
Hello Christian, Alex,
As part of our transition to drm_sched for the powervr GPU driver, we
realized drm_sched_resubmit_jobs(), which is used by all drivers
relying on drm_sched right except amdgpu, has been deprecated.
Unfortunately, commit 5efbe6aa7a0e ("drm/scheduler: deprecate
Update the names of the fb_mem*() helpers to be consistent with their
regular counterparts. Hence, fb_memset() now becomes fb_memset_io(),
fb_memcpy_fromfb() now becomes fb_memcpy_fromio() and fb_memcpy_tofb()
becomes fb_memcpy_toio(). No functional changes.
Signed-off-by: Thomas Zimmermann
---
The code uses writel() and similar I/O-memory helpers. Include
the header file to get the declarations.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Sam Ravnborg
---
drivers/video/fbdev/arcfb.c | 1 +
drivers/video/fbdev/aty/atyfb.h | 2 ++
drivers/video/fbdev/wmt_ge_rops.c | 2 ++
3
Fbdev's main header file, , includes to get
declarations for I/O helper functions. From these declarations, it
later defines framebuffer I/O helpers, such as fb_{read,write}[bwlq]()
or fb_memset().
The framebuffer I/O helpers depend on the system architecture and
will therefore be moved into .
The code uses readl() and writel(). Include the header file to
get the declarations.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Sam Ravnborg
---
drivers/gpu/ipu-v3/ipu-prv.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/ipu-v3/ipu-prv.h b/drivers/gpu/ipu-v3/ipu-prv.h
index
Fix coding style. No functional changes.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Sam Ravnborg
---
drivers/video/fbdev/matrox/matroxfb_accel.c | 6 +++---
drivers/video/fbdev/matrox/matroxfb_base.h | 4 ++--
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git
Implement framebuffer I/O helpers, such as fb_read*() and fb_write*(),
in the architecture's header file or the generic one.
The common case has been the use of regular I/O functions, such as
__raw_readb() or memset_io(). A few architectures used plain system-
memory reads and writes. Sparc used
(was: fbdev: Use regular I/O function for framebuffers)
Fbdev provides helpers for framebuffer I/O, such as fb_readl(),
fb_writel() or fb_memcpy_to_fb(). The implementation of each helper
depends on the architecture, but they are all equivalent to regular
I/O functions of similar names. So use
> -Original Message-
> From: Biju Das
> Sent: Tuesday, May 2, 2023 10:56 AM
> To: David Airlie ; Daniel Vetter ; Geert
> Uytterhoeven ; Laurent Pinchart
> ; Krzysztof Kozlowski
>
> Cc: Biju Das ; Fabrizio Castro
> ; Prabhakar Mahadev Lad lad...@bp.renesas.com>;
Hi Boris,
Am 02.05.23 um 13:19 schrieb Boris Brezillon:
Hello Christian, Alex,
As part of our transition to drm_sched for the powervr GPU driver, we
realized drm_sched_resubmit_jobs(), which is used by all drivers
relying on drm_sched right except amdgpu, has been deprecated.
Unfortunately,
[CCing the regression list, as it should be in the loop for regressions:
https://docs.kernel.org/admin-guide/reporting-regressions.html]
[TLDR: I'm adding this report to the list of tracked Linux kernel
regressions; the text you find below is based on a few templates
paragraphs you might have
On 5/1/23 10:31, Arnd Bergmann wrote:
From: Arnd Bergmann
A global function without a header prototype has made it into
linux-next during the merge window:
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:6339:6: error: no
previous prototype for 'amdgpu_dm_connector_funcs_force'
On Tue, May 02, 2023 at 02:00:36PM +0200, Krzysztof Kozlowski wrote:
> description: regulator that supplies the I/O voltage
[..]
>
> + ports:
> +$ref: /schemas/graph.yaml#/properties/ports
> +
> +required:
> + - port@0
> + - port@1
Konrad has added a single DSI panel to
On 02/05/2023 14:44, Jianhua Lu wrote:
> On Tue, May 02, 2023 at 02:00:36PM +0200, Krzysztof Kozlowski wrote:
>> description: regulator that supplies the I/O voltage
> [..]
>>
>> + ports:
>> +$ref: /schemas/graph.yaml#/properties/ports
>> +
>> +required:
>> + - port@0
>> +
On Tue, May 2, 2023 at 9:34 AM Linux regression tracking (Thorsten
Leemhuis) wrote:
>
> On 02.05.23 15:13, Alex Deucher wrote:
> > On Tue, May 2, 2023 at 7:45 AM Linux regression tracking (Thorsten
> > Leemhuis) wrote:
> >
> >> On 30.04.23 13:44, Felix Richter wrote:
> >>> Hi,
> >>>
> >>> I am
On 02.05.23 15:48, Felix Richter wrote:
> On 5/2/23 15:34, Linux regression tracking (Thorsten Leemhuis) wrote:
>> On 02.05.23 15:13, Alex Deucher wrote:
>>> On Tue, May 2, 2023 at 7:45 AM Linux regression tracking (Thorsten
>>> Leemhuis) wrote:
>>>
On 30.04.23 13:44, Felix Richter wrote:
From: Ville Syrjälä
Split some overly long lines.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fdi.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c
b/drivers/gpu/drm/i915/display/intel_fdi.c
index
From: Ville Syrjälä
ICL doesn't support FEC with a x1 DP link. Make sure
we don't try to enable FEC in such cases.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp.c | 23 ---
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git
From: Ville Syrjälä
Stop dumping state while reading it out. We have a proper
place for that stuff.
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_crtc_state_dump.c| 2 ++
drivers/gpu/drm/i915/display/intel_ddi.c| 13 +++--
2 files changed, 5
From: Ville Syrjälä
We always check whether combo PHYs need to be re-initialized
after disabling DC states, which leads to log spam. Switch things
around so that we only log something when we actually have to
re-initialized a PHY.
The log spam was exacerbated by commit 41b4c7fe72b6 ("drm/i915:
From: Ville Syrjälä
Track DP enhanced framing properly in the crtc state instead
of relying just on the cached DPCD everywhere, and hook it
up into the state check and dump.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/g4x_dp.c | 10 --
From: Ville Syrjälä
On pre-TGL FEC is a port level feature, not a transcoder
level features, and it's DDI A which doesn't have it, not
trancodere A. Check for the correct thing when determining
whether FEC is supported or not.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
encoder->get_config() is not the place where the state
should be dumped. Get rid of the spam.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
From: Ville Syrjälä
There's no need to check for both eDP and fixed_mode when
deciding whether to do the pfit calculations or not.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
gcc on aarch64 reports
drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c: In function ‘mtk_hdmi_pll_set_rate’:
drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:240:52: error: ‘-mgeneral-regs-only’
is incompatible with the use of floating-point types
240 | else if (tmds_clk >= 54 * MEGA && tmds_clk
Slightly rearrainge code in dpu_plane_sspp_update_pipe() to group
QoS/LUT related functions.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
Get rid of intermediatory configuration structure and defines. Pass the
format and the enablement bit directly to the new helper. The
WB_CDP_CNTL register ignores BIT(2), so we can write it for both SSPP
and WB CDP settings.
Signed-off-by: Dmitry Baryshkov
---
Rework SSPP and WB code to use common helper for programming QoS
settings.
Signed-off-by: Dmitry Baryshkov
---
.../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 31 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 19 +
This flag is always passed to _dpu_plane_set_qos_ctrl(), so drop it and
remove corresponding conditions from the mentioned function.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 27 +++
1 file changed, 8 insertions(+), 19 deletions(-)
diff
Drop support for DPU_PLANE_QOS_VBLANK_CTRL flag. It is not used both
in upstream driver and in vendor SDE driver.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c| 8
On Wed, Apr 26, 2023 at 04:57:08PM -0400, Rodrigo Vivi wrote:
> Let's start to move our existent logs to devcoredump one by
> one. Any format change should come on follow-up work.
>
> Signed-off-by: Rodrigo Vivi
Reviewed-by: Matthew Brost
> ---
> drivers/gpu/drm/xe/xe_devcoredump.c | 7
Now as the struct dpu_hw_pipe_qos_cfg consists of only one bool field,
drop the structure and use corresponding bool directly.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 10 +++---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 13 ++---
After removal of DPU_PLANE_QOS_VBLANK_CTRL, several fields of struct
dpu_hw_pipe_qos_cfg are fixed to false/0. Drop them from the structure
(and drop the corresponding code from the functions).
The DPU_PLANE_QOS_VBLANK_AMORTIZE flag is also removed, since it is now
a NOP.
Signed-off-by: Dmitry
Reorder SSPP register definitions to sort them in the ascending order.
Move register bitfields after the register definitions.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 66 +++--
1 file changed, 34 insertions(+), 32 deletions(-)
diff
The function dpu_plane_sspp_update_pipe() contains code to skip enabling
the QoS and OT limitis for CURSOR pipes. However all DPU since sdm845
repurpose DMA SSPP for the cursor planes because they lack the real
CURSOR SSPP. Fix the condition to actually check that the plane is
CURSOR or not.
Merge SSPP and WB code programming QoS and CDP. This allows us to drop
intermediate structures and duplicate code.
Changes since v1:
- Fixed kerneldoc for _dpu_plane_set_qos_ctrl()
- Fixed danger_safe_en programming conditions (Jeykumar)
- Simplified the code surrounding setup_cdp() calls
The new binaries that support the 2-step authentication have contain the
legacy-style binary, which we can use for loading the HuC via DMA. To
find out where this is located in the image, we need to parse the meu
manifest of the GSC binary. The manifest consist of a partition header
followed by
On 02.05.23 15:13, Alex Deucher wrote:
> On Tue, May 2, 2023 at 7:45 AM Linux regression tracking (Thorsten
> Leemhuis) wrote:
>
>> On 30.04.23 13:44, Felix Richter wrote:
>>> Hi,
>>>
>>> I am running into an issue with the integrated GPU of the Ryzen 9 7950X. It
>>> seems to be a regression
On Tue, May 2, 2023 at 9:35 AM Timur Kristóf wrote:
>
> Hi,
>
> On Tue, 2023-05-02 at 13:14 +0200, Christian König wrote:
> > >
> > > Christian König ezt írta (időpont: 2023.
> > > máj. 2., Ke 9:59):
> > >
> > > > Am 02.05.23 um 03:26 schrieb André Almeida:
> > > > > Em 01/05/2023 16:24, Alex
On Tue, 02 May 2023 14:59:56 +0200,
Dan Carpenter wrote:
>
> The "unode" pointer cannot be NULL here and checking for it causes
> Smatch warnings:
>
>drivers/gpu/drm/udl/udl_main.c:259 udl_get_urb_locked()
>warn: can 'unode' even be NULL?
>
> Fortunately, it's just harmless dead code
On Wed, Apr 26, 2023 at 04:57:05PM -0400, Rodrigo Vivi wrote:
> Let's start to move our existent logs to devcoredump one by
> one. Any format change should come on follow-up work.
>
> Signed-off-by: Rodrigo Vivi
Reviewed-by: Matthew Brost
> ---
> drivers/gpu/drm/xe/xe_devcoredump.c |
On 02/05/2023 03:56, Jeykumar Sankaran wrote:
On 4/30/2023 1:57 PM, Dmitry Baryshkov wrote:
The function dpu_plane_sspp_update_pipe() contains code to skip enabling
the QoS and OT limitis for CURSOR pipes. However all DPU since sdm845
repurpose DMA SSPP for the cursor planes because they lack
On Wed, Apr 26, 2023 at 04:57:07PM -0400, Rodrigo Vivi wrote:
> The goal is to allow for a snapshot capture to be taken at the time
> of the crash, while the print out can happen at a later time through
> the exposed devcoredump virtual device.
>
> Signed-off-by: Rodrigo Vivi
> ---
>
On Sun, 30 Apr 2023 at 11:22, Linus Walleij wrote:
>
> A recent change to the OMAP driver making it use a dynamic GPIO
> base created problems with some old OMAP1 board files, among
> them Nokia 770, SX1 and also the OMAP2 Nokia n8x0.
>
> Fix up all instances of GPIOs being used for the MMC
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