ffer
> space to become available sees partial progress, rather than not
> seeing rptr advance at all until the GPU gets to the end of the
> submit that it is currently chewing on.
Acked-by: Jordan Crouse
> Signed-off-by: Rob Clark
> ---
> drivers/g
On Fri, Apr 23, 2021 at 03:08:17PM -0400, Jonathan Marek wrote:
> No one knows what this is for anymore, so just remove it.
Acked-by: Jordan Crouse
> Signed-off-by: Jonathan Marek
> ---
> drivers/gpu/drm/msm/msm_gem.c | 15 +++
> 1 file changed, 3 insertions(+
s was stil in there.
Acked-by: Jordan Crouse
> Signed-off-by: Jonathan Marek
> ---
> drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 ++--
> drivers/gpu/drm/msm/adreno/a5xx_power.c | 2 +-
> drivers/gpu/drm/msm/adreno/a5xx_preempt.c | 4 ++--
> drivers/gpu/drm/msm/adreno/a
On Fri, Apr 23, 2021 at 03:08:19PM -0400, Jonathan Marek wrote:
> Use the same logic as the userspace mapping.
>
> This fixes msm_rd with cached BOs.
>
Acked-by: Jordan Crouse
> Signed-off-by: Jonathan Marek
> ---
> drivers/gpu/drm/msm/msm_gem.c | 19 +++-
On Fri, Apr 23, 2021 at 03:08:21PM -0400, Jonathan Marek wrote:
> There shouldn't be any reason to ever use uncached over writecombine,
> so just use writecombine for MSM_BO_UNCACHED.
Extremely correct.
>
> Note: userspace never used MSM_BO_UNCACHED anyway
>
Acked-by: Jord
requirements to accept firmware 0.99.
Ugh, my ugly. .95 is the actual version that fixed it but since .99 is what is
going into the l-f repo it is fine to use that as a baseline.
Acked-by: Jordan Crouse
> Fixes: 8490f02a3ca4 ("drm/msm: a6xx: Make sure the SQE microcode is safe"
On Wed, Mar 24, 2021 at 06:23:52PM -0700, Rob Clark wrote:
> From: Rob Clark
>
> They were reading a counter that was configured to ALWAYS_COUNT (ie.
> cycles that the GPU is doing something) rather than ALWAYS_ON. This
> isn't the thing that userspace is looking for.
Ack
e of this. For
> example, after a suspend userspace needs to recalibrate it's offset
> between CPU and GPU time.
>
Acked-by: Jordan Crouse
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 +++
> drivers/gpu/drm/msm/msm_drv.c | 1 +
>
een made when porting:
> 4 is the value that's supposed to be passed, but
> log2(4) = 2. Changing the value to 16 (= 2^4) fixes
> the issue.
I like keeping it in human readable values because its easier to visually
identify how many registers are saved without doing math.
Reviewed-
On Wed, Jan 13, 2021 at 07:33:38PM +0100, AngeloGioacchino Del Regno wrote:
> From: Konrad Dybcio
>
> Port over the command from downstream to prevent undefined
> behaviour.
Reviewed-by: Jordan Crouse
> Signed-off-by: Konrad Dybcio
> Signed-off-by: AngeloGi
On Wed, Jan 13, 2021 at 07:33:39PM +0100, AngeloGioacchino Del Regno wrote:
> From: Konrad Dybcio
>
> Port over the command from downstream to prevent undefined
> behaviour.
Reviewed-by: Jordan Crouse
> Signed-off-by: Konrad Dybcio
> Signed-off-by: AngeloGi
65ca5a2cb ("drm/msm: Add A6XX device support")
Because that was my ugly.
Reviewed-by: Jordan Crouse
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 25 ++---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 8
> drivers/gpu/drm/msm/adreno/a6xx_g
> Cc: sta...@vger.kernel.org # v5.9
The joys of not having a global mutex locking everything.
Reviewed-by: Jordan Crouse
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> b/
On Wed, Jan 27, 2021 at 03:39:46PM -0800, Eric Anholt wrote:
> Now that the bug is fixed in the minimal way for stable, go make the
> code table-driven.
>
> Signed-off-by: Eric Anholt
There shouldn't be too many more OOB bits, but this is a good cleanup
regardless.
Reviewed-
On Thu, Jan 28, 2021 at 11:17:16AM -0800, Eric Anholt wrote:
> On Thu, Jan 28, 2021 at 10:52 AM Jordan Crouse wrote:
> >
> > On Wed, Jan 27, 2021 at 03:39:44PM -0800, Eric Anholt wrote:
> > > We were using the same force-poweron bit in the two codepaths, so they
> &g
On Mon, Feb 01, 2021 at 08:20:44AM -0800, Rob Clark wrote:
> On Mon, Feb 1, 2021 at 3:16 AM Will Deacon wrote:
> >
> > On Fri, Jan 29, 2021 at 03:12:59PM +0530, Sai Prakash Ranjan wrote:
> > > On 2021-01-29 14:35, Will Deacon wrote:
> > > > On Mon, Jan 11, 2021 at 07:45:04PM +0530, Sai Prakash Ran
Most a6xx targets have security issues that were fixed with new versions
of the microcode(s). Make sure that we are booting with a safe version of
the microcode for the target and print a message and error if not.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 67
Most a6xx targets have security issues that were fixed with new versions
of the microcode(s). Make sure that we are booting with a safe version of
the microcode for the target and print a message and error if not.
v2: Add more informative error messages and fix typos
Signed-off-by: Jordan Crouse
nks. I feel silly that I missed that.
Reviewed-by: Jordan Crouse
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> i
On Thu, Feb 11, 2021 at 06:50:28PM +0530, Akhil P Oommen wrote:
> On 2/10/2021 6:22 AM, Jordan Crouse wrote:
> >Most a6xx targets have security issues that were fixed with new versions
> >of the microcode(s). Make sure that we are booting with a safe version of
> >the microco
On Wed, Feb 17, 2021 at 07:14:16PM +0530, Akhil P Oommen wrote:
> On 2/17/2021 8:36 AM, Rob Clark wrote:
> >On Tue, Feb 16, 2021 at 12:10 PM Jonathan Marek wrote:
> >>
> >>Ignore nvmem_cell_get() EOPNOTSUPP error in the same way as a ENOENT error,
> >>to fix the case where the kernel was compiled
solid base that we can expand on later for even more
extensive GPU side page fault debugging capabilities.
v3: Always clear FSR even if the target driver is going to handle resume
v2: Fix comment wording and function pointer check per Rob Clark
Jordan Crouse (3):
iommu/arm-smmu: Add support for
Use the new adreno-smmu-priv fault info function to get more SMMU
debug registers and print the current TTBR0 to debug per-instance
pagetables and figure out which GPU block generated the request.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 +-
drivers/gpu/drm
later for even more
extensive GPU side page fault debugging capabilities.
v2: Fix comment wording and function pointer check per Rob Clark
Jordan Crouse (3):
iommu/arm-smmu: Add support for driver IOMMU fault handlers
drm/msm: Add an adreno-smmu-priv callback to get pagefault info
drm/msm
Use the new adreno-smmu-priv fault info function to get more SMMU
debug registers and print the current TTBR0 to debug per-instance
pagetables and figure out which GPU block generated the request.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 +-
drivers/gpu/drm
On Wed, Nov 25, 2020 at 06:24:13PM +, Robin Murphy wrote:
> On 2020-11-25 17:29, Robin Murphy wrote:
> >The only user of tlb_flush_leaf is a particularly hairy corner of the
> >Arm short-descriptor code, which wants a synchronous invalidation to
> >minimise the races inherent in trying to split
On Fri, Nov 27, 2020 at 06:19:44PM +0530, Akhil P Oommen wrote:
> So far a530v2 gpu has support for detecting its supported opps
> based on a fuse value called speed-bin. This patch makes this
> support generic across gpu families. This is in preparation to
> extend speed-bin support to a6x family.
On Wed, Dec 02, 2020 at 08:53:51PM +0530, Akhil P Oommen wrote:
> On 11/30/2020 10:32 PM, Jordan Crouse wrote:
> >On Fri, Nov 27, 2020 at 06:19:44PM +0530, Akhil P Oommen wrote:
> >>So far a530v2 gpu has support for detecting its supported opps
> >>based on a fuse v
;
> Fixes: 8907afb476ac ("drm/msm: Allow a5xx to mark the RPTR shadow as
> privileged")
> Signed-off-by: Marijn Suijten
> Tested-by: AngeloGioacchino Del Regno
>
Way better. Thanks for doing this.
Reviewed-by: Jordan Crouse
> ---
> drivers/gpu/drm/msm/adreno
Use the new adreno-smmu-priv fault info function to get more SMMU
debug registers and print the current TTBR0 to debug per-instance
pagetables and figure out which GPU block generated the request.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 +-
drivers/gpu/drm
later for even more
extensive GPU side page fault debugging capabilities.
Jordan Crouse (3):
iommu/arm-smmu: Add support for driver IOMMU fault handlers
drm/msm: Add an adreno-smmu-priv callback to get pagefault info
drm/msm: Improve the a6xx page fault handler
drivers/gpu/drm/msm/adreno
ged")
> Signed-off-by: Rob Clark
Reviewed-by: Jordan Crouse
> ---
> drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 12 +++-
> 1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> b/drivers/gpu/drm/msm/adreno/
*ERROR* timeout waiting for space in
> ringbuffer 0
>
> in the resume path.
>
> Fixes: d3a569fccfa0 ("drm/msm: a6xx: Use WHERE_AM_I for eligible targets")
> Signed-off-by: Rob Clark
Reviewed-by: Jordan Crouse
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 11 ++
On Thu, Nov 12, 2020 at 09:19:04PM +0530, Akhil P Oommen wrote:
> So far a530v2 gpu has support for detecting its supported opps
> based on a fuse value called speed-bin. This patch makes this
> support generic across gpu families. This is in preparation to
> extend speed-bin support to a6x family.
; Cc: David Airlie
> Cc: Daniel Vetter
> Cc: linux-arm-...@vger.kernel.org
> Cc: dri-devel@lists.freedesktop.org
> Cc: freedr...@lists.freedesktop.org
> Signed-off-by: Lee Jones
Reviewed-by: Jordan Crouse
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
> 1 file change
On Mon, Nov 16, 2020 at 07:40:03PM +0530, Akhil P Oommen wrote:
> On 11/12/2020 10:05 PM, Jordan Crouse wrote:
> >On Thu, Nov 12, 2020 at 09:19:04PM +0530, Akhil P Oommen wrote:
> >>So far a530v2 gpu has support for detecting its supported opps
> >>based on a fuse v
On Sat, Nov 14, 2020 at 11:30:10AM -0800, Rob Clark wrote:
> From: Rob Clark
>
> In situations where the GPU is mostly idle, all or nearly all buffer
> objects will be in the inactive list. But if the system is under memory
> pressure (from something other than GPU), we could still get a lot of
On Sat, Nov 14, 2020 at 10:17:12AM -0500, Jonathan Marek wrote:
> This makes it possible to use the non-coherent cached MSM_BO_CACHED mode,
> which otherwise doesn't provide any method for cleaning/invalidating the
> cache to sync with the device.
>
> Signed-off-by: Jonathan Marek
> ---
> driver
On Sat, Nov 14, 2020 at 11:39:45AM -0800, Rob Clark wrote:
> On Sat, Nov 14, 2020 at 10:58 AM Jonathan Marek wrote:
> >
> > On 11/14/20 1:46 PM, Rob Clark wrote:
> > > On Sat, Nov 14, 2020 at 8:24 AM Christoph Hellwig wrote:
> > >>
> > >> On Sat, Nov 14, 2020 at 10:17:12AM -0500, Jonathan Marek w
On Mon, Dec 07, 2020 at 04:12:07PM +0530, Akhil P Oommen wrote:
> Some GPUs support different max frequencies depending on the platform.
> To identify the correct variant, we should check the gpu speedbin
> fuse value. Add support for this speedbin detection to a6xx family
> along with the required
ioacchino Del Regno
>
Yep, I can see how this would be not ideal.
Reviewed-by: Jordan Crouse
> ---
> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 21 -
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +
> 2 files changed, 17 insertions(+), 9 deletions(-)
&
On Mon, Jan 11, 2021 at 09:54:12AM +0530, Sai Prakash Ranjan wrote:
> Hi Rob,
>
> On 2021-01-08 22:16, Rob Clark wrote:
> >On Fri, Jan 8, 2021 at 6:05 AM Sai Prakash Ranjan
> > wrote:
> >>
> >>On 2021-01-08 19:09, Konrad Dybcio wrote:
> Konrad, can you please test this below change without yo
ong with the required fuse details for a618 gpu.
Reviewed-by: Jordan Crouse
> Signed-off-by: Akhil P Oommen
> ---
> Changes from v2:
> 1. Made the changes a6xx specific to save space.
> Changes from v1:
> 1. Added the changes to support a618 sku to the series.
>
These are a few support changes in advance of per-instance pagetables. These
can be added to msm-next immediately since they don't require anything external
support and they are mostly benign on their own without the more aggressive
changes coming up later.
Jordan Crouse (3):
drm/msm/a
When we move to 64 bit addressing for a5xx and a6xx targets we will start
seeing pagefaults at larger addresses so format them appropriately in the
log message for easier debugging.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_iommu.c | 2 +-
1 file changed, 1 insertion(+), 1
Pass the index of the MMU domain in struct msm_file_private instead
of assuming gpu->id throughout the submit path. This clears the way
to change ctx->aspace to a per-instance pagetable.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.c| 2 ++
drivers/gpu/d
generating 32 bit addresses so switch over now to prepare
for using addresses above 4G on targets that support them.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 14 ++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 14 ++
2 files changed, 28 insertions
An error while initializing the msm driver ends up calling
drm_atomic_helper_shutdown() without first initializing the funcs
in mode_config. While I'm not 100% sure this isn't a ordering
problem in msm adding a check to drm_mode_alloc seems like
a nice and safe solution.
Signed-off-
I somewhat accidently injected an error in the DPU KMS init that caused it to
fail and a handful of NULL deferences and errors ended up popping out. Here are
some fixes in the interest of robustness.
Jordan Crouse (3):
drm/msm/dpu: Fix error recovery after failing to enable clocks
drm/msm/dpu
d, in the case of the GMU).
Instead of calling the pm_suspend function directly, use
pm_runtime_force_suspend() which should check the correct state of
runtime and call the functions on our behalf or skip them if they are
not needed.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/a
just failed to prepare/enable. Skip the current failed clock during
the unwind to to avoid the extra log spew.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_io_ut
In the failure path for dpu_kms_init() it is possible to get to the MMU
destroy function with uninitialized MMU structs. Check for NULl and skip
if needed.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions
y* handled, but missed
> clearing 'ret' resulting that hw_init() returned an error on these
> devices.
>
> Fixes: abccb9fe3267 drm/msm/a6xx: Add zap shader load
> Signed-off-by: Rob Clark
Woo, I'm glad we finally got a chance to verify this on both types of systems.
Acked
On Sun, May 12, 2019 at 03:40:26PM +0200, Boris Brezillon wrote:
> On Tue, 30 Apr 2019 09:49:51 -0600
> Jordan Crouse wrote:
>
> > On Tue, Apr 30, 2019 at 06:10:53AM -0700, Rob Clark wrote:
> > > On Tue, Apr 30, 2019 at 5:42 AM Boris Brezillon
> > > wrote:
>
power domain")
> Cc: Jordan Crouse
> Cc: Rob Clark
> Signed-off-by: Sean Paul
Reviewed-by: Jordan Crouse
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx
mplement preemption for A5XX targets")
> Cc: sta...@vger.kernel.org
> Reported-by: "Paul E. McKenney"
> Reported-by: Peter Zijlstra
> Signed-off-by: Andrea Parri
> Cc: Rob Clark
> Cc: Sean Paul
> Cc: David Airlie
> Cc: Daniel Vetter
> Cc: J
and
drm/msm: Add support to create target specific address spaces
can be merged to the msm-next tree without dependencies on the IOMMU changes.
Only the last three patches will require coordination between the two areas.
Jordan Crouse (15):
iommu/arm-smmu: Allow IOMMU enabled devices to ski
When we move to 64 bit addressing for a5xx and a6xx targets we will start
seeing pagefaults at larger addresses so format them appropriately in the
log message for easier debugging.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_iommu.c | 2 +-
1 file changed, 1 insertion(+), 1
Add a helper function to create a GEM address space attached to
an iommu auxiliary domain for a per-instance pagetable.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.h | 4 +++
drivers/gpu/drm/msm/msm_gem_vma.c | 53 +++
2 files changed
generating 32 bit addresses so switch over now to prepare
for using addresses above 4G for targets that support them.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 14 ++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 14 ++
2 files changed, 28 insertions
.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 120 +-
drivers/gpu/drm/msm/adreno/a5xx_gpu.h | 19 +
drivers/gpu/drm/msm/adreno/a5xx_preempt.c | 70 +
3 files changed, 192 insertions(+), 17 deletions(-)
diff
Pass the index of the MMU domain in struct msm_file_private instead
of assuming gpu->id throughout the submit path. This clears the way
to change ctx->aspace to a per-instance pagetable.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.c| 2 ++
drivers/gpu/d
Add support for creating a auxiliary domain from the IOMMU device to
implement per-instance pagetables. Also add a helper function to
return the pagetable base address (ttbr) and asid to the caller so
that the GPU target code can set up the pagetable switch.
Signed-off-by: Jordan Crouse
some of the target files but I think
it pays for itself in improved code flow and flexibility.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 37 --
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 50 ++
drivers/gpu/drm/msm
Targets that support per-instance pagetable switching will have to keep
track of which pagetable belongs to each instance to be able to recover
for preemption.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_ringbuffer.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu
Add support to create a GPU target specific address space for
a context. For those targets that support per-instance
pagetables they will return a new address space set up for
the instance if possible otherwise just use the global
device pagetable.
Signed-off-by: Jordan Crouse
---
drivers/gpu
Add support for per-instance pagetables for a6xx targets. Add support
to handle split pagetables and create a new instance if the needed
IOMMU support exists and insert the necessary PM4 commands to trigger
a pagetable switch at the beginning of a user command.
Signed-off-by: Jordan Crouse
et on
> successful probe and cleared on removal.
>
> Changes in v2:
> - None
>
> Cc: Jordan Crouse
> Signed-off-by: Sean Paul
Reviewed-by: Jordan Crouse
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 14 +-
> drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 1 +
he irqs_enabled flag
> it's just housekeeping.
>
> Changes in v2:
> - None
>
> Cc: Jordan Crouse
> Signed-off-by: Sean Paul
Reviewed-by: Jordan Crouse
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git
On Thu, May 23, 2019 at 01:16:42PM -0400, Sean Paul wrote:
> From: Sean Paul
>
> pdcptr and seqptr aren't necessarily valid, check them before trying to
> unmap them.
>
> Changes in v2:
> - None
>
> Cc: Jordan Crouse
> Signed-off-by: Sean Paul
It has alway
In the case of irqs, this causes failures since the irqs are
> not shared (nor should they be).
>
> This patch removes all devm_* calls and manually cleans things up in
> gmu_remove.
>
> Changes in v2:
> - Add iounmap and free_irq to gmu_probe error paths
>
> Cc: Jordan
On Thu, May 23, 2019 at 01:16:44PM -0400, Sean Paul wrote:
> From: Sean Paul
>
> of_find_device_by_node() grabs a dev reference, so make sure we clear it
> on error and remove.
>
> Changes in v2:
> - Added to the set (Jordan)
>
> Cc: Jordan Crouse
> Signed-o
or reasons laid
> out in the previous patch).
>
> Changes in v2:
> - None
>
> Cc: Jordan Crouse
> Signed-off-by: Sean Paul
Reviewed-by: Jordan Crouse
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 +-
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
> drivers
On Tue, May 28, 2019 at 11:13:39AM -0400, Sean Paul wrote:
> From: Sean Paul
>
> Instead of reaching into dev->primary for debugfs_root, use the minor
> passed into debugfs_init.
>
> This avoids creating a debug directory under /sys/kernel/debug/debug
> and instead uses /sys/kernel/debug/dri//
>
On Tue, May 28, 2019 at 02:26:45PM -0400, Sean Paul wrote:
> From: Sean Paul
>
> This comment doesn't make any sense, remove it.
>
> Suggested-by: Jordan Crouse
> Signed-off-by: Sean Paul
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 -
> 1 file cha
On Tue, May 28, 2019 at 10:06:12AM -0700, Jeffrey Hugo wrote:
> The A540 is a derivative of the A530, and is found in the MSM8998 SoC.
>
> Signed-off-by: Jeffrey Hugo
> ---
> drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 22 +++
> drivers/gpu/drm/msm/adreno/a5xx_power.c| 76 ++
remented on line 51, but without a
> corresponding object release within this function.
>
> Signed-off-by: Wen Yang
> Cc: Rob Clark
> Cc: Sean Paul
> Cc: David Airlie
> Cc: Daniel Vetter
> Cc: Jordan Crouse
> Cc: Mamta Shukla
> Cc: Thomas Zimmermann
>
Add CONFIG_DRM_MSM_GPU_STATE to conditionally compile Adreno GPU state
code depending on the availability of the dependencies.
Reported-by: Hulk Robot
Reported-by: YueHaibing
Fixes: 1707add81551 ("drm/msm/a6xx: Add a6xx gpu state")
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/m
On Thu, Apr 04, 2019 at 10:02:07AM +0800, YueHaibing wrote:
> On 2019/4/3 23:36, Jordan Crouse wrote:
> > On Wed, Apr 03, 2019 at 02:48:11PM +0800, Yue Haibing wrote:
> >> From: YueHaibing
> >>
> >> When building CONFIG_DEBUG_FS is not set
> >> gcc wa
e an informed decision about exposing
> KHR_robustness.
>
> Signed-off-by: Rob Clark
Reviewed-by: Jordan Crouse
> ---
> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 +++
> include/uapi/drm/msm_drm.h | 1 +
> 2 files changed, 4 insertions(+)
>
> diff --git
ch provides the latter.
>
> Signed-off-by: Rob Clark
Reviewed-by: Jordan Crouse
> ---
> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 +++
> drivers/gpu/drm/msm/msm_gpu.c | 3 +++
> drivers/gpu/drm/msm/msm_gpu.h | 3 +++
> include/uapi/drm/msm_drm.h
he final two patches add the DT bindings and DT settings for
setting up the reserved memory that the shader requires.
v2: Reduced the redundant log messages for targets that don't need the zap
shader
Jordan Crouse (3):
drm/msm/gpu: Move zap shader loading to adreno
drm/msm/a6xx: Add zap
a5xx and a6xx both share (mostly) the same code to load the zap shader and
bring the GPU out of secure mode. Move the formerly 5xx specific code to
adreno to make it available for a6xx too.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 111
Describe the zap-shader node that defines a reserved memory region
to store the zap shader.
Signed-off-by: Jordan Crouse
---
Documentation/devicetree/bindings/display/msm/gpu.txt | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt
b
M sequence this should fail and we would fall back
to writing the register.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 38 +-
drivers/gpu/drm/msm/adreno/adreno_device.c | 1 +
2 files changed, 38 insertions(+), 1 deletion(-)
di
Add documentation for the interconnect and interconnect-names bindings
for the GPU node as detailed by bindings/interconnect/interconnect.txt.
Signed-off-by: Jordan Crouse
Reviewed-by: Douglas Anderson
Reviewed-by: Rob Herring
Acked-by: Georgi Djakov
---
v4: Fix spelling nits per Georgi
On Tue, Apr 30, 2019 at 06:10:53AM -0700, Rob Clark wrote:
> On Tue, Apr 30, 2019 at 5:42 AM Boris Brezillon
> wrote:
> >
> > +Rob, Eric, Mark and more
> >
> > Hi,
> >
> > On Fri, 5 Apr 2019 16:20:45 +0100
> > Steven Price wrote:
> >
> > > On 04/04/2019 16:20, Boris Brezillon wrote:
> > > > Hello
Now that the GX domain is sorted we can wire up a working GMU reset.
IF a GMU hang was detected then try to forcefully shut down the GMU
in the power down sequence which should ensure that it can recover
normally on the next power up.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno
-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 82 +++---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 20 ++--
drivers/gpu/drm/msm/adreno/adreno_device.c | 1 +
3 files changed, 58 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/msm
The GMU code currently has some misguided code to try to work around
a hardware quirk that requires the power domains on the GPU be
collapsed in a certain order. Upcoming patches will do this the
right way so get rid of the unused and unwanted regulator
code.
Signed-off-by: Jordan Crouse
t is today.
Jordan Crouse (6):
drm/msm/a6xx: Remove unwanted regulator code
dt-bindings: drm/msm/a6xx: Add GX power-domain for GMU bindings
drm/msm/gpu: Attach to the GPU GX power domain
drm/msm/a6xx: Make GMU reset useful
msm/drm/a6xx: Turn off the GMU if resume fails
drm/msm/a6xx: Remove
The GMU should have two power domains defined: "cx" and "gx". "cx" is the
actual power domain for the device and "gx" will be attached at runtime
to manage reference counting on the GPU device in case of a GMU crash.
Signed-off-by: Jordan Crouse
---
D
The HFI tasklet was removed in df0dff1 ("drm/msm/a6xx: Poll for HFI
responses") but the tasklet_struct was accidentally left behind.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/
power domain and does
the magic to "enable" and disable it at the right points.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 41 ++-
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 2 ++
2 files changed, 42 insertions(+), 1 deletio
On Tue, Dec 18, 2018 at 06:50:38PM +0530, Jayant Shekhar wrote:
> Remove unused functions from dpu plane interface
> and unused variables from dpu plane state structure.
>
> Signed-off-by: Jayant Shekhar
Reviewed-by: Jordan Crouse
> ---
> drivers/gpu/drm/msm/disp/dpu
On Tue, Dec 18, 2018 at 11:22:01AM -0600, Rob Herring wrote:
> On Fri, Dec 14, 2018 at 03:16:39PM -0700, Jordan Crouse wrote:
> > Add documentation for the interconnect and interconnect-names bindings
> > for the GPU node as detailed by bindings/interconnect/interconnect.txt.
>
Each GPU core only uses one interrupt so we don't to look up
an interrupt by name and thereby we don't need interrupt-names.
Signed-off-by: Jordan Crouse
---
Documentation/devicetree/bindings/display/msm/gpu.txt | 1 -
1 file changed, 1 deletion(-)
diff --git a/Documentation/
Every GPU core only has one interrupt so there isn't any
value in looking up the interrupt by name. Remove the name (which
is legacy anyway) and use platform_get_irq() instead.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 1 -
drivers/gpu/drm/msm/msm_
'interrupt-names' shouldn't be used in cases when there is only
one interrupt and it is not otherwise used in the driver.
Signed-off-by: Jordan Crouse
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dts
'interrupt-names' shouldn't be used in cases when there is only
one interrupt and it is not otherwise used in the driver.
Signed-off-by: Jordan Crouse
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi
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