> using any GEN6_RING_FAULT_REG_* one GRAPHICS_VER >= 8.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
> not used.
s/when not used/for engines that only exist on gen8+ platforms/
Reviewed-by: Matt Roper
For historical reference, we did use hw_id on gen8+ platforms too until
relatively recently --- it was used to set the engine's guc_id as well
up until:
commit c784e5249e773689e3
s actually not
> used in recent platforms.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
although if we apply patch #4 we could probably drop this intermediate
step.
Matt
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c| 12 ++--
> drivers
r to someone reading it down the road,
you could always do something explicit like:
#define _RING_FAULT_REG_RCS0x4094
#define _RING_FAULT_REG_VCS0x4194
#define _RING_FAULT_REG_BCS0x4294
#define _RING_FAULT_REG_VECS 0x4394
#define RING_FAULT_REG(engine)
to intel_ddi_init(): the only platform with that display version
> is already handled separately (GLK).
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_bios.c| 6 +++---
> drivers/gpu/drm/i915/display/intel_display.
eset_calc_cdclk;
> - dev_priv->display.calc_voltage_level = cnl_calc_voltage_level;
> - dev_priv->cdclk.table = cnl_cdclk_table;
> } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
> dev_priv->display.bw_calc_min_cdclk = skl_bw_c
Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
On Fri, Jul 23, 2021 at 05:10:51PM -0700, Lucas De Marchi wrote:
> No need for special CNL handling as there is no real platform with that
> configuration.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_crtc.c | 2 +-
&g
rdingly to use ICL prefix.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
> ---
> .../gpu/drm/i915/display/intel_combo_phy.c| 106 --
> 1 file changed, 20 insertions(+), 86 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel
i915/display: Simplify GLK display version tests")
> Cc: Matt Roper
> Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/intel_device_info.c | 9 +
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/
he highest number of slices comes from SKL
> and BDW with 3 slices. Recent platforms actually increase the
> number of subslices so the number of slices remain 1.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_sseu.c | 79 -
On Fri, Jul 23, 2021 at 05:10:54PM -0700, Lucas De Marchi wrote:
> Remove DMC firmware for CNL.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_dmc.c | 9 -
> 1 file changed, 9 deletions(-)
>
> diff --gi
rc_is_wanted(struct intel_guc *guc)
> +{
> + return guc->submission_selected && intel_guc_rc_is_supported(guc);
> +}
> +
> +static inline bool intel_guc_rc_is_used(struct intel_guc *guc)
> +{
> + return intel_guc_submission_is_used(guc) && intel_guc_rc_is_wanted(guc);
> +}
> +
> +int intel_guc_rc_enable(struct intel_guc *guc);
> +int intel_guc_rc_disable(struct intel_guc *guc);
> +
> +#endif
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.h
> b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
> index 925a58ca6b94..866b462821c0 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
> @@ -7,6 +7,7 @@
> #define _INTEL_UC_H_
>
> #include "intel_guc.h"
> +#include "intel_guc_rc.h"
> #include "intel_guc_submission.h"
> #include "intel_guc_slpc.h"
> #include "intel_huc.h"
> @@ -85,6 +86,7 @@ uc_state_checkers(guc, guc);
> uc_state_checkers(huc, huc);
> uc_state_checkers(guc, guc_submission);
> uc_state_checkers(guc, guc_slpc);
> +uc_state_checkers(guc, guc_rc);
>
> #undef uc_state_checkers
> #undef __uc_state_checker
> --
> 2.25.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
On Tue, Jul 27, 2021 at 09:18:08AM -0700, Belgaumkar, Vinay wrote:
>
>
> On 7/27/2021 8:37 AM, Matt Roper wrote:
> > On Mon, Jul 26, 2021 at 12:08:00PM -0700, Vinay Belgaumkar wrote:
> > > This feature hands over the control of HW RC6 to the GuC.
> > > GuC deci
. Either way:
> > Reviewed-by: John Harrison
>
> Either is fine with me.
>
> Acked-by: Daniel Vetter
>
Applied to drm-intel-gt-next (with the suggested debug message wording
tweak). Thanks for the patch and reviews.
Matt
> >
> > > + return -EN
;
> > > Commit
> > >
> > > db47fe727e1f ("drm/i915/step: s/_revid_tbl/_revids")
> > >
> > > is missing a Signed-off-by from its committer.
> > >
> > > --
> > > Cheers,
> > > Stephen Rothwell
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
On Wed, Aug 11, 2021 at 11:48:00AM +0200, Daniel Vetter wrote:
> On Wed, Aug 11, 2021 at 10:16:41AM +0300, Jani Nikula wrote:
> > On Tue, 10 Aug 2021, Daniel Vetter wrote:
> > > On Mon, Aug 09, 2021 at 09:19:39AM -0700, Matt Roper wrote:
> > >> On Mon, Aug 09, 20
ciids.h).
Thanks!
Matt
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
ctor out function to read RP_STATE_CAP
Matt Roper (29):
drm/i915/xehp: Xe_HP forcewake support
drm/i915/xehp: Define multicast register ranges
drm/i915/xehp: Loop over all gslices for INSTDONE processing
drm/i915/xehpsdv: Add maximum sseu limits
drm/i915/xehpsdv: Define steering tables
drm/i
bspec
describes as 'SQIDI' since all instances of those registers will always
be present and we'll always be able to read back a workaround value that
was written with multicast.
Bspec: 66534
Cc: José Roberto de Souza
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/inte
Implement Xe_HP forcewake handling. While we're at it, let's reorder to
the forcewake assignment if/else ladder to match our usual driver
conventions.
Co-authored-by: Daniele Ceraolo Spurio
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
Signed-off-by:
From: John Harrison
Xe_HP can have a lot of extra media engines. This patch adds the
interrupt handler support for them.
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Signed-off-by: John Harrison
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 13
s a feature that
started with DG1 and is true for all DGFX platforms, it's also true for
XE_HP in general.
Signed-off-by: Lucas De Marchi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_pci.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/gpu/
always have SFC, odd
numbered physical instances have SFC only if previous even instance is
fused off.
Bspec: 48028
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Signed-off-by: Venkata Sandeep Dhanalakota
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 30
as a separate field from
graphics_ver.
Also, currently there is not much use for the release id in media and
display, so keep them out.
This is a mix of 2 independent changes: one by me and the other by Matt
Roper.
Cc: Matt Roper
Signed-off-by: Lucas De Marchi
Signed-off-by: Matt Roper
---
-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_drv.h | 27
drivers/gpu/drm/i915/i915_pci.c | 16 ++
drivers/gpu/drm/i915/intel_device_info.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 5 +
drivers/gpu/drm/i915/intel_step.c
ff-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 9d1c99c9c0dd..d640fd37792f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/dr
From: John Harrison
Xe_HP can have a lot of extra media engines. This patch adds the reset
support for them.
Signed-off-by: John Harrison
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_reset.c | 6 ++
drivers/gpu/drm/i915/i915_reg.h | 8
2 files changed, 14
for the device.
The goal of this patch set is to minimize the amount of impact to prior
generations while still giving the user maximum flexibility.
Bspec: 33117, 33118, 20376
Cc: Daniele Ceraolo Spurio
Cc: Matt Roper
Signed-off-by: Stuart Summers
Signed-off-by: Steve Hampson
Signed-off-by
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: José Roberto de Souza
Signed-off-by: Stuart Summers
Signed-off-by: Tomas Winkler
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_drv.h | 10 ++
drivers/gpu/drm/i915/i915_pci.c | 20
DG2 supports compute DSS and has the same maximum number of DSS and EU
as XeHP SDV.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c
b/drivers/gpu/drm/i915/gt/intel_sseu.c
valid for DG2-G11, we'll just
initialize the MCFG and SF steering registers to a constant value of "2"
for all XeHP-based platforms for simplicity --- that will work in all
cases.
Bspec: 66534
Cc: Radhakrishna Sripada
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_workarou
pointer dereference issue.
Cc: Manasi Navare
Signed-off-by: Animesh Manna
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_display.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display
From: Prathap Kumar Valsan
The layout of some engine contexts has changed on Xe_HP. Define the new
offsets.
Bspec: 45585, 46256
Signed-off-by: Prathap Kumar Valsan
Signed-off-by: Ramalingam C
Signed-off-by: Venkata Ramana Nayana
Signed-off-by: Akeem G Abodunrin
Signed-off-by: Matt Roper
as De Marchi
Signed-off-by: Matt Roper
Signed-off-by: Vandita Kulkarni
Signed-off-by: Jani Nikula
Signed-off-by: Nidhi Gupta
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 1 +
.../drm/i915/display/intel_display_types.h| 17 +-
le Ceraolo Spurio
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Stuart Summers
Signed-off-by: Prasad Nallani
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 24
drivers/gpu/drm/i915/i915_getparam.c | 6 --
drivers/gpu/drm/i915/i915_reg.h
hold all of the values. XeHP
design has 8 gslices, whereas older platforms never had more than 3
slices.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 48 +++-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 12 -
drivers/gpu/drm/i915/gt
Cc: Stuart Summers
Signed-off-by: Paulo Zanoni
Signed-off-by: Lucas De Marchi
Signed-off-by: Tomasz Lis
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_drv.h | 2 -
drivers/gpu/drm/i915/i915_irq.c | 139 +++
drivers/gpu/drm/i915/i915_pci.c |
Note that DG2 only has a single possible refclk frequency (38.4 MHz).
Bspec: 54034
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 24 --
1 file changed, 22 insertions(+), 2 deletions(-)
diff
As with DG1, DG2 has an ICL-style south display interface provided on
the same PCI device. Add a fake PCH to ensure DG2 takes the appropriate
codepaths for south display handling.
Bspec: 54871, 50062, 49961, 53673
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
Signed-off-by: Aditya Swarup
ingle default steering
value that satisfies the fusing of all types.
Bspec: 66534
Cc: Tvrtko Ursulin
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 40 -
drivers/gpu/drm/i915/gt/intel_gt.h | 1 +
drivers/gpu/drm
Xe_HPG adds some additional INSTDONE_GEOM debug registers; the Mesa team
has indicated that having these reported in the error state would be
useful for debugging GPU hangs. These registers are replicated per-DSS
with gslice steering.
Cc: Lionel Landwerlin
Signed-off-by: Matt Roper
From: John Harrison
Increasing the engine count causes a couple of local array variables
to exceed the kernel stack limit. So make them dynamic allocations
instead.
Signed-off-by: John Harrison
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt
Due to the removal of legacy slices and the transition to a
gslice/cslice/mslice/etc. design, we'll internally store all DSS under
"slice0."
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 5 -
drivers/gpu/drm/i915/gt/intel_sseu.h | 2 +-
DG2 has outputs on DDI A-D attached to what the bspec diagram shows as
"Combo PHY A-D." Note that despite being labelled "combo" the PHYs on
these outputs are Synopsys PHYs rather than traditional Intel combo PHY
technology.
Cc: Anusha Srivatsa
Signed-off-by: Matt Roper
ngle dummy QGV point with the proper amount of memory bandwidth,
rather than trying to query the pcode for this information.
Bspec: 64631
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_bw.c | 24 +++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git
te functions and don't need to
spin up a separate DG2 instance.
Bspec: 66534
Cc: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/intel_uncore.c | 305 +++-
1 file changed, 168 insertions(+), 137 deletions(-)
diff --git a/drivers/gpu/drm/i91
to make any changes. using the legacy meaning is the correct
thing to do. If/when we have userspace consumers that want to utilize
third-level batch nesting, we can provide a context parameter to allow
them to opt-in.
Bspec: 45974, 45718
Cc: John Harrison
Signed-off-by: Matt Roper
---
drivers
Although the BW_BUDDY registers still exist, they are not used for
anything on DG2. This change is expected to hold true for future dgpu's
too.
Bspec: 49218
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_display_power.c | 4
1 file changed, 4 insertions(+)
diff --
islav Lisovskiy
Signed-off-by: Matt Roper
---
.../drm/i915/display/intel_display_power.h| 4 +
drivers/gpu/drm/i915/intel_pm.c | 120 +-
2 files changed, 123 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
b/drivers/gpu/drm
The RP_STATE_CAP register is no longer part of the MCHBAR on XEHPSDV; this
register is now a per-tile register at GTTMMADDR offset 0x250014.
Cc: Rodrigo Vivi
Signed-off-by: Matt Roper
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/intel_rps.c | 4 +++-
drivers/gpu/drm/i915
45101
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
Signed-off-by: Stuart Summers
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_mocs.c | 33 +++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
Define and initialize the MMIO ranges for which XeHP SDV requires MSLICE
and LNCF steering.
Bspec: 66534
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 19 ++-
drivers/gpu/drm/i915/gt
all accepted values
Cc: Vandita Kulkarni
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
Signed-off-by: Patnana Venkata Sai
Signed-off-by: Matt Roper
---
.../drm/i915/display/intel_display_debugfs.c | 103 +-
.../drm/i915/display/intel_display_types.h| 1 +
2 files
From: Anusha Srivatsa
Set compress BPP in kernel while connector DP or eDP
Cc: Vandita Kulkarni
Cc: Navare Manasi D
Signed-off-by: Anusha Srivatsa
Signed-off-by: Patnana Venkata Sai
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_dp.c | 23 ++-
1 file
From: Lucas De Marchi
Instead of maintaining the same if ladder in 3 different places, add a
function to read RP_STATE_CAP.
Signed-off-by: Lucas De Marchi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 8 +++-
drivers/gpu/drm/i915/gt/intel_rps.c | 17
Bspec: 45101, 45427
Cc: Ramalingam C (v5)
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_mocs.c | 35 +++-
1 file changed, 34 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
b/drivers/gpu/drm/i915/gt/intel_mocs.c
index
From: John Harrison
Xe_HP can have a lot of extra media engines. This patch adds the basic
definitions for them.
Cc: Tvrtko Ursulin
Signed-off-by: John Harrison
Signed-off-by: Tomas Winkler
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 7 ++-
drivers/gpu/drm
: 54128
Cc: Lucas De Marchi
Cc: Anusha Srivatsa
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_ddi.c | 135 +--
1 file changed, 127 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_d
Vswing programming for SNPS PHYs is just a single step -- look up the
value that corresponds to the voltage level from a table and program it
into the SNPS_PHY_TX_EQ register.
Bspec: 53920
Cc: Matt Atwood
Signed-off-by: Matt Roper
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display
for DG2, in
order to use it for live_lrc_fixed selftest.
Cc: Chris P Wilson
Cc: Prathap Kumar Valsan
Signed-off-by: Akeem G Abodunrin
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 85 -
1 file changed, 83 insertions(+), 2 deletions(-)
diff --git
At the moment we don't have a proper algorithm that can be used to
calculate PHY settings for arbitrary HDMI link rates. The PHY tables
here should support the regular modes of real-world HDMI monitors.
Bspec: 54032
Cc: Matt Atwood
Signed-off-by: Matt Roper
Signed-off-by: Vandita Kul
sing masks before processing them.
Bspec: 33288
Cc: Daniele Ceraolo Spurio
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/d
down legacy
programming paths, so just return false from it on DG2. Instead add a
new intel_phy_is_snps() that will return true for all DG2 PHYs.
Cc: Anusha Srivatsa
Cc: Matt Atwood
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_display.c | 26 +++-
Initialization of the PHY is handled by the hardware/firmware, but the
driver should wait up to 25ms for the PHY to report that its calibration
has completed.
Bspec: 49189
Bspec: 50107
Cc: Matt Atwood
Signed-off-by: Matt Roper
---
.../gpu/drm/i915/display/intel_display_power.c| 5
From: Gwan-gyeong Mun
The PSR enable/disable sequences now require that we program an extra
register in the PHY to adjust the lane disable power setting.
Bspec: 49274
Bspec: 53885
Cc: Anusha Srivatsa
Signed-off-by: Matt Roper
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display
From: Ankit Nautiyal
Add the functions to configure HDMI2.1 pcon for DG2, before DP link
training.
Signed-off-by: Ankit Nautiyal
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display
On DG2 we're supposed to just wait 600us after programming the well
before moving on; there won't be an ack from the hardware.
Bspec: 49296
Signed-off-by: Matt Roper
---
.../gpu/drm/i915/display/intel_display_power.c | 16
.../gpu/drm/i915/display/intel_display_powe
From: José Roberto de Souza
PSR2 is not supported on DG2.
Cc: Caz Yokoyama
Cc: Gwan-gyeong Mun
Signed-off-by: José Roberto de Souza
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_psr.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm
DG2 has no shared DPLL's or DDI clock muxing. The Port PLL is embedded
within the PHY.
Bspec: 54032
Bspec: 54034
Cc: Lucas De Marchi
Cc: Mohammed Khajapasha
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_display.c | 10 +++---
drivers/gpu/drm/i915/di
DG2 does not use system DRAM information for BW_BUDDY programming or
watermark workarounds, so there's no need to read this out at startup.
Cc: Anusha Srivatsa
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/intel_dram.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
From: Stuart Summers
Xe_HP changes the format of the context ID from past platforms.
Cc: Robert M. Fosha
Signed-off-by: Stuart Summers
Signed-off-by: Umesh Nerlige Ramappa
Signed-off-by: Matt Roper
---
.../drm/i915/gt/intel_execlists_submission.c | 74 ---
drivers/gpu/drm
the
> last users so we can remove the macros.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_migrate.c | 20 ++--
> 1 file changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i
t users so
> we can remove the macros.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
I think the third change here is just one we somehow missed during the
previous conversion rather than a new use, right?
> ---
> drivers/gpu/drm/i915/display/intel_display_debugfs
On Wed, Jul 07, 2021 at 11:13:25AM -0700, Lucas De Marchi wrote:
> Now that all the codebase is converted to the new *VER macros, remove
> the old GEN ones.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
We're still going to need another patch or two to kill o
whether each DSS is accessible for geometry and/or compute.
- Rename "rcs_topology" to "sseu_topology" since the information
reported is common to both RCS and CCS engines now.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 48 +-
irement for sseu
topology. We'll also document some of the constants to make it a little
bit more clear what they represent.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_engine_types.h | 2 +-
drivers/gpu/drm/i915/gt/intel_sseu.h | 47 +++-
2 files chan
On Fri, Mar 11, 2022 at 11:00:09AM -0800, Lucas De Marchi wrote:
> On Thu, Mar 10, 2022 at 10:15:42PM -0800, Matt Roper wrote:
> > Xe_HP removed "slice" as a first-class unit in the hardware design.
> > Instead we now have a single pool of subslices (which are now refer
On Fri, Mar 11, 2022 at 12:38:17PM -0800, Matt Roper wrote:
> On Fri, Mar 11, 2022 at 11:00:09AM -0800, Lucas De Marchi wrote:
> > On Thu, Mar 10, 2022 at 10:15:42PM -0800, Matt Roper wrote:
> > > Xe_HP removed "slice" as a first-class unit in the hardware design.
On Fri, Mar 11, 2022 at 11:01:01PM +0200, Ville Syrjälä wrote:
> On Fri, Mar 11, 2022 at 12:52:33PM -0800, Lucas De Marchi wrote:
> > On Fri, Mar 11, 2022 at 12:43:40PM -0800, Matt Roper wrote:
> > >On Fri, Mar 11, 2022 at 12:38:17PM -0800, Matt Roper wrote:
> > >>
save/restore list
Matt Roper (2):
drm/i915: Report steering details in debugfs
drm/i915: Add support for steered register writes
drivers/gpu/drm/i915/gt/intel_gt.c | 75 +
drivers/gpu/drm/i915/gt/intel_gt.h | 5 ++
drivers/gpu/drm/i915/gt/intel_gt_debu
soon, so the information reported here will become
increasingly valuable once that happens.
Cc: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.c | 46 +
drivers/gpu/drm/i915/gt/intel_gt.h | 2 +
drivers/gpu/drm/i915/gt
ering, we set the
steering for all entries in the guc list that do not require a special
steering (e.g. mslice) to the default settings; this will cost us a few
extra writes during engine reset but allows us to keep the steering
logic simple.
Cc: John Harrison
Cc: Matt Roper
Signed-off-by: Da
2013088509 suggests that
we leave the multicast bit enabled when performing read operations, so
we follow suit here.
Cc: Harish Chegondi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/intel_uncore.c | 75 ++---
drivers/gp
d-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 22 +---
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
index 6b944de48666..2d5d011e01db 100644
soon, so the information reported here will become
increasingly valuable once that happens.
v2:
- Adding missing 'static' on intel_steering_types[] (Jose, sparse)
Cc: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
Reviewed-by: José Roberto de Souza
---
drivers/gpu/d
hosting 2 8 bit numbers to holding a
> > > i915_engine_class_instance struct
> > >
> > > Cc: Ashutosh Dixit
> > > Cc: Matt Roper
> > > Cc: Joonas Lahtinen
> > > UMD (mesa):
> > > https://gitlab.freedesktop.org/mesa/mesa/-/merge_req
the only places we're using
that value are the programming of BLIT_CCTL (bspec 45807) and
RING_CMD_CCTL (bspec 45826), both of which are supposed to be using
GO:Memory instead of GO:L3. So maybe we should fix the uc_index value
for those platforms and then use "rq->engine->gt->mocs.uc_index << 1"
here. Might be worth renaming the field to "uc_index_gomemory" just to
make it more explicit what it's representing to prevent mistakes during
enablement of future platforms.
Matt
> + cs = i915_flush_dw(cs, offset, MI_FLUSH_LLC | MI_FLUSH_CCS);
> +
> + if (ccs_ring_size & 1)
> + *cs++ = MI_NOOP;
> + }
> intel_ring_advance(rq, cs);
> return 0;
> }
> @@ -711,7 +848,7 @@ intel_context_migrate_clear(struct intel_context *ce,
> if (err)
> goto out_rq;
>
> - err = emit_clear(rq, offset, len, value);
> + err = emit_clear(rq, offset, len, value, is_lmem);
>
> /* Arbitration is re-enabled between requests. */
> out_rq:
> --
> 2.20.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
g., I think a lot of these were based
on feedback from Tvrtko?
>
> Signed-off-by: Michael Cheng
Change appears to accurately implement the same type of cache flush as
what we have on the x86 backend.
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/drm_cache.c | 6 ++
> 1 file changed,
this function is only used from a selftest, not
from real driver codepaths, so the extra flushing shouldn't have any
negative impact on end users.
Reviewed-by: Matt Roper
> Signed-off-by: Michael Cheng
> ---
> drivers/gpu/drm/i915/gt/intel_engine.h | 13 -
> 1 file
ssues a clflush for the first and last entries
rather than the range from 0..reset_value, but since there are only a
maximum of 12 u64 entries, which fits into two cachelines, the end
result should be the same either way.
Reviewed-by: Matt Roper
>
> /* Once more for luck and our trusty paranoia */
> ENGINE_WRITE(engine, RING_CONTEXT_STATUS_PTR,
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
64 depending on architecture). Not that it will really
change the behavior since it all works out to a single cacheline in the
end.
Aside from that,
Reviewed-by: Matt Roper
>
> inactive = process_csb(engine, inactive); /* drain preemption events */
>
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
e ordering of clflush wrt to the system.
>*/
> if (flushes & CLFLUSH_AFTER)
> - clflushopt(addr);
> + drm_clflush_virt_range(addr, sizeof(addr));
Ditto.
Aside from those,
Reviewed-by: Matt Roper
> } else
>
On Thu, Feb 10, 2022 at 10:36:36AM -0800, Michael Cheng wrote:
> Replace all occurrence of cache_clflush_range with drm_clflush_virt_range.
> This will prevent compile errors on non-x86 platforms.
>
> Signed-off-by: Michael Cheng
Reviewed-by: Matt Roper
> ---
> drive
ed out.
Daniele Ceraolo Spurio (3):
drm/i915/xehp: compute engine pipe_control
drm/i915/xehp/guc: enable compute engine inside GuC
drm/i915/xehp: handle fused off CCS engines
Matt Roper (8):
drm/i915/xehp: Define compute class and engine
drm/i915/xehp: CCS shares the render reset domain
bits must not be set
Bspec: 47112
Cc: Vinay Belgaumkar
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Aravind Iddamsetty
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 35 +++-
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 15 +
2
: Daniele Ceraolo Spurio
Cc: Tvrtko Ursulin
Cc: Vinay Belgaumkar
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Aravind Iddamsetty
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_engine.h | 2 ++
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 17
damsetty
Signed-off-by: Matt Roper
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 8 +---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 ++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
drivers/gpu/drm
-off-by: Matt Roper
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 3190b7b462a9..3150c0847f65 100644
--- a/drivers/gpu
and CCS3 are in a new one.
BSpec: 50844, 54029, 54030, 53223, 53224.
Original-author: Michel Thierry
Cc: Tvrtko Ursulin
Cc: Vinay Belgaumkar
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Aravind Iddamsetty
Signed-off-by: Matt Roper
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915
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