On 15 March 2018 at 09:40, Marc Zyngier wrote:
> On 15/03/18 07:30, Ard Biesheuvel wrote:
>> On 15 March 2018 at 07:11, Guo Heyi wrote:
>>> Hi Marc and Ard,
>>>
>>> I found the timer re-enable code was added by Ard for special reason:
>>>
>>> commit
On 15 March 2018 at 07:11, Guo Heyi wrote:
> Hi Marc and Ard,
>
> I found the timer re-enable code was added by Ard for special reason:
>
> commit b1a633434ddc5fc28de817debd963f7845fb78c7
> Author: Ard Biesheuvel
> Date: Thu Sep 18 21:16:47 2014
Hi Marc and Ard,
I found the timer re-enable code was added by Ard for special reason:
commit b1a633434ddc5fc28de817debd963f7845fb78c7
Author: Ard Biesheuvel
Date: Thu Sep 18 21:16:47 2014 +
ArmPkg/TimerDxe: add workaround for KVM timer interrupt handling
On 14 March 2018 at 07:45, Marc Zyngier wrote:
> On Wed, 14 Mar 2018 00:25:09 +,
> Guo Heyi wrote:
>>
>> On Tue, Mar 13, 2018 at 09:33:33AM +, Marc Zyngier wrote:
>> > On 13/03/18 00:31, Heyi Guo wrote:
>> > > If timer interrupt is level sensitive, reloading timer
On Wed, 14 Mar 2018 00:25:09 +,
Guo Heyi wrote:
>
> On Tue, Mar 13, 2018 at 09:33:33AM +, Marc Zyngier wrote:
> > On 13/03/18 00:31, Heyi Guo wrote:
> > > If timer interrupt is level sensitive, reloading timer compare
> > > register has a side effect of clearing GIC pending status, so a
On Tue, Mar 13, 2018 at 09:33:33AM +, Marc Zyngier wrote:
> On 13/03/18 00:31, Heyi Guo wrote:
> > If timer interrupt is level sensitive, reloading timer compare
> > register has a side effect of clearing GIC pending status, so a "ISB"
> > is needed to make sure this instruction is executed
On 13/03/18 00:31, Heyi Guo wrote:
> If timer interrupt is level sensitive, reloading timer compare
> register has a side effect of clearing GIC pending status, so a "ISB"
> is needed to make sure this instruction is executed before enabling
> CPU IRQ, or else we may get spurious timer interrupts.
If timer interrupt is level sensitive, reloading timer compare
register has a side effect of clearing GIC pending status, so a "ISB"
is needed to make sure this instruction is executed before enabling
CPU IRQ, or else we may get spurious timer interrupts.
Contributed-under: TianoCore Contribution
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