Hi,
> Okay, my vote is 0x8000_ (2GB) then.
>
> I will modify the patch as follows: simultaneously with programming the
> exbar at 2GB, I will lower the start of the 32-bit PCI aperture from the
> current 3GB (0xC000_) to (2GB+256MB == 0x9000_). Is that alright?
Yes, that should
Thank you for this message! Some comments below:
On 03/07/16 09:47, Gerd Hoffmann wrote:
> Hi,
>
>> PCI: MMCONFIG at [mem 0xb000-0xbfff] reserved in E820
>
> Ok, I see you mimic seabios behavior here, resulting in a somewhat odd
> memory layout (not your fault, of course).
>
>
Hi,
> PCI: MMCONFIG at [mem 0xb000-0xbfff] reserved in E820
Ok, I see you mimic seabios behavior here, resulting in a somewhat odd
memory layout (not your fault, of course).
Short history lesson:
Traditional i440fx memory layout (before we did gigabyte alignment) was
memory up to
On 03/06/16 11:54, Marcel Apfelbaum wrote:
> On 03/04/2016 04:46 PM, Laszlo Ersek wrote:
>> The comments in the code should speak for themselves; here we note only
>> two facts:
>>
>> - The PCI config space writes (to the PCIEXBAR register) are performed
>>using the 0xCF8 / 0xCFC IO ports, by
On 03/04/2016 04:46 PM, Laszlo Ersek wrote:
The comments in the code should speak for themselves; here we note only
two facts:
- The PCI config space writes (to the PCIEXBAR register) are performed
using the 0xCF8 / 0xCFC IO ports, by virtue of PciLib being resolved to
BasePciLibCf8.
5 matches
Mail list logo
