Re: [edk2] [PATCH] Maintainers.txt: Add Giri as 2nd maintainer

[Mudusuru, Giri P]

Thanks Jiewen. 

Reviewed-by: Giri P Mudusuru  

> -Original Message-
> From: Yao, Jiewen
> Sent: Tuesday, September 6, 2016 6:21 PM
> To: edk2-devel@lists.01.org
> Cc: Mudusuru, Giri P ; Chan, Amy
> 
> Subject: [PATCH] Maintainers.txt: Add Giri as 2nd maintainer
> 
> Add Giri as 2nd maintainer to IntelFsp2*Pkg and IntelSiliconPkg.
> 
> Cc: Giri P Mudusuru 
> Cc: Amy Chan 
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Jiewen Yao 
> ---
>  Maintainers.txt | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/Maintainers.txt b/Maintainers.txt
> index b2e679d..6ac7085 100644
> --- a/Maintainers.txt
> +++ b/Maintainers.txt
> @@ -130,10 +130,12 @@ M: Jeff Fan 
>  IntelFsp2Pkg
>  W: https://github.com/tianocore/tianocore.github.io/wiki/IntelFsp2Pkg
>  M: Jiewen Yao 
> +M: Giri P Mudusuru 
> 
>  IntelFsp2WrapperPkg
>  W:
> https://github.com/tianocore/tianocore.github.io/wiki/IntelFsp2WrapperPkg
>  M: Jiewen Yao 
> +M: Giri P Mudusuru 
> 
>  IntelFspPkg
>  W: https://github.com/tianocore/tianocore.github.io/wiki/IntelFspPkg
> @@ -146,6 +148,7 @@ M: Jiewen Yao 
>  IntelSiliconPkg
>  W: https://github.com/tianocore/tianocore.github.io/wiki/IntelSiliconPkg
>  M: Jiewen Yao 
> +M: Giri P Mudusuru 
> 
>  MdeModulePkg
>  W: https://github.com/tianocore/tianocore.github.io/wiki/MdeModulePkg
> --
> 2.7.4.windows.1

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Re: [edk2] [PATCH v2 1/3] MdePkg/BaseMemoryLib: widen aligned accesses to 32 or 64 bits

[Gao, Liming]

Ard:
In InternalMemSetMem, Value64 = (((UINT64)Value32) << 32) | Value32; may cause 
the below link error with VS IA32 build. It (<<) should be replaced by BaseLib 
LShift API

BaseMemoryLib.lib(SetMem.obj) : error LNK2001: unresolved external symbol 
__allshl

Thanks
Liming
> -Original Message-
> From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org]
> Sent: Tuesday, September 06, 2016 10:24 PM
> To: edk2-devel@lists.01.org; leif.lindh...@linaro.org; Gao, Liming
> 
> Cc: Kinney, Michael D ; Ard Biesheuvel
> 
> Subject: [PATCH v2 1/3] MdePkg/BaseMemoryLib: widen aligned accesses to
> 32 or 64 bits
> 
> Since the default BaseMemoryLib should be callable from any context,
> including ones where unaligned accesses are not allowed, it implements
> InternalCopyMem() and InternalSetMem() using byte accesses only.
> However, especially in a context where the MMU is off, such narrow
> accesses may be disproportionately costly, and so if the size and
> alignment of the access allow it, use 32-bit or even 64-bit loads and
> stores (the latter may be beneficial even on a 32-bit architectures like
> ARM, which has load pair/store pair instructions)
> 
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Ard Biesheuvel 
> ---
>  MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf |   2 +-
>  MdePkg/Library/BaseMemoryLib/CopyMem.c | 112
> ++--
>  MdePkg/Library/BaseMemoryLib/SetMem.c  |  40 ++-
>  3 files changed, 140 insertions(+), 14 deletions(-)
> 
> diff --git a/MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
> b/MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
> index 6d906e93faf3..358eeed4f449 100644
> --- a/MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
> +++ b/MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
> @@ -26,7 +26,7 @@ [Defines]
> 
> 
>  #
> -#  VALID_ARCHITECTURES   = IA32 X64 IPF EBC
> +#  VALID_ARCHITECTURES   = IA32 X64 IPF EBC ARM AARCH64
>  #
> 
>  [Sources]
> diff --git a/MdePkg/Library/BaseMemoryLib/CopyMem.c
> b/MdePkg/Library/BaseMemoryLib/CopyMem.c
> index 37f03660df5f..6f4fd900df5d 100644
> --- a/MdePkg/Library/BaseMemoryLib/CopyMem.c
> +++ b/MdePkg/Library/BaseMemoryLib/CopyMem.c
> @@ -4,6 +4,9 @@
>particular platform easily if an optimized version is desired.
> 
>Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
> +  Copyright (c) 2012 - 2013, ARM Ltd. All rights reserved.
> +  Copyright (c) 2016, Linaro Ltd. All rights reserved.
> +
>This program and the accompanying materials
>are licensed and made available under the terms and conditions of the BSD
> License
>which accompanies this distribution.  The full text of the license may be
> found at
> @@ -44,18 +47,107 @@ InternalMemCopyMem (
>//
>volatile UINT8*Destination8;
>CONST UINT8   *Source8;
> +  volatile UINT32   *Destination32;
> +  CONST UINT32  *Source32;
> +  volatile UINT64   *Destination64;
> +  CONST UINT64  *Source64;
> +  UINTN Alignment;
> +
> +  if UINTN)DestinationBuffer & 0x7) == 0) && (((UINTN)SourceBuffer &
> 0x7) == 0) && (Length >= 8)) {
> +if (SourceBuffer > DestinationBuffer) {
> +  Destination64 = (UINT64*)DestinationBuffer;
> +  Source64 = (CONST UINT64*)SourceBuffer;
> +  while (Length >= 8) {
> +*(Destination64++) = *(Source64++);
> +Length -= 8;
> +  }
> +
> +  // Finish if there are still some bytes to copy
> +  Destination8 = (UINT8*)Destination64;
> +  Source8 = (CONST UINT8*)Source64;
> +  while (Length-- != 0) {
> +*(Destination8++) = *(Source8++);
> +  }
> +} else if (SourceBuffer < DestinationBuffer) {
> +  Destination64 = (UINT64*)((UINTN)DestinationBuffer + Length);
> +  Source64 = (CONST UINT64*)((UINTN)SourceBuffer + Length);
> +
> +  // Destination64 and Source64 were aligned on a 64-bit boundary
> +  // but if length is not a multiple of 8 bytes then they won't be
> +  // anymore.
> +
> +  Alignment = Length & 0x7;
> +  if (Alignment != 0) {
> +Destination8 = (UINT8*)Destination64;
> +Source8 = (CONST UINT8*)Source64;
> +
> +while (Alignment-- != 0) {
> +  *(--Destination8) = *(--Source8);
> +  --Length;
> +}
> +Destination64 = (UINT64*)Destination8;
> +Source64 = (CONST UINT64*)Source8;
> +  }
> +
> +  while (Length > 0) {
> +*(--Destination64) = *(--Source64);
> +Length -= 8;
> +  }
> +}
> +  } else if UINTN)DestinationBuffer & 0x3) == 0) &&
> (((UINTN)SourceBuffer & 0x3) == 0) && (Length >= 4)) {
> +if (SourceBuffer > DestinationBuffer) {
> +  Destination32 = (UINT32*)DestinationBuffer;
> +  Source32 = (CONST 

Re: [edk2] [PATCH 0/2] Follow PI1.4a to fix artificial limitation of PCD SkuId range

[Gao, Liming]

Reviewed-by: Liming Gao 

> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
> Star Zeng
> Sent: Friday, September 02, 2016 7:59 PM
> To: edk2-devel@lists.01.org
> Cc: Zeng, Star 
> Subject: [edk2] [PATCH 0/2] Follow PI1.4a to fix artificial limitation of PCD
> SkuId range
> 
> Current BaseTools follow previous PI spec to use UINT8 for SkuId, to
> follow PI1.4a, BaseTools need to be updated to fix artificial limitation
> of PCD SkuId range.
> 
> BaseTools is updated to use UINT64 for SkuId, since the PCD database
> structure needs to be naturally aligned, the PCD database structure
> layout is adjusted to keep the natural alignment and version
> is updated to 6.
> 
> The structure definition in MdeModulePkg/Include/Guid/
> PcdDataBaseSignatureGuid.h and PCD drivers are also updated to match
> BaseTools.
> 
> Note: The source code and BaseTools need to be upgraded at the same time,
> and if they are not upgraded at the same time, build error like below will
> be triggered to help user identify the problem.
> 
> "Please make sure the version of PCD PEIM Service and the generated
> PCD PEI Database match."
> 
> Star Zeng (1):
>   MdeModulePkg PCD: Update PCD database structure definition to match
> BaseTools
> 
> Yonghong Zhu (1):
>   BaseTools: Follow PI1.4a to fix artificial limitation of PCD SkuId
> range
> 
>  BaseTools/Source/Python/AutoGen/GenPcdDb.py| 91
> ++
>  .../Include/Guid/PcdDataBaseSignatureGuid.h| 14 ++--
>  MdeModulePkg/Universal/PCD/Dxe/Pcd.c   |  2 +-
>  MdeModulePkg/Universal/PCD/Dxe/Service.c   |  2 +-
>  MdeModulePkg/Universal/PCD/Dxe/Service.h   |  4 +-
>  MdeModulePkg/Universal/PCD/Pei/Pcd.c   |  2 +-
>  MdeModulePkg/Universal/PCD/Pei/Service.c   |  4 +-
>  MdeModulePkg/Universal/PCD/Pei/Service.h   |  4 +-
>  8 files changed, 73 insertions(+), 50 deletions(-)
> 
> --
> 2.7.0.windows.1
> 
> ___
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> edk2-devel@lists.01.org
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[edk2] [PATCH] Maintainers.txt: Add Giri as 2nd maintainer

[Jiewen Yao]

Add Giri as 2nd maintainer to IntelFsp2*Pkg and IntelSiliconPkg.

Cc: Giri P Mudusuru 
Cc: Amy Chan 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao 
---
 Maintainers.txt | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Maintainers.txt b/Maintainers.txt
index b2e679d..6ac7085 100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -130,10 +130,12 @@ M: Jeff Fan 
 IntelFsp2Pkg
 W: https://github.com/tianocore/tianocore.github.io/wiki/IntelFsp2Pkg
 M: Jiewen Yao 
+M: Giri P Mudusuru 
 
 IntelFsp2WrapperPkg
 W: https://github.com/tianocore/tianocore.github.io/wiki/IntelFsp2WrapperPkg
 M: Jiewen Yao 
+M: Giri P Mudusuru 
 
 IntelFspPkg
 W: https://github.com/tianocore/tianocore.github.io/wiki/IntelFspPkg
@@ -146,6 +148,7 @@ M: Jiewen Yao 
 IntelSiliconPkg
 W: https://github.com/tianocore/tianocore.github.io/wiki/IntelSiliconPkg
 M: Jiewen Yao 
+M: Giri P Mudusuru 
 
 MdeModulePkg
 W: https://github.com/tianocore/tianocore.github.io/wiki/MdeModulePkg
-- 
2.7.4.windows.1

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Re: [edk2] [PATCH] ShellPkg: More fallbacks + error handling in UefiShellLib

[Ni, Ruiyu]

Nico,
You want to develop an application which needs file system access support but 
doesn't depend on Shell environment. So you link your application to 
UefiShellLib and change the shell library to handle the case when it's not in 
the Shell environment.
Is my understanding correct?

If yes, I suggest you directly use MdePkg/Library/UefiFileHandleLib. It 
provides file system access support while doesn't depend on Shell environment.

It's a bit strange to remove the hard dependency of Shell environment from 
Uefi*Shell*Lib.

Regards,
Ray

From: nico.sch...@ts.fujitsu.com [mailto:nico.sch...@ts.fujitsu.com]
Sent: Tuesday, September 6, 2016 8:02 PM
To: edk2-devel@lists.01.org
Cc: Carsey, Jaben ; Ni, Ruiyu 
Subject: [PATCH] ShellPkg: More fallbacks + error handling in UefiShellLib

Dear edk2 developers,
I've made a patch in the edk2 ShellPkg CodeModule. It improves compatibility 
when no Efi Shell is available. I've noted all details on Github. To not 
duplicate the information, please visit this link below. You can also find and 
compare the code there:
https://github.com/tianocore/edk2/pull/111

It would be really nice if you can have a look at the patch. Some further 
discussion might be required before this patch gets applied. Feedback is highly 
welcome. Thanks a lot :)

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by:  Nico Schulz 
nico.sch...@ts.fujitsu.com

Cheers,
Nico

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Re: [edk2] [PATCH] OptionRomPkg: .dsc fixes for ARM/AARCH64 and USB drivers

[Ni, Ruiyu]

Reviewed-by: Ruiyu Ni 

Regards,
Ray

>-Original Message-
>From: Leif Lindholm [mailto:leif.lindh...@linaro.org]
>Sent: Sunday, September 4, 2016 9:16 PM
>To: edk2-devel@lists.01.org
>Cc: Ni, Ruiyu ; Ard Biesheuvel 
>Subject: [PATCH] OptionRomPkg: .dsc fixes for ARM/AARCH64 and USB drivers
>
>Drivers under OptionRomPkg wouldn't build standalone, since ARM and
>AARCH64 were missing from SUPPORTED_ARCHITECTURES. So add them.
>Also, add some compiler libraries needed for ARM/AARCH64 GCC
>toolchains (CompilerIntrinsicsLib and BaseSwStackCheckLib).
>
>Also, the UsbNetworking drivers were not listed under [Components],
>so failed to build standalone. This patch adds them.
>
>Contributed-under: TianoCore Contribution Agreement 1.0
>Signed-off-by: Leif Lindholm 
>---
> OptionRomPkg/OptionRomPkg.dsc | 11 ++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
>diff --git a/OptionRomPkg/OptionRomPkg.dsc b/OptionRomPkg/OptionRomPkg.dsc
>index 03592f8..3365556 100644
>--- a/OptionRomPkg/OptionRomPkg.dsc
>+++ b/OptionRomPkg/OptionRomPkg.dsc
>@@ -7,6 +7,7 @@
> # A single driver can support mixes of EFI 1.1, UEFI 2.0 and UEFI 2.1.
> #
> # Copyright (c) 2007 - 2013, Intel Corporation. All rights reserved.
>+# Copyright (c) 2016, Linaro Ltd. All rights reserved.
> #
> # This program and the accompanying materials
> # are licensed and made available under the terms and conditions of the BSD 
> License
>@@ -29,7 +30,7 @@ [Defines]
>   PLATFORM_VERSION   = 0.1
>   DSC_SPECIFICATION  = 0x00010005
>   OUTPUT_DIRECTORY   = Build/OptionRomPkg
>-  SUPPORTED_ARCHITECTURES= IA32|IPF|X64|EBC
>+  SUPPORTED_ARCHITECTURES= IA32|IPF|X64|EBC|ARM|AARCH64
>   BUILD_TARGETS  = DEBUG|RELEASE
>   SKUID_IDENTIFIER   = DEFAULT
>
>@@ -60,6 +61,12 @@ [LibraryClasses]
>   
> UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
>   UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
>
>+[LibraryClasses.AARCH64, LibraryClasses.ARM]
>+  NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
>+
>+[LibraryClasses.ARM]
>+  NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
>+
> 
> #
> # Pcd Section - list of all EDK II PCD Entries defined by this Platform
>@@ -105,6 +112,8 @@ [Components]
>   OptionRomPkg/CirrusLogic5430Dxe/CirrusLogic5430Dxe.inf
>   OptionRomPkg/UndiRuntimeDxe/UndiRuntimeDxe.inf
>   OptionRomPkg/Bus/Usb/FtdiUsbSerialDxe/FtdiUsbSerialDxe.inf
>+  OptionRomPkg/Bus/Usb/UsbNetworking/Ax88772/Ax88772.inf
>+  OptionRomPkg/Bus/Usb/UsbNetworking/Ax88772b/Ax88772b.inf
>
> [Components.IA32, Components.X64, Components.IPF]
>   OptionRomPkg/Application/BltLibSample/BltLibSample.inf
>--
>2.9.3

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Re: [edk2] Ingebrigtsen: The End of Gmane?

[Rafael Machado]

Nice!!!

Em ter, 6 de set de 2016 às 13:20, Bruce Cran  escreveu:

> On 9/6/16 3:25 AM, Laszlo Ersek wrote:
>
> > The gmane web interface is gone, and I'm unaware of anyone who has
> > picked up the archive and exposed it under the same URLs (via domain
> > name transfer etc). So, at the moment (to my knowledge) all our
> > historical gmane links are broken. Neither do I know how someone could
> > access edk2-devel messages that predate Mike's enablement of the
> > built-in  archive.
>
> As of today, it seems a reboot is underway:
> http://home.gmane.org/2016/09/06/reboot-v1/
>
> "I just re-enabled some of the URLs and traffic is flowing.
>
> This rebuild is going to require an ongoing effort to bring it back to
> its former glory but we will get there shortly."
>
> --
> Bruce
>
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Re: [edk2] [Patch 20/20] UefiCpuPkg/XeonPhiMsr.h: add MSR reference from SDM in comment

[Mudusuru, Giri P]

Thanks Jeff for adding comments to refer the SDM naming.

Reviewed series of patches.

Reviewed-by: Giri P Mudusuru  

> -Original Message-
> From: Fan, Jeff
> Sent: Tuesday, September 6, 2016 4:39 AM
> To: edk2-devel@lists.01.org
> Cc: Kinney, Michael D ; Tian, Feng
> ; Mudusuru, Giri P 
> Subject: [Patch 20/20] UefiCpuPkg/XeonPhiMsr.h: add MSR reference from SDM
> in comment
> 
> Cc: Michael Kinney 
> Cc: Feng Tian 
> Cc: Giri P Mudusuru 
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Jeff Fan 
> ---
>  UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h | 51
> 
>  1 file changed, 51 insertions(+)
> 
> diff --git a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
> b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
> index 6695b69..75f2dce 100644
> --- a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
> +++ b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
> @@ -41,6 +41,7 @@
> 
>Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMI_COUNT);
>@endcode
> +  @note MSR_XEON_PHI_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
>  **/
>  #define MSR_XEON_PHI_SMI_COUNT   0x0034
> 
> @@ -85,6 +86,7 @@ typedef union {
>Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PLATFORM_INFO);
>AsmWriteMsr64 (MSR_XEON_PHI_PLATFORM_INFO, Msr.Uint64);
>@endcode
> +  @note MSR_XEON_PHI_PLATFORM_INFO is defined as
> MSR_PLATFORM_INFO in SDM.
>  **/
>  #define MSR_XEON_PHI_PLATFORM_INFO   0x00CE
> 
> @@ -151,6 +153,7 @@ typedef union {
>Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL);
>AsmWriteMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
>@endcode
> +  @note MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL is defined as
> MSR_PKG_CST_CONFIG_CONTROL in SDM.
>  **/
>  #define MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL  0x00E2
> 
> @@ -208,6 +211,7 @@ typedef union {
>Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE);
>AsmWriteMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE, Msr.Uint64);
>@endcode
> +  @note MSR_XEON_PHI_PMG_IO_CAPTURE_BASE is defined as
> MSR_PMG_IO_CAPTURE_BASE in SDM.
>  **/
>  #define MSR_XEON_PHI_PMG_IO_CAPTURE_BASE 0x00E4
> 
> @@ -261,6 +265,7 @@ typedef union {
>Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_FEATURE_CONFIG);
>AsmWriteMsr64 (MSR_XEON_PHI_FEATURE_CONFIG, Msr.Uint64);
>@endcode
> +  @note MSR_XEON_PHI_FEATURE_CONFIG is defined as
> MSR_FEATURE_CONFIG in SDM.
>  **/
>  #define MSR_XEON_PHI_FEATURE_CONFIG  0x013C
> 
> @@ -313,6 +318,7 @@ typedef union {
>Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE);
>AsmWriteMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE, Msr.Uint64);
>@endcode
> +  @note MSR_XEON_PHI_IA32_MISC_ENABLE is defined as
> IA32_MISC_ENABLE in SDM.
>  **/
>  #define MSR_XEON_PHI_IA32_MISC_ENABLE0x01A0
> 
> @@ -402,6 +408,7 @@ typedef union {
>Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET);
>AsmWriteMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET, Msr.Uint64);
>@endcode
> +  @note MSR_XEON_PHI_TEMPERATURE_TARGET is defined as
> MSR_TEMPERATURE_TARGET in SDM.
>  **/
>  #define MSR_XEON_PHI_TEMPERATURE_TARGET  0x01A2
> 
> @@ -450,6 +457,7 @@ typedef union {
>Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0);
>AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0, Msr);
>@endcode
> +  @note MSR_XEON_PHI_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0
> in SDM.
>  **/
>  #define MSR_XEON_PHI_OFFCORE_RSP_0   0x01A6
> 
> @@ -468,6 +476,7 @@ typedef union {
>Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1);
>AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1, Msr);
>@endcode
> +  @note MSR_XEON_PHI_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1
> in SDM.
>  **/
>  #define MSR_XEON_PHI_OFFCORE_RSP_1   0x01A7
> 
> @@ -488,6 +497,7 @@ typedef union {
>Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT);
>AsmWriteMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT, Msr.Uint64);
>@endcode
> +  @note MSR_XEON_PHI_TURBO_RATIO_LIMIT is defined as
> MSR_TURBO_RATIO_LIMIT in SDM.
>  **/
>  #define MSR_XEON_PHI_TURBO_RATIO_LIMIT   0x01AD
> 
> @@ -612,6 +622,7 @@ typedef union {
>Msr = AsmReadMsr64 (MSR_XEON_PHI_LBR_SELECT);
>AsmWriteMsr64 (MSR_XEON_PHI_LBR_SELECT, Msr);
>@endcode
> +  @note MSR_XEON_PHI_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
>  **/
>  #define MSR_XEON_PHI_LBR_SELECT  0x01C8
> 
> @@ -630,6 +641,7 @@ typedef union {
>Msr = AsmReadMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS);
>AsmWriteMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS, Msr);
>@endcode
> +  @note MSR_XEON_PHI_LASTBRANCH_TOS is defined as
> MSR_LASTBRANCH_TOS in SDM.
>  **/
>  #define MSR_XEON_PHI_LASTBRANCH_TOS  0x01C9
> 
> @@ -647,6 

Re: [edk2] [PATCH] OptionRomPkg: .dsc fixes for ARM/AARCH64 and USB drivers

[Leif Lindholm]

Ruiyu - any comments?

Regards,

Leif

On 4 September 2016 at 14:16, Leif Lindholm  wrote:
> Drivers under OptionRomPkg wouldn't build standalone, since ARM and
> AARCH64 were missing from SUPPORTED_ARCHITECTURES. So add them.
> Also, add some compiler libraries needed for ARM/AARCH64 GCC
> toolchains (CompilerIntrinsicsLib and BaseSwStackCheckLib).
>
> Also, the UsbNetworking drivers were not listed under [Components],
> so failed to build standalone. This patch adds them.
>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Leif Lindholm 
> ---
>  OptionRomPkg/OptionRomPkg.dsc | 11 ++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/OptionRomPkg/OptionRomPkg.dsc b/OptionRomPkg/OptionRomPkg.dsc
> index 03592f8..3365556 100644
> --- a/OptionRomPkg/OptionRomPkg.dsc
> +++ b/OptionRomPkg/OptionRomPkg.dsc
> @@ -7,6 +7,7 @@
>  # A single driver can support mixes of EFI 1.1, UEFI 2.0 and UEFI 2.1.
>  #
>  # Copyright (c) 2007 - 2013, Intel Corporation. All rights reserved.
> +# Copyright (c) 2016, Linaro Ltd. All rights reserved.
>  #
>  # This program and the accompanying materials
>  # are licensed and made available under the terms and conditions of the BSD 
> License
> @@ -29,7 +30,7 @@ [Defines]
>PLATFORM_VERSION   = 0.1
>DSC_SPECIFICATION  = 0x00010005
>OUTPUT_DIRECTORY   = Build/OptionRomPkg
> -  SUPPORTED_ARCHITECTURES= IA32|IPF|X64|EBC
> +  SUPPORTED_ARCHITECTURES= IA32|IPF|X64|EBC|ARM|AARCH64
>BUILD_TARGETS  = DEBUG|RELEASE
>SKUID_IDENTIFIER   = DEFAULT
>
> @@ -60,6 +61,12 @@ [LibraryClasses]
>
> UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
>UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
>
> +[LibraryClasses.AARCH64, LibraryClasses.ARM]
> +  NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
> +
> +[LibraryClasses.ARM]
> +  NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
> +
>  
> 
>  #
>  # Pcd Section - list of all EDK II PCD Entries defined by this Platform
> @@ -105,6 +112,8 @@ [Components]
>OptionRomPkg/CirrusLogic5430Dxe/CirrusLogic5430Dxe.inf
>OptionRomPkg/UndiRuntimeDxe/UndiRuntimeDxe.inf
>OptionRomPkg/Bus/Usb/FtdiUsbSerialDxe/FtdiUsbSerialDxe.inf
> +  OptionRomPkg/Bus/Usb/UsbNetworking/Ax88772/Ax88772.inf
> +  OptionRomPkg/Bus/Usb/UsbNetworking/Ax88772b/Ax88772b.inf
>
>  [Components.IA32, Components.X64, Components.IPF]
>OptionRomPkg/Application/BltLibSample/BltLibSample.inf
> --
> 2.9.3
>
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Re: [edk2] [PATCH 0/7] MdeModulePkg ArmVirtPkg: fixes for 64-bit PCI DMA

[Ard Biesheuvel]

On 6 September 2016 at 13:41, Tian, Feng  wrote:
> ATA/USB/NVME/SD are ok to me
>
> Reviewed-by: Feng Tian 
>

Thanks everyone

Committed as

a2c9b0873a77 MdeModulePkg/AtaAtapiPassThru: enable 64-bit PCI DMA
167c3fb45674 MdeModulePkg/EhciDxe: enable 64-bit PCI DMA
4e28ea2c29e0 MdeModulePkg/NvmExpressDxe: enable 64-bit PCI DMA
df0a0e4b6fae MdeModulePkg/SdMmcPciHcDxe: enable 64-bit PCI DMA
5c1b371a8839 MdeModulePkg/XhciDxe: enable 64-bit PCI DMA
e58a71d9c50b MdeModulePkg/PciHostBridgeDxe: restrict 64-bit DMA to
devices that support it
4c0b2d25c61c ArmVirtPkg/FdtPciHostBridgeLib: enable 64-bit PCI DMA



> -Original Message-
> From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org]
> Sent: Tuesday, September 6, 2016 6:36 PM
> To: Ni, Ruiyu 
> Cc: edk2-devel-01 ; Tian, Feng 
> ; Zeng, Star ; Gao, Liming 
> ; Laszlo Ersek ; Leif Lindholm 
> 
> Subject: Re: [edk2] [PATCH 0/7] MdeModulePkg ArmVirtPkg: fixes for 64-bit PCI 
> DMA
>
> On 6 September 2016 at 09:54, Ni, Ruiyu  wrote:
>> Ard,
>> The patch to MdeModulePkg/PciHostBridgeDxe is good.
>>
>> Reviewed-by: Ruiyu Ni 
>>
>
> Thanks Ray!
>
> Who is responsible for the AtapPassThru, USB, NVME and SDHCI drivers?
>
>>> -Original Message-
>>> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf
>>> Of Ard Biesheuvel
>>> Sent: Tuesday, September 6, 2016 3:48 PM
>>> To: edk2-devel-01 ; Tian, Feng
>>> ; Zeng, Star ; Gao, Liming
>>> 
>>> Cc: Laszlo Ersek ; Leif Lindholm
>>> ; Ard Biesheuvel
>>> 
>>> Subject: Re: [edk2] [PATCH 0/7] MdeModulePkg ArmVirtPkg: fixes for
>>> 64-bit PCI DMA
>>>
>>> Feng, Star: do you have any feedback on these patches? Thanks.
>>>
>>> On 5 September 2016 at 10:17, Ard Biesheuvel
>>> 
>>> wrote:
>>> > After moving ArmVirtQemu to the generic PciHostBridgeDxe, we
>>> > noticed that setting DmaAbove4G resulted in problems with the
>>> > emulated EHCI USB host controller, which were caused by the fact
>>> > that the PCI layer was providing DMA buffers allocated above 4 GB
>>> > while the emulated EHCI controller in QEMU does not indicate support for 
>>> > 64-bit addressing.
>>> >
>>> > As it turns out, the PCI drivers in MdeModulePkg *completely*
>>> > ignore the EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute, and
>>> > simply
>>> assume
>>> > that no PCI root bridge driver will produce mappings above 4 GB. On
>>> > ARM, this is problematic, since not all platforms have memory below
>>> > 4 GB, and so having full support for DMA above 4 GB is indispensable.
>>> >
>>> > So first, make the various drivers under MdeModulePkg/Pci/Bus set
>>> > the EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE attributes for devices
>>> > that can support 64-bit DMA addressing (patches #1 - #5). Then, we
>>> > can update the host bridge driver to actually take these attributes
>>> > into account, and only create mappings above 4 GB for devices that
>>> > have
>>> indicated support for it.
>>> >
>>> > Finally, in patch #7 we can remove the 4 GB DMA limit from ArmVirtPkg.
>>> >
>>> > Branch can be found here:
>>> > https://git.linaro.org/people/ard.biesheuvel/uefi-next.git/shortlog
>>> > /re
>>> > fs/heads/pci-64bit-dma-fixes
>>> >
>>> > Ard Biesheuvel (7):
>>> >   MdeModulePkg/AtaAtapiPassThru: enable 64-bit PCI DMA
>>> >   MdeModulePkg/EhciDxe: enable 64-bit PCI DMA
>>> >   MdeModulePkg/NvmExpressDxe: enable 64-bit PCI DMA
>>> >   MdeModulePkg/SdMmcPciHcDxe: enable 64-bit PCI DMA
>>> >   MdeModulePkg/XhciDxe: enable 64-bit PCI DMA
>>> >   MdeModulePkg/PciHostBridgeDxe: restrict 64-bit DMA to devices that
>>> > support it
>>> >   ArmVirtPkg/FdtPciHostBridgeLib: enable 64-bit PCI DMA
>>> >
>>> >  ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c |  2 +-
>>> >  MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c | 20
>>> +-
>>> >  MdeModulePkg/Bus/Pci/EhciDxe/Ehci.c  | 22
>>> +++-
>>> >  MdeModulePkg/Bus/Pci/EhciDxe/Ehci.h  |  2 ++
>>> >  MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c |  2 +-
>>> >  MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c   | 13
>>> 
>>> >  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c  | 14
>>> +
>>> >  MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c   | 20
>>> ++
>>> >  MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c  | 22
>>> +++-
>>> >  MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h  |  2 ++
>>> >  10 files changed, 110 insertions(+), 9 deletions(-)
>>> >
>>> > --
>>> > 

Re: [edk2] [PATCH] ArmPkg/CompilerIntrinsicsLib: use Clang-compatible 'weak' attribute

[Leif Lindholm]

On Tue, Sep 06, 2016 at 03:27:31PM +0100, Ard Biesheuvel wrote:
> Clang does not like separate definitions for the __alias__ and the
> __weak__ attributes, so merge the definitions into one.
> 
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Ard Biesheuvel 

Reviewed-by: Leif Lindholm 

> ---
> 
> Note that the CI job is currently broken due to this clang issue.
> 
>  ArmPkg/Library/CompilerIntrinsicsLib/memset.c | 9 +++--
>  1 file changed, 3 insertions(+), 6 deletions(-)
> 
> diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/memset.c 
> b/ArmPkg/Library/CompilerIntrinsicsLib/memset.c
> index 0d837fcecf09..7271b4be6f96 100644
> --- a/ArmPkg/Library/CompilerIntrinsicsLib/memset.c
> +++ b/ArmPkg/Library/CompilerIntrinsicsLib/memset.c
> @@ -26,20 +26,17 @@ void *__memset(void *s, int c, size_t n)
>return s;
>  }
>  
> -__attribute__((__alias__("__memset")))
> -void *memset(void *dest, int c, size_t n);
> -
> -#ifdef __arm__
> -
>  //
>  // Other modules (such as CryptoPkg/IntrinsicLib) may provide another
>  // implementation of memset(), which may conflict with this one if this
>  // object was pulled into the link due to the definitions below. So make
>  // our memset() 'weak' to let the other implementation take precedence.
>  //
> -__attribute__((__weak__))
> +__attribute__((__weak__, __alias__("__memset")))
>  void *memset(void *dest, int c, size_t n);
>  
> +#ifdef __arm__
> +
>  void __aeabi_memset(void *dest, size_t n, int c)
>  {
>__memset(dest, c, n);
> -- 
> 2.7.4
> 
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[edk2] [PATCH] ArmPkg/CompilerIntrinsicsLib: use Clang-compatible 'weak' attribute

[Ard Biesheuvel]

Clang does not like separate definitions for the __alias__ and the
__weak__ attributes, so merge the definitions into one.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel 
---

Note that the CI job is currently broken due to this clang issue.

 ArmPkg/Library/CompilerIntrinsicsLib/memset.c | 9 +++--
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/memset.c 
b/ArmPkg/Library/CompilerIntrinsicsLib/memset.c
index 0d837fcecf09..7271b4be6f96 100644
--- a/ArmPkg/Library/CompilerIntrinsicsLib/memset.c
+++ b/ArmPkg/Library/CompilerIntrinsicsLib/memset.c
@@ -26,20 +26,17 @@ void *__memset(void *s, int c, size_t n)
   return s;
 }
 
-__attribute__((__alias__("__memset")))
-void *memset(void *dest, int c, size_t n);
-
-#ifdef __arm__
-
 //
 // Other modules (such as CryptoPkg/IntrinsicLib) may provide another
 // implementation of memset(), which may conflict with this one if this
 // object was pulled into the link due to the definitions below. So make
 // our memset() 'weak' to let the other implementation take precedence.
 //
-__attribute__((__weak__))
+__attribute__((__weak__, __alias__("__memset")))
 void *memset(void *dest, int c, size_t n);
 
+#ifdef __arm__
+
 void __aeabi_memset(void *dest, size_t n, int c)
 {
   __memset(dest, c, n);
-- 
2.7.4

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[edk2] [PATCH v2 2/3] MdePkg/BaseMemoryLibOptDxe: add accelerated ARM routines

[Ard Biesheuvel]

This adds ARM support to BaseMemoryLibOptDxe, partially based on the
cortex-strings library (ScanMem) and the existing CopyMem() implementation
from BaseMemoryLibStm in ArmPkg.

All string routines are accelerated except ScanMem16, ScanMem32,
ScanMem64 and IsZeroBuffer, which can wait for another day. (Very few
occurrences exist in the codebase)

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel 
---
 MdePkg/Library/BaseMemoryLibOptDxe/Arm/CompareMem.S| 138 

 MdePkg/Library/BaseMemoryLibOptDxe/Arm/CompareMem.asm  | 140 

 MdePkg/Library/BaseMemoryLibOptDxe/Arm/CopyMem.S   | 172 

 MdePkg/Library/BaseMemoryLibOptDxe/Arm/CopyMem.asm | 147 
+
 MdePkg/Library/BaseMemoryLibOptDxe/Arm/ScanMem.S   | 146 
+
 MdePkg/Library/BaseMemoryLibOptDxe/Arm/ScanMem.asm | 147 
+
 MdePkg/Library/BaseMemoryLibOptDxe/Arm/ScanMemGeneric.c| 142 

 MdePkg/Library/BaseMemoryLibOptDxe/Arm/SetMem.S|  69 
 MdePkg/Library/BaseMemoryLibOptDxe/Arm/SetMem.asm  |  74 +
 MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf |  30 ++--
 10 files changed, 1191 insertions(+), 14 deletions(-)

diff --git a/MdePkg/Library/BaseMemoryLibOptDxe/Arm/CompareMem.S 
b/MdePkg/Library/BaseMemoryLibOptDxe/Arm/CompareMem.S
new file mode 100644
index ..951d15777a38
--- /dev/null
+++ b/MdePkg/Library/BaseMemoryLibOptDxe/Arm/CompareMem.S
@@ -0,0 +1,138 @@
+//
+// Copyright (c) 2013 - 2016, Linaro Limited
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// * Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// * Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the distribution.
+// * Neither the name of the Linaro nor the
+//   names of its contributors may be used to endorse or promote products
+//   derived from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+
+// Parameters and result.
+#define src1  r0
+#define src2  r1
+#define limit r2
+#define resultr0
+
+// Internal variables.
+#define data1 r3
+#define data2 r4
+#define limit_wd  r5
+#define diff  r6
+#define tmp1  r7
+#define tmp2  r12
+#define pos   r8
+#define mask  r14
+
+.text
+.thumb
+.syntax unified
+.align  5
+ASM_GLOBAL ASM_PFX(InternalMemCompareMem)
+ASM_PFX(InternalMemCompareMem):
+push{r4-r8, lr}
+eor tmp1, src1, src2
+tst tmp1, #3
+bne .Lmisaligned4
+andstmp1, src1, #3
+bne .Lmutual_align
+add limit_wd, limit, #3
+nop.w
+lsr limit_wd, limit_wd, #2
+
+// Start of performance-critical section  -- one 32B cache line.
+.Lloop_aligned:
+ldr data1, [src1], #4
+ldr data2, [src2], #4
+.Lstart_realigned:
+subslimit_wd, limit_wd, #1
+eor diff, data1, data2// Non-zero if differences found.
+cbnzdiff, 0f
+bne .Lloop_aligned
+// End of performance-critical section  -- one 32B cache line.
+
+// Not reached the limit, must have found a diff.
+0:  cbnzlimit_wd, .Lnot_limit
+
+// Limit % 4 == 0 => all bytes significant.
+andslimit, limit, #3
+beq .Lnot_limit
+
+lsl limit, limit, #3  // Bits -> bytes.
+mov mask, #~0
+lsl mask, mask, limit
+bic data1, data1, mask
+bic data2, data2, mask
+
+orr diff, diff, mask
+
+.Lnot_limit:
+rev diff, diff
+rev data1, data1
+rev data2, data2
+
+// The MS-non-zero bit of DIFF marks either the first bit
+// that is different, or the end of the significant data.
+// Shifting left now will bring the 

[edk2] [PATCH v2 3/3] MdePkg/BaseMemoryLibOptDxe: add accelerated AARCH64 routines

[Ard Biesheuvel]

This adds AARCH64 support to BaseMemoryLibOptDxe, based on the cortex-strings
library. All string routines are accelerated except ScanMem16, ScanMem32,
ScanMem64 and IsZeroBuffer, which can wait for another day. (Very few
occurrences exist in the codebase)

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel 
---
 MdePkg/Library/BaseMemoryLibOptDxe/AArch64/CompareMem.S| 142 ++
 MdePkg/Library/BaseMemoryLibOptDxe/AArch64/CopyMem.S   | 284 

 MdePkg/Library/BaseMemoryLibOptDxe/AArch64/ScanMem.S   | 161 +++
 MdePkg/Library/BaseMemoryLibOptDxe/AArch64/SetMem.S| 244 
+
 MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf |   9 +-
 5 files changed, 839 insertions(+), 1 deletion(-)

diff --git a/MdePkg/Library/BaseMemoryLibOptDxe/AArch64/CompareMem.S 
b/MdePkg/Library/BaseMemoryLibOptDxe/AArch64/CompareMem.S
new file mode 100644
index ..a54de6948be1
--- /dev/null
+++ b/MdePkg/Library/BaseMemoryLibOptDxe/AArch64/CompareMem.S
@@ -0,0 +1,142 @@
+//
+// Copyright (c) 2013, Linaro Limited
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// * Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// * Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the distribution.
+// * Neither the name of the Linaro nor the
+//   names of its contributors may be used to endorse or promote products
+//   derived from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+
+// Assumptions:
+//
+// ARMv8-a, AArch64
+//
+
+
+// Parameters and result.
+#define src1  x0
+#define src2  x1
+#define limit x2
+#define resultx0
+
+// Internal variables.
+#define data1 x3
+#define data1ww3
+#define data2 x4
+#define data2ww4
+#define diff  x6
+#define endloop   x7
+#define tmp1  x8
+#define tmp2  x9
+#define pos   x11
+#define limit_wd  x12
+#define mask  x13
+
+.p2align 6
+ASM_GLOBAL ASM_PFX(InternalMemCompareMem)
+ASM_PFX(InternalMemCompareMem):
+eor tmp1, src1, src2
+tst tmp1, #7
+b.ne.Lmisaligned8
+andstmp1, src1, #7
+b.ne.Lmutual_align
+add limit_wd, limit, #7
+lsr limit_wd, limit_wd, #3
+
+// Start of performance-critical section  -- one 64B cache line.
+.Lloop_aligned:
+ldr data1, [src1], #8
+ldr data2, [src2], #8
+.Lstart_realigned:
+subslimit_wd, limit_wd, #1
+eor diff, data1, data2// Non-zero if differences found.
+csinv   endloop, diff, xzr, ne// Last Dword or differences.
+cbz endloop, .Lloop_aligned
+// End of performance-critical section  -- one 64B cache line.
+
+// Not reached the limit, must have found a diff.
+cbnzlimit_wd, .Lnot_limit
+
+// Limit % 8 == 0 => all bytes significant.
+andslimit, limit, #7
+b.eq.Lnot_limit
+
+lsl limit, limit, #3  // Bits -> bytes.
+mov mask, #~0
+lsl mask, mask, limit
+bic data1, data1, mask
+bic data2, data2, mask
+
+orr diff, diff, mask
+
+.Lnot_limit:
+rev diff, diff
+rev data1, data1
+rev data2, data2
+
+// The MS-non-zero bit of DIFF marks either the first bit
+// that is different, or the end of the significant data.
+// Shifting left now will bring the critical information into the
+// top bits.
+clz pos, diff
+lsl data1, data1, pos
+lsl data2, data2, pos
+
+// But we need to zero-extend (char is unsigned) the value and then
+// perform a signed 32-bit subtraction.
+lsr data1, data1, #56
+sub result, data1, data2, lsr #56
+ret
+
+.Lmutual_align:
+// Sources are mutually aligned, but are not currently at 

[edk2] [PATCH v2 1/3] MdePkg/BaseMemoryLib: widen aligned accesses to 32 or 64 bits

[Ard Biesheuvel]

Since the default BaseMemoryLib should be callable from any context,
including ones where unaligned accesses are not allowed, it implements
InternalCopyMem() and InternalSetMem() using byte accesses only.
However, especially in a context where the MMU is off, such narrow
accesses may be disproportionately costly, and so if the size and
alignment of the access allow it, use 32-bit or even 64-bit loads and
stores (the latter may be beneficial even on a 32-bit architectures like
ARM, which has load pair/store pair instructions)

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel 
---
 MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf |   2 +-
 MdePkg/Library/BaseMemoryLib/CopyMem.c | 112 ++--
 MdePkg/Library/BaseMemoryLib/SetMem.c  |  40 ++-
 3 files changed, 140 insertions(+), 14 deletions(-)

diff --git a/MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf 
b/MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
index 6d906e93faf3..358eeed4f449 100644
--- a/MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+++ b/MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
@@ -26,7 +26,7 @@ [Defines]
 
 
 #
-#  VALID_ARCHITECTURES   = IA32 X64 IPF EBC
+#  VALID_ARCHITECTURES   = IA32 X64 IPF EBC ARM AARCH64
 #
 
 [Sources]
diff --git a/MdePkg/Library/BaseMemoryLib/CopyMem.c 
b/MdePkg/Library/BaseMemoryLib/CopyMem.c
index 37f03660df5f..6f4fd900df5d 100644
--- a/MdePkg/Library/BaseMemoryLib/CopyMem.c
+++ b/MdePkg/Library/BaseMemoryLib/CopyMem.c
@@ -4,6 +4,9 @@
   particular platform easily if an optimized version is desired.
 
   Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+  Copyright (c) 2012 - 2013, ARM Ltd. All rights reserved.
+  Copyright (c) 2016, Linaro Ltd. All rights reserved.
+
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -44,18 +47,107 @@ InternalMemCopyMem (
   //
   volatile UINT8*Destination8;
   CONST UINT8   *Source8;
+  volatile UINT32   *Destination32;
+  CONST UINT32  *Source32;
+  volatile UINT64   *Destination64;
+  CONST UINT64  *Source64;
+  UINTN Alignment;
+
+  if UINTN)DestinationBuffer & 0x7) == 0) && (((UINTN)SourceBuffer & 0x7) 
== 0) && (Length >= 8)) {
+if (SourceBuffer > DestinationBuffer) {
+  Destination64 = (UINT64*)DestinationBuffer;
+  Source64 = (CONST UINT64*)SourceBuffer;
+  while (Length >= 8) {
+*(Destination64++) = *(Source64++);
+Length -= 8;
+  }
+
+  // Finish if there are still some bytes to copy
+  Destination8 = (UINT8*)Destination64;
+  Source8 = (CONST UINT8*)Source64;
+  while (Length-- != 0) {
+*(Destination8++) = *(Source8++);
+  }
+} else if (SourceBuffer < DestinationBuffer) {
+  Destination64 = (UINT64*)((UINTN)DestinationBuffer + Length);
+  Source64 = (CONST UINT64*)((UINTN)SourceBuffer + Length);
+
+  // Destination64 and Source64 were aligned on a 64-bit boundary
+  // but if length is not a multiple of 8 bytes then they won't be
+  // anymore.
+
+  Alignment = Length & 0x7;
+  if (Alignment != 0) {
+Destination8 = (UINT8*)Destination64;
+Source8 = (CONST UINT8*)Source64;
+
+while (Alignment-- != 0) {
+  *(--Destination8) = *(--Source8);
+  --Length;
+}
+Destination64 = (UINT64*)Destination8;
+Source64 = (CONST UINT64*)Source8;
+  }
+
+  while (Length > 0) {
+*(--Destination64) = *(--Source64);
+Length -= 8;
+  }
+}
+  } else if UINTN)DestinationBuffer & 0x3) == 0) && (((UINTN)SourceBuffer 
& 0x3) == 0) && (Length >= 4)) {
+if (SourceBuffer > DestinationBuffer) {
+  Destination32 = (UINT32*)DestinationBuffer;
+  Source32 = (CONST UINT32*)SourceBuffer;
+  while (Length >= 4) {
+*(Destination32++) = *(Source32++);
+Length -= 4;
+  }
+
+  // Finish if there are still some bytes to copy
+  Destination8 = (UINT8*)Destination32;
+  Source8 = (CONST UINT8*)Source32;
+  while (Length-- != 0) {
+*(Destination8++) = *(Source8++);
+  }
+} else if (SourceBuffer < DestinationBuffer) {
+  Destination32 = (UINT32*)((UINTN)DestinationBuffer + Length);
+  Source32 = (CONST UINT32*)((UINTN)SourceBuffer + Length);
+
+  // Destination32 and Source32 were aligned on a 32-bit boundary
+  // but if length is not a multiple of 4 bytes then they won't be
+  // anymore.
+
+  Alignment = Length & 0x3;
+  if (Alignment != 0) {
+Destination8 = (UINT8*)Destination32;
+Source8 = (CONST UINT8*)Source32;
+
+while (Alignment-- != 0) {
+  

[edk2] [PATCH v2 0/3] MdePkg: add ARM/AARCH64 support to BaseMemoryLib

[Ard Biesheuvel]

This adds ARM and AARCH64 support to both BaseMemoryLib (generic C) and
BaseMemoryLibOptDxe (accelerated). The former can be used anywhere, the
latter only in places where the caches are guaranteed to be on, not only
due to the unaligned accesses but also due to the fact that it uses
DC ZVA instructions for clearing memory (AArch64 only).

Ard Biesheuvel (3):
  MdePkg/BaseMemoryLib: widen aligned accesses to 32 or 64 bits
  MdePkg/BaseMemoryLibOptDxe: add accelerated ARM routines
  MdePkg/BaseMemoryLibOptDxe: add accelerated AARCH64 routines

 MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf |   2 +-
 MdePkg/Library/BaseMemoryLib/CopyMem.c | 112 +++-
 MdePkg/Library/BaseMemoryLib/SetMem.c  |  40 ++-
 MdePkg/Library/BaseMemoryLibOptDxe/AArch64/CompareMem.S| 142 ++
 MdePkg/Library/BaseMemoryLibOptDxe/AArch64/CopyMem.S   | 284 

 MdePkg/Library/BaseMemoryLibOptDxe/AArch64/ScanMem.S   | 161 +++
 MdePkg/Library/BaseMemoryLibOptDxe/AArch64/SetMem.S| 244 
+
 MdePkg/Library/BaseMemoryLibOptDxe/Arm/CompareMem.S| 138 ++
 MdePkg/Library/BaseMemoryLibOptDxe/Arm/CompareMem.asm  | 140 ++
 MdePkg/Library/BaseMemoryLibOptDxe/Arm/CopyMem.S   | 172 
 MdePkg/Library/BaseMemoryLibOptDxe/Arm/CopyMem.asm | 147 ++
 MdePkg/Library/BaseMemoryLibOptDxe/Arm/ScanMem.S   | 146 ++
 MdePkg/Library/BaseMemoryLibOptDxe/Arm/ScanMem.asm | 147 ++
 MdePkg/Library/BaseMemoryLibOptDxe/Arm/ScanMemGeneric.c| 142 ++
 MdePkg/Library/BaseMemoryLibOptDxe/Arm/SetMem.S|  69 +
 MdePkg/Library/BaseMemoryLibOptDxe/Arm/SetMem.asm  |  74 +
 MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf |  37 ++-
 17 files changed, 2169 insertions(+), 28 deletions(-)
 create mode 100644 MdePkg/Library/BaseMemoryLibOptDxe/AArch64/CompareMem.S
 create mode 100644 MdePkg/Library/BaseMemoryLibOptDxe/AArch64/CopyMem.S
 create mode 100644 MdePkg/Library/BaseMemoryLibOptDxe/AArch64/ScanMem.S
 create mode 100644 MdePkg/Library/BaseMemoryLibOptDxe/AArch64/SetMem.S
 create mode 100644 MdePkg/Library/BaseMemoryLibOptDxe/Arm/CompareMem.S
 create mode 100644 MdePkg/Library/BaseMemoryLibOptDxe/Arm/CompareMem.asm
 create mode 100644 MdePkg/Library/BaseMemoryLibOptDxe/Arm/CopyMem.S
 create mode 100644 MdePkg/Library/BaseMemoryLibOptDxe/Arm/CopyMem.asm
 create mode 100644 MdePkg/Library/BaseMemoryLibOptDxe/Arm/ScanMem.S
 create mode 100644 MdePkg/Library/BaseMemoryLibOptDxe/Arm/ScanMem.asm
 create mode 100644 MdePkg/Library/BaseMemoryLibOptDxe/Arm/ScanMemGeneric.c
 create mode 100644 MdePkg/Library/BaseMemoryLibOptDxe/Arm/SetMem.S
 create mode 100644 MdePkg/Library/BaseMemoryLibOptDxe/Arm/SetMem.asm

-- 
2.7.4

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Re: [edk2] [PATCH 0/7] MdeModulePkg ArmVirtPkg: fixes for 64-bit PCI DMA

[Tian, Feng]

ATA/USB/NVME/SD are ok to me

Reviewed-by: Feng Tian 

-Original Message-
From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org] 
Sent: Tuesday, September 6, 2016 6:36 PM
To: Ni, Ruiyu 
Cc: edk2-devel-01 ; Tian, Feng ; 
Zeng, Star ; Gao, Liming ; Laszlo 
Ersek ; Leif Lindholm 
Subject: Re: [edk2] [PATCH 0/7] MdeModulePkg ArmVirtPkg: fixes for 64-bit PCI 
DMA

On 6 September 2016 at 09:54, Ni, Ruiyu  wrote:
> Ard,
> The patch to MdeModulePkg/PciHostBridgeDxe is good.
>
> Reviewed-by: Ruiyu Ni 
>

Thanks Ray!

Who is responsible for the AtapPassThru, USB, NVME and SDHCI drivers?

>> -Original Message-
>> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf 
>> Of Ard Biesheuvel
>> Sent: Tuesday, September 6, 2016 3:48 PM
>> To: edk2-devel-01 ; Tian, Feng 
>> ; Zeng, Star ; Gao, Liming 
>> 
>> Cc: Laszlo Ersek ; Leif Lindholm 
>> ; Ard Biesheuvel 
>> 
>> Subject: Re: [edk2] [PATCH 0/7] MdeModulePkg ArmVirtPkg: fixes for 
>> 64-bit PCI DMA
>>
>> Feng, Star: do you have any feedback on these patches? Thanks.
>>
>> On 5 September 2016 at 10:17, Ard Biesheuvel 
>> 
>> wrote:
>> > After moving ArmVirtQemu to the generic PciHostBridgeDxe, we 
>> > noticed that setting DmaAbove4G resulted in problems with the 
>> > emulated EHCI USB host controller, which were caused by the fact 
>> > that the PCI layer was providing DMA buffers allocated above 4 GB 
>> > while the emulated EHCI controller in QEMU does not indicate support for 
>> > 64-bit addressing.
>> >
>> > As it turns out, the PCI drivers in MdeModulePkg *completely* 
>> > ignore the EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute, and 
>> > simply
>> assume
>> > that no PCI root bridge driver will produce mappings above 4 GB. On 
>> > ARM, this is problematic, since not all platforms have memory below 
>> > 4 GB, and so having full support for DMA above 4 GB is indispensable.
>> >
>> > So first, make the various drivers under MdeModulePkg/Pci/Bus set 
>> > the EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE attributes for devices 
>> > that can support 64-bit DMA addressing (patches #1 - #5). Then, we 
>> > can update the host bridge driver to actually take these attributes 
>> > into account, and only create mappings above 4 GB for devices that 
>> > have
>> indicated support for it.
>> >
>> > Finally, in patch #7 we can remove the 4 GB DMA limit from ArmVirtPkg.
>> >
>> > Branch can be found here:
>> > https://git.linaro.org/people/ard.biesheuvel/uefi-next.git/shortlog
>> > /re
>> > fs/heads/pci-64bit-dma-fixes
>> >
>> > Ard Biesheuvel (7):
>> >   MdeModulePkg/AtaAtapiPassThru: enable 64-bit PCI DMA
>> >   MdeModulePkg/EhciDxe: enable 64-bit PCI DMA
>> >   MdeModulePkg/NvmExpressDxe: enable 64-bit PCI DMA
>> >   MdeModulePkg/SdMmcPciHcDxe: enable 64-bit PCI DMA
>> >   MdeModulePkg/XhciDxe: enable 64-bit PCI DMA
>> >   MdeModulePkg/PciHostBridgeDxe: restrict 64-bit DMA to devices that
>> > support it
>> >   ArmVirtPkg/FdtPciHostBridgeLib: enable 64-bit PCI DMA
>> >
>> >  ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c |  2 +-
>> >  MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c | 20
>> +-
>> >  MdeModulePkg/Bus/Pci/EhciDxe/Ehci.c  | 22
>> +++-
>> >  MdeModulePkg/Bus/Pci/EhciDxe/Ehci.h  |  2 ++
>> >  MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c |  2 +-
>> >  MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c   | 13
>> 
>> >  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c  | 14
>> +
>> >  MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c   | 20
>> ++
>> >  MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c  | 22
>> +++-
>> >  MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h  |  2 ++
>> >  10 files changed, 110 insertions(+), 9 deletions(-)
>> >
>> > --
>> > 2.7.4
>> >
>> ___
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>> https://lists.01.org/mailman/listinfo/edk2-devel
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[edk2] [PATCH] ShellPkg: More fallbacks + error handling in UefiShellLib

[nico.sch...@ts.fujitsu.com]

Dear edk2 developers,

I’ve made a patch in the edk2 ShellPkg CodeModule. It improves compatibility
when no Efi Shell is available. I’ve noted all details on Github. To not
duplicate the information, please visit this link below. You can also find
and compare the code there:

https://github.com/tianocore/edk2/pull/111

 

It would be really nice if you can have a look at the patch. Some further
discussion might be required before this patch gets applied. Feedback is
highly welcome. Thanks a lot J

 

Contributed-under: TianoCore Contribution Agreement 1.0

Signed-off-by:  Nico Schulz nico.sch...@ts.fujitsu.com

 

Cheers,

Nico

 

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Re: [edk2] [Patch] MdeModulePkg: Support classless IP for DHCPv4 TransmitReceive()

[Santhapur Naveen]

Hello Jiaxin,

Thank you very much for your timely help and support.

Regards,
Naveen

-Original Message-
From: Wu, Jiaxin [mailto:jiaxin...@intel.com] 
Sent: Tuesday, September 06, 2016 4:35 PM
To: Santhapur Naveen; edk2-devel@lists.01.org
Cc: Ye, Ting; Fu, Siyuan
Subject: RE: [edk2] [Patch] MdeModulePkg: Support classless IP for DHCPv4 
TransmitReceive()

Hi Naveen,

The patch has been committed:

SHA-1: 8c5f78a2cc15199e3f77ae4b156023af366fd6c7
* MdeModulePkg: Support classless IP for DHCPv4 TransmitReceive()

Thanks,
Jiaxin

> -Original Message-
> From: Santhapur Naveen [mailto:nave...@amiindia.co.in]
> Sent: Friday, September 2, 2016 2:16 PM
> To: Wu, Jiaxin ; edk2-devel@lists.01.org
> Cc: Ye, Ting ; Fu, Siyuan 
> Subject: RE: [edk2] [Patch] MdeModulePkg: Support classless IP for 
> DHCPv4
> TransmitReceive()
> 
> Hello Jiaxin,
> 
>   My sincere apologies for the delayed response.
> 
>   I've verified the patch from my side and PXE boot is happening 
> successfully even in classless IP network.
> 
>   May I know whether this will be included in EDK2? If yes, can you 
> please provide any schedule for the same?
> 
> Best regards,
> Naveen
> 
> -Original Message-
> From: Santhapur Naveen
> Sent: Thursday, August 18, 2016 11:14 AM
> To: 'Wu, Jiaxin'; edk2-devel@lists.01.org
> Cc: Ye, Ting; Fu, Siyuan; Sivaraman Nainar; Madhan B. Santharam
> Subject: RE: [edk2] [Patch] MdeModulePkg: Support classless IP for 
> DHCPv4
> TransmitReceive()
> 
> Jiaxin,
> 
> We will verify the patch and update you the result.
> 
> Thanks,
> Naveen
> 
> -Original Message-
> From: Wu, Jiaxin [mailto:jiaxin...@intel.com]
> Sent: Thursday, August 18, 2016 11:12 AM
> To: Santhapur Naveen; Wu, Jiaxin; edk2-devel@lists.01.org
> Cc: Ye, Ting; Fu, Siyuan; Sivaraman Nainar; Madhan B. Santharam
> Subject: RE: [edk2] [Patch] MdeModulePkg: Support classless IP for 
> DHCPv4
> TransmitReceive()
> 
> Naveen,
> 
> Can you help to verify this patch to support the classless IP.
> 
> Thanks,
> Jiaxin
> 
> > -Original Message-
> > From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf 
> > Of Jiaxin Wu
> > Sent: Thursday, August 18, 2016 1:39 PM
> > To: edk2-devel@lists.01.org
> > Cc: Ye, Ting ; Fu, Siyuan ; 
> > Santhapur Naveen 
> > Subject: [edk2] [Patch] MdeModulePkg: Support classless IP for 
> > DHCPv4
> > TransmitReceive()
> >
> > The IP address should not be treated as classful one if DHCP options 
> > contain a classless IP with its true subnet mask. Otherwise, DHCPv4
> > TransmitReceive() will failed. This real subnet mask will be parsed 
> > and recorded in DhcpSb->Netmask. So, we need check it before get the 
> > IP's corresponding subnet mask.
> >
> > Cc: Santhapur Naveen 
> > Cc: Ye Ting 
> > Cc: Fu Siyuan 
> > Contributed-under: TianoCore Contribution Agreement 1.0
> > Signed-off-by: Jiaxin Wu 
> > ---
> >  .../Universal/Network/Dhcp4Dxe/Dhcp4Impl.c | 28
> +++-
> > --
> >  1 file changed, 20 insertions(+), 8 deletions(-)
> >
> > diff --git a/MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Impl.c
> > b/MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Impl.c
> > index 4f491b4..79f7cde 100644
> > --- a/MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Impl.c
> > +++ b/MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Impl.c
> > @@ -1,9 +1,9 @@
> >  /** @file
> >This file implement the EFI_DHCP4_PROTOCOL interface.
> >
> > -Copyright (c) 2006 - 2015, Intel Corporation. All rights 
> > reserved.
> > +Copyright (c) 2006 - 2016, Intel Corporation. All rights 
> > +reserved.
> >  This program and the accompanying materials  are licensed and made 
> > available under the terms and conditions of the BSD License  which 
> > accompanies this distribution.  The full text of the license may be 
> > found at http://opensource.org/licenses/bsd-license.php
> >
> > @@ -1186,18 +1186,20 @@ Dhcp4InstanceConfigUdpIo (
> >IN UDP_IO   *UdpIo,
> >IN VOID *Context
> >)
> >  {
> >DHCP_PROTOCOL *Instance;
> > +  DHCP_SERVICE  *DhcpSb;
> >EFI_DHCP4_TRANSMIT_RECEIVE_TOKEN  *Token;
> >EFI_UDP4_CONFIG_DATA  UdpConfigData;
> >IP4_ADDR  ClientAddr;
> >IP4_ADDR  Ip;
> >INTN  Class;
> >IP4_ADDR  SubnetMask;
> >
> >Instance = (DHCP_PROTOCOL *) Context;
> > +  DhcpSb   = Instance->Service;
> >Token= Instance->Token;
> >
> >ZeroMem (, sizeof (EFI_UDP4_CONFIG_DATA));
> >
> >UdpConfigData.AcceptBroadcast= TRUE;
> > @@ -1206,14 +1208,19 @@ Dhcp4InstanceConfigUdpIo (
> >UdpConfigData.DoNotFragment  = TRUE;
> >
> >ClientAddr = EFI_NTOHL 

[edk2] [Patch 17/20] UefiCpuPkg/Xeon5600Msr.h: add MSR reference from SDM in comment

[Jeff Fan]

Cc: Michael Kinney 
Cc: Feng Tian 
Cc: Giri P Mudusuru 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan 
---
 UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h 
b/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h
index a4c6ba0..504c76b 100644
--- a/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h
@@ -43,6 +43,7 @@
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_FEATURE_CONFIG);
   AsmWriteMsr64 (MSR_XEON_5600_FEATURE_CONFIG, Msr.Uint64);
   @endcode
+  @note MSR_XEON_5600_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
 **/
 #define MSR_XEON_5600_FEATURE_CONFIG 0x013C
 
@@ -92,6 +93,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_5600_OFFCORE_RSP_1);
   AsmWriteMsr64 (MSR_XEON_5600_OFFCORE_RSP_1, Msr);
   @endcode
+  @note MSR_XEON_5600_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
 **/
 #define MSR_XEON_5600_OFFCORE_RSP_1  0x01A7
 
@@ -112,6 +114,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_TURBO_RATIO_LIMIT);
   @endcode
+  @note MSR_XEON_5600_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in 
SDM.
 **/
 #define MSR_XEON_5600_TURBO_RATIO_LIMIT  0x01AD
 
@@ -176,6 +179,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS);
   AsmWriteMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS, Msr);
   @endcode
+  @note MSR_XEON_5600_IA32_ENERGY_PERF_BIAS is defined as 
IA32_ENERGY_PERF_BIAS in SDM.
 **/
 #define MSR_XEON_5600_IA32_ENERGY_PERF_BIAS  0x01B0
 
-- 
2.9.3.windows.2

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[edk2] [Patch 20/20] UefiCpuPkg/XeonPhiMsr.h: add MSR reference from SDM in comment

[Jeff Fan]

Cc: Michael Kinney 
Cc: Feng Tian 
Cc: Giri P Mudusuru 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan 
---
 UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h | 51 
 1 file changed, 51 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h 
b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
index 6695b69..75f2dce 100644
--- a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
@@ -41,6 +41,7 @@
 
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMI_COUNT);
   @endcode
+  @note MSR_XEON_PHI_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
 **/
 #define MSR_XEON_PHI_SMI_COUNT   0x0034
 
@@ -85,6 +86,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PLATFORM_INFO);
   AsmWriteMsr64 (MSR_XEON_PHI_PLATFORM_INFO, Msr.Uint64);
   @endcode
+  @note MSR_XEON_PHI_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
 **/
 #define MSR_XEON_PHI_PLATFORM_INFO   0x00CE
 
@@ -151,6 +153,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL);
   AsmWriteMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
   @endcode
+  @note MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL is defined as 
MSR_PKG_CST_CONFIG_CONTROL in SDM.
 **/
 #define MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL  0x00E2
 
@@ -208,6 +211,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE);
   AsmWriteMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE, Msr.Uint64);
   @endcode
+  @note MSR_XEON_PHI_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE 
in SDM.
 **/
 #define MSR_XEON_PHI_PMG_IO_CAPTURE_BASE 0x00E4
 
@@ -261,6 +265,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_FEATURE_CONFIG);
   AsmWriteMsr64 (MSR_XEON_PHI_FEATURE_CONFIG, Msr.Uint64);
   @endcode
+  @note MSR_XEON_PHI_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
 **/
 #define MSR_XEON_PHI_FEATURE_CONFIG  0x013C
 
@@ -313,6 +318,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE);
   AsmWriteMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE, Msr.Uint64);
   @endcode
+  @note MSR_XEON_PHI_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
 **/
 #define MSR_XEON_PHI_IA32_MISC_ENABLE0x01A0
 
@@ -402,6 +408,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET);
   AsmWriteMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET, Msr.Uint64);
   @endcode
+  @note MSR_XEON_PHI_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET 
in SDM.
 **/
 #define MSR_XEON_PHI_TEMPERATURE_TARGET  0x01A2
 
@@ -450,6 +457,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0);
   AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0, Msr);
   @endcode
+  @note MSR_XEON_PHI_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.
 **/
 #define MSR_XEON_PHI_OFFCORE_RSP_0   0x01A6
 
@@ -468,6 +476,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1);
   AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1, Msr);
   @endcode
+  @note MSR_XEON_PHI_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
 **/
 #define MSR_XEON_PHI_OFFCORE_RSP_1   0x01A7
 
@@ -488,6 +497,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT);
   AsmWriteMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT, Msr.Uint64);
   @endcode
+  @note MSR_XEON_PHI_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in 
SDM.
 **/
 #define MSR_XEON_PHI_TURBO_RATIO_LIMIT   0x01AD
 
@@ -612,6 +622,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_PHI_LBR_SELECT);
   AsmWriteMsr64 (MSR_XEON_PHI_LBR_SELECT, Msr);
   @endcode
+  @note MSR_XEON_PHI_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
 **/
 #define MSR_XEON_PHI_LBR_SELECT  0x01C8
 
@@ -630,6 +641,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS);
   AsmWriteMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS, Msr);
   @endcode
+  @note MSR_XEON_PHI_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
 **/
 #define MSR_XEON_PHI_LASTBRANCH_TOS  0x01C9
 
@@ -647,6 +659,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_FROM_LIP);
   @endcode
+  @note MSR_XEON_PHI_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
 **/
 #define MSR_XEON_PHI_LER_FROM_LIP0x01DD
 
@@ -664,6 +677,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_TO_LIP);
   @endcode
+  @note MSR_XEON_PHI_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
 **/
 #define MSR_XEON_PHI_LER_TO_LIP  0x01DE
 
@@ -682,6 +696,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS);
   AsmWriteMsr64 (MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS, Msr);
   @endcode
+  @note MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS is defined as 

[edk2] [Patch 15/20] UefiCpuPkg/SilvermontMsr.h: add MSR reference from SDM in comment

[Jeff Fan]

Cc: Michael Kinney 
Cc: Feng Tian 
Cc: Giri P Mudusuru 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan 
---
 UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h | 57 +
 1 file changed, 57 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h 
b/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
index 4272375..335ebb2 100644
--- a/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
@@ -41,6 +41,7 @@
 
   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PLATFORM_ID);
   @endcode
+  @note MSR_SILVERMONT_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.
 **/
 #define MSR_SILVERMONT_PLATFORM_ID   0x0017
 
@@ -89,6 +90,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_EBL_CR_POWERON);
   AsmWriteMsr64 (MSR_SILVERMONT_EBL_CR_POWERON, Msr.Uint64);
   @endcode
+  @note MSR_SILVERMONT_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
 **/
 #define MSR_SILVERMONT_EBL_CR_POWERON0x002A
 
@@ -190,6 +192,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_SMI_COUNT);
   @endcode
+  @note MSR_SILVERMONT_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
 **/
 #define MSR_SILVERMONT_SMI_COUNT 0x0034
 
@@ -238,6 +241,14 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP);
   AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP, Msr);
   @endcode
+  @note MSR_SILVERMONT_LASTBRANCH_0_FROM_IP is defined as 
MSR_LASTBRANCH_0_FROM_IP in SDM.
+MSR_SILVERMONT_LASTBRANCH_1_FROM_IP is defined as 
MSR_LASTBRANCH_1_FROM_IP in SDM.
+MSR_SILVERMONT_LASTBRANCH_2_FROM_IP is defined as 
MSR_LASTBRANCH_2_FROM_IP in SDM.
+MSR_SILVERMONT_LASTBRANCH_3_FROM_IP is defined as 
MSR_LASTBRANCH_3_FROM_IP in SDM.
+MSR_SILVERMONT_LASTBRANCH_4_FROM_IP is defined as 
MSR_LASTBRANCH_4_FROM_IP in SDM.
+MSR_SILVERMONT_LASTBRANCH_5_FROM_IP is defined as 
MSR_LASTBRANCH_5_FROM_IP in SDM.
+MSR_SILVERMONT_LASTBRANCH_6_FROM_IP is defined as 
MSR_LASTBRANCH_6_FROM_IP in SDM.
+MSR_SILVERMONT_LASTBRANCH_7_FROM_IP is defined as 
MSR_LASTBRANCH_7_FROM_IP in SDM.
   @{
 **/
 #define MSR_SILVERMONT_LASTBRANCH_0_FROM_IP  0x0040
@@ -268,6 +279,14 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP);
   AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP, Msr);
   @endcode
+  @note MSR_SILVERMONT_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP 
in SDM.
+MSR_SILVERMONT_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP 
in SDM.
+MSR_SILVERMONT_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP 
in SDM.
+MSR_SILVERMONT_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP 
in SDM.
+MSR_SILVERMONT_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP 
in SDM.
+MSR_SILVERMONT_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP 
in SDM.
+MSR_SILVERMONT_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP 
in SDM.
+MSR_SILVERMONT_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP 
in SDM.
   @{
 **/
 #define MSR_SILVERMONT_LASTBRANCH_0_TO_IP0x0060
@@ -297,6 +316,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_FSB_FREQ);
   @endcode
+  @note MSR_SILVERMONT_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
 **/
 #define MSR_SILVERMONT_FSB_FREQ  0x00CD
 
@@ -364,6 +384,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL);
   AsmWriteMsr64 (MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
   @endcode
+  @note MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL is defined as 
MSR_PKG_CST_CONFIG_CONTROL in SDM.
 **/
 #define MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL0x00E2
 
@@ -428,6 +449,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PMG_IO_CAPTURE_BASE);
   AsmWriteMsr64 (MSR_SILVERMONT_PMG_IO_CAPTURE_BASE, Msr.Uint64);
   @endcode
+  @note MSR_SILVERMONT_PMG_IO_CAPTURE_BASE is defined as 
MSR_PMG_IO_CAPTURE_BASE in SDM.
 **/
 #define MSR_SILVERMONT_PMG_IO_CAPTURE_BASE   0x00E4
 
@@ -486,6 +508,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_BBL_CR_CTL3);
   AsmWriteMsr64 (MSR_SILVERMONT_BBL_CR_CTL3, Msr.Uint64);
   @endcode
+  @note MSR_SILVERMONT_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
 **/
 #define MSR_SILVERMONT_BBL_CR_CTL3   0x011E
 
@@ -545,6 +568,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_FEATURE_CONFIG);
   AsmWriteMsr64 (MSR_SILVERMONT_FEATURE_CONFIG, Msr.Uint64);
   @endcode
+  @note MSR_SILVERMONT_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
 **/
 #define MSR_SILVERMONT_FEATURE_CONFIG0x013C
 
@@ -597,6 +621,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 

[edk2] [Patch 13/20] UefiCpuPkg/PentiumMsr.h: add MSR reference from SDM in comment

[Jeff Fan]

Cc: Michael Kinney 
Cc: Feng Tian 
Cc: Giri P Mudusuru 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan 
---
 UefiCpuPkg/Include/Register/Msr/PentiumMsr.h | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h 
b/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h
index a8916b4..62c5b7e 100644
--- a/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h
@@ -40,6 +40,7 @@
   Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_ADDR);
   AsmWriteMsr64 (MSR_PENTIUM_P5_MC_ADDR, Msr);
   @endcode
+  @note MSR_PENTIUM_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
 **/
 #define MSR_PENTIUM_P5_MC_ADDR   0x
 
@@ -58,6 +59,7 @@
   Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_TYPE);
   AsmWriteMsr64 (MSR_PENTIUM_P5_MC_TYPE, Msr);
   @endcode
+  @note MSR_PENTIUM_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
 **/
 #define MSR_PENTIUM_P5_MC_TYPE   0x0001
 
@@ -76,6 +78,7 @@
   Msr = AsmReadMsr64 (MSR_PENTIUM_TSC);
   AsmWriteMsr64 (MSR_PENTIUM_TSC, Msr);
   @endcode
+  @note MSR_PENTIUM_TSC is defined as TSC in SDM.
 **/
 #define MSR_PENTIUM_TSC  0x0010
 
@@ -94,6 +97,7 @@
   Msr = AsmReadMsr64 (MSR_PENTIUM_CESR);
   AsmWriteMsr64 (MSR_PENTIUM_CESR, Msr);
   @endcode
+  @note MSR_PENTIUM_CESR is defined as CESR in SDM.
 **/
 #define MSR_PENTIUM_CESR 0x0011
 
@@ -112,6 +116,8 @@
   Msr = AsmReadMsr64 (MSR_PENTIUM_CTR0);
   AsmWriteMsr64 (MSR_PENTIUM_CTR0, Msr);
   @endcode
+  @note MSR_PENTIUM_CTR0 is defined as CTR0 in SDM.
+MSR_PENTIUM_CTR1 is defined as CTR1 in SDM.
   @{
 **/
 #define MSR_PENTIUM_CTR0 0x0012
-- 
2.9.3.windows.2

___
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[edk2] [Patch 16/20] UefiCpuPkg/SkylakeMsr.h: add MSR reference from SDM in comment

[Jeff Fan]

Cc: Michael Kinney 
Cc: Feng Tian 
Cc: Giri P Mudusuru 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan 
---
 UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h | 83 
 1 file changed, 83 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h 
b/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
index 34868f9..604b98f 100644
--- a/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
@@ -42,6 +42,7 @@
 
   Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT);
   @endcode
+  @note MSR_SKYLAKE_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in 
SDM.
 **/
 #define MSR_SKYLAKE_TURBO_RATIO_LIMIT0x01AD
 
@@ -101,6 +102,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS);
   AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS, Msr);
   @endcode
+  @note MSR_SKYLAKE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
 **/
 #define MSR_SKYLAKE_LASTBRANCH_TOS   0x01C9
 
@@ -119,6 +121,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_SKYLAKE_SGXOWNER0);
   @endcode
+  @note MSR_SKYLAKE_SGXOWNER0 is defined as MSR_SGXOWNER0 in SDM.
 **/
 #define MSR_SKYLAKE_SGXOWNER00x0300
 
@@ -137,6 +140,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_SKYLAKE_SGXOWNER1);
   @endcode
+  @note MSR_SKYLAKE_SGXOWNER1 is defined as MSR_SGXOWNER1 in SDM.
 **/
 #define MSR_SKYLAKE_SGXOWNER10x0301
 
@@ -158,6 +162,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS);
   AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS, Msr.Uint64);
   @endcode
+  @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS is defined as 
IA32_PERF_GLOBAL_STAUS in SDM.
 **/
 #define MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS   0x038E
 
@@ -269,6 +274,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET);
   AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);
   @endcode
+  @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET is defined as 
IA32_PERF_GLOBAL_STATUS_RESET in SDM.
 **/
 #define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET 0x0390
 
@@ -381,6 +387,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET);
   AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);
   @endcode
+  @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET is defined as 
IA32_PERF_GLOBAL_STATUS_SET in SDM.
 **/
 #define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET  0x0391
 
@@ -489,6 +496,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PEBS_FRONTEND);
   AsmWriteMsr64 (MSR_SKYLAKE_PEBS_FRONTEND, Msr.Uint64);
   @endcode
+  @note MSR_SKYLAKE_PEBS_FRONTEND is defined as MSR_PEBS_FRONTEND in SDM.
 **/
 #define MSR_SKYLAKE_PEBS_FRONTEND0x03F7
 
@@ -549,6 +557,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER);
   @endcode
+  @note MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER is defined as 
MSR_PLATFORM_ENERGY_COUNTER in SDM.
 **/
 #define MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER  0x064D
 
@@ -596,6 +605,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_SKYLAKE_PPERF);
   @endcode
+  @note MSR_SKYLAKE_PPERF is defined as MSR_PPERF in SDM.
 **/
 #define MSR_SKYLAKE_PPERF0x064E
 
@@ -616,6 +626,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG);
   AsmWriteMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG, Msr.Uint64);
   @endcode
+  @note MSR_SKYLAKE_PKG_HDC_CONFIG is defined as MSR_PKG_HDC_CONFIG in SDM.
 **/
 #define MSR_SKYLAKE_PKG_HDC_CONFIG   0x0652
 
@@ -659,6 +670,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_HDC_RESIDENCY);
   @endcode
+  @note MSR_SKYLAKE_CORE_HDC_RESIDENCY is defined as MSR_CORE_HDC_RESIDENCY in 
SDM.
 **/
 #define MSR_SKYLAKE_CORE_HDC_RESIDENCY   0x0653
 
@@ -677,6 +689,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY);
   @endcode
+  @note MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY is defined as 
MSR_PKG_HDC_SHALLOW_RESIDENCY in SDM.
 **/
 #define MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY0x0655
 
@@ -694,6 +707,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY);
   @endcode
+  @note MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY is defined as 
MSR_PKG_HDC_DEEP_RESIDENCY in SDM.
 **/
 #define MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY   0x0656
 
@@ -714,6 +728,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_SKYLAKE_WEIGHTED_CORE_C0);
   @endcode
+  @note MSR_SKYLAKE_WEIGHTED_CORE_C0 is defined as MSR_WEIGHTED_CORE_C0 in SDM.
 **/
 #define MSR_SKYLAKE_WEIGHTED_CORE_C0 0x0658
 
@@ -733,6 +748,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_SKYLAKE_ANY_CORE_C0);
   @endcode
+  @note MSR_SKYLAKE_ANY_CORE_C0 is defined as 

[edk2] [Patch 14/20] UefiCpuPkg/SandyBridgeMsr.h: add MSR reference from SDM in comment

[Jeff Fan]

Cc: Michael Kinney 
Cc: Feng Tian 
Cc: Giri P Mudusuru 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan 
---
 UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h | 271 +++
 1 file changed, 271 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h 
b/UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
index c41e45b..a50bad2 100644
--- a/UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
@@ -41,6 +41,7 @@
 
   Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_SMI_COUNT);
   @endcode
+  @note MSR_SANDY_BRIDGE_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
 **/
 #define MSR_SANDY_BRIDGE_SMI_COUNT   0x0034
 
@@ -85,6 +86,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO, Msr.Uint64);
   @endcode
+  @note MSR_SANDY_BRIDGE_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
 **/
 #define MSR_SANDY_BRIDGE_PLATFORM_INFO   0x00CE
 
@@ -153,6 +155,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
   @endcode
+  @note MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL is defined as 
MSR_PKG_CST_CONFIG_CONTROL in SDM.
 **/
 #define MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL  0x00E2
 
@@ -242,6 +245,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE, Msr.Uint64);
   @endcode
+  @note MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE is defined as 
MSR_PMG_IO_CAPTURE_BASE in SDM.
 **/
 #define MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE 0x00E4
 
@@ -301,6 +305,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG, Msr.Uint64);
   @endcode
+  @note MSR_SANDY_BRIDGE_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in 
SDM.
 **/
 #define MSR_SANDY_BRIDGE_FEATURE_CONFIG  0x013C
 
@@ -350,6 +355,10 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4 is defined as IA32_PERFEVTSEL4 in 
SDM.
+MSR_SANDY_BRIDGE_IA32_PERFEVTSEL5 is defined as IA32_PERFEVTSEL5 in 
SDM.
+MSR_SANDY_BRIDGE_IA32_PERFEVTSEL6 is defined as IA32_PERFEVTSEL6 in 
SDM.
+MSR_SANDY_BRIDGE_IA32_PERFEVTSEL7 is defined as IA32_PERFEVTSEL7 in 
SDM.
   @{
 **/
 #define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL40x018A
@@ -375,6 +384,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PERF_STATUS);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_PERF_STATUS, Msr.Uint64);
   @endcode
+  @note MSR_SANDY_BRIDGE_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.
 **/
 #define MSR_SANDY_BRIDGE_PERF_STATUS 0x0198
 
@@ -418,6 +428,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION, Msr.Uint64);
   @endcode
+  @note MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION is defined as 
IA32_CLOCK_MODULATION in SDM.
 **/
 #define MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION   0x019A
 
@@ -470,6 +481,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MISC_ENABLE);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MISC_ENABLE, Msr.Uint64);
   @endcode
+  @note MSR_SANDY_BRIDGE_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in 
SDM.
 **/
 #define MSR_SANDY_BRIDGE_IA32_MISC_ENABLE0x01A0
 
@@ -564,6 +576,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_TEMPERATURE_TARGET);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_TEMPERATURE_TARGET, Msr.Uint64);
   @endcode
+  @note MSR_SANDY_BRIDGE_TEMPERATURE_TARGET is defined as 
MSR_TEMPERATURE_TARGET in SDM.
 **/
 #define MSR_SANDY_BRIDGE_TEMPERATURE_TARGET  0x01A2
 
@@ -611,6 +624,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL, Msr.Uint64);
   @endcode
+  @note MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL is defined as 
MSR_MISC_FEATURE_CONTROL in SDM.
 **/
 #define MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL0x01A4
 
@@ -675,6 +689,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_0);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_0, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_OFFCORE_RSP_0   0x01A6
 
@@ -693,6 +708,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_1);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_1, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in 

[edk2] [Patch 12/20] UefiCpuPkg/PentiumMMsr.h: add MSR reference from SDM in comment

[Jeff Fan]

Cc: Michael Kinney 
Cc: Feng Tian 
Cc: Giri P Mudusuru 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan 
---
 UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h | 25 +
 1 file changed, 25 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h 
b/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h
index 324fc9b..3040631 100644
--- a/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h
@@ -40,6 +40,7 @@
   Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_ADDR);
   AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_ADDR, Msr);
   @endcode
+  @note MSR_PENTIUM_M_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
 **/
 #define MSR_PENTIUM_M_P5_MC_ADDR 0x
 
@@ -58,6 +59,7 @@
   Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_TYPE);
   AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_TYPE, Msr);
   @endcode
+  @note MSR_PENTIUM_M_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
 **/
 #define MSR_PENTIUM_M_P5_MC_TYPE 0x0001
 
@@ -79,6 +81,7 @@
   Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON);
   AsmWriteMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON, Msr.Uint64);
   @endcode
+  @note MSR_PENTIUM_M_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
 **/
 #define MSR_PENTIUM_M_EBL_CR_POWERON 0x002A
 
@@ -195,6 +198,14 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_0);
   AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_0, Msr);
   @endcode
+  @note MSR_PENTIUM_M_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.
+MSR_PENTIUM_M_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.
+MSR_PENTIUM_M_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.
+MSR_PENTIUM_M_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.
+MSR_PENTIUM_M_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM.
+MSR_PENTIUM_M_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM.
+MSR_PENTIUM_M_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM.
+MSR_PENTIUM_M_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.
   @{
 **/
 #define MSR_PENTIUM_M_LASTBRANCH_0   0x0040
@@ -222,6 +233,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL);
   AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL, Msr);
   @endcode
+  @note MSR_PENTIUM_M_BBL_CR_CTL is defined as MSR_BBL_CR_CTL in SDM.
 **/
 #define MSR_PENTIUM_M_BBL_CR_CTL 0x0119
 
@@ -242,6 +254,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3);
   AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3, Msr.Uint64);
   @endcode
+  @note MSR_PENTIUM_M_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
 **/
 #define MSR_PENTIUM_M_BBL_CR_CTL30x011E
 
@@ -308,6 +321,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_THERM2_CTL);
   AsmWriteMsr64 (MSR_PENTIUM_M_THERM2_CTL, Msr.Uint64);
   @endcode
+  @note MSR_PENTIUM_M_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
 **/
 #define MSR_PENTIUM_M_THERM2_CTL 0x019D
 
@@ -359,6 +373,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE);
   AsmWriteMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE, Msr.Uint64);
   @endcode
+  @note MSR_PENTIUM_M_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
 **/
 #define MSR_PENTIUM_M_IA32_MISC_ENABLE   0x01A0
 
@@ -460,6 +475,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS);
   AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS, Msr);
   @endcode
+  @note MSR_PENTIUM_M_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
 **/
 #define MSR_PENTIUM_M_LASTBRANCH_TOS 0x01C9
 
@@ -480,6 +496,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_M_DEBUGCTLB);
   AsmWriteMsr64 (MSR_PENTIUM_M_DEBUGCTLB, Msr);
   @endcode
+  @note MSR_PENTIUM_M_DEBUGCTLB is defined as MSR_DEBUGCTLB in SDM.
 **/
 #define MSR_PENTIUM_M_DEBUGCTLB  0x01D9
 
@@ -502,6 +519,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_TO_LIP);
   @endcode
+  @note MSR_PENTIUM_M_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
 **/
 #define MSR_PENTIUM_M_LER_TO_LIP 0x01DD
 
@@ -523,6 +541,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_FROM_LIP);
   @endcode
+  @note MSR_PENTIUM_M_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
 **/
 #define MSR_PENTIUM_M_LER_FROM_LIP   0x01DE
 
@@ -541,6 +560,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_CTL);
   AsmWriteMsr64 (MSR_PENTIUM_M_MC4_CTL, Msr);
   @endcode
+  @note MSR_PENTIUM_M_MC4_CTL is defined as MSR_MC4_CTL in SDM.
 **/
 #define MSR_PENTIUM_M_MC4_CTL0x040C
 
@@ -559,6 +579,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_STATUS);
   AsmWriteMsr64 (MSR_PENTIUM_M_MC4_STATUS, Msr);
   @endcode
+  @note MSR_PENTIUM_M_MC4_STATUS is defined 

[edk2] [Patch 11/20] UefiCpuPkg/Pentium4Msr.h: add MSR reference from SDM in comment

[Jeff Fan]

Cc: Michael Kinney 
Cc: Feng Tian 
Cc: Giri P Mudusuru 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan 
---
 UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h | 167 ++
 1 file changed, 167 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h 
b/UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h
index caeb5bb..306857f 100644
--- a/UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h
@@ -41,6 +41,7 @@
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE);
   AsmWriteMsr64 (MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE, Msr);
   @endcode
+  @note MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE is defined as 
IA32_MONITOR_FILTER_LINE_SIZE in SDM.
 **/
 #define MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE 0x0006
 
@@ -63,6 +64,7 @@
   Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_HARD_POWERON);
   AsmWriteMsr64 (MSR_PENTIUM_4_EBC_HARD_POWERON, Msr.Uint64);
   @endcode
+  @note MSR_PENTIUM_4_EBC_HARD_POWERON is defined as MSR_EBC_HARD_POWERON in 
SDM.
 **/
 #define MSR_PENTIUM_4_EBC_HARD_POWERON   0x002A
 
@@ -162,6 +164,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_SOFT_POWERON);
   AsmWriteMsr64 (MSR_PENTIUM_4_EBC_SOFT_POWERON, Msr.Uint64);
   @endcode
+  @note MSR_PENTIUM_4_EBC_SOFT_POWERON is defined as MSR_EBC_SOFT_POWERON in 
SDM.
 **/
 #define MSR_PENTIUM_4_EBC_SOFT_POWERON   0x002B
 
@@ -242,6 +245,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_FREQUENCY_ID);
   @endcode
+  @note MSR_PENTIUM_4_EBC_FREQUENCY_ID is defined as MSR_EBC_FREQUENCY_ID in 
SDM.
 **/
 #define MSR_PENTIUM_4_EBC_FREQUENCY_ID   0x002C
 
@@ -314,6 +318,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_FREQUENCY_ID_1);
   @endcode
+  @note MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 is defined as MSR_EBC_FREQUENCY_ID_1 
in SDM.
 **/
 #define MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 0x002C
 
@@ -364,6 +369,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RAX);
   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RAX, Msr);
   @endcode
+  @note MSR_PENTIUM_4_MCG_RAX is defined as MSR_MCG_RAX in SDM.
 **/
 #define MSR_PENTIUM_4_MCG_RAX0x0180
 
@@ -385,6 +391,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RBX);
   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RBX, Msr);
   @endcode
+  @note MSR_PENTIUM_4_MCG_RBX is defined as MSR_MCG_RBX in SDM.
 **/
 #define MSR_PENTIUM_4_MCG_RBX0x0181
 
@@ -406,6 +413,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RCX);
   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RCX, Msr);
   @endcode
+  @note MSR_PENTIUM_4_MCG_RCX is defined as MSR_MCG_RCX in SDM.
 **/
 #define MSR_PENTIUM_4_MCG_RCX0x0182
 
@@ -427,6 +435,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RDX);
   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RDX, Msr);
   @endcode
+  @note MSR_PENTIUM_4_MCG_RDX is defined as MSR_MCG_RDX in SDM.
 **/
 #define MSR_PENTIUM_4_MCG_RDX0x0183
 
@@ -448,6 +457,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RSI);
   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RSI, Msr);
   @endcode
+  @note MSR_PENTIUM_4_MCG_RSI is defined as MSR_MCG_RSI in SDM.
 **/
 #define MSR_PENTIUM_4_MCG_RSI0x0184
 
@@ -469,6 +479,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RDI);
   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RDI, Msr);
   @endcode
+  @note MSR_PENTIUM_4_MCG_RDI is defined as MSR_MCG_RDI in SDM.
 **/
 #define MSR_PENTIUM_4_MCG_RDI0x0185
 
@@ -490,6 +501,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RBP);
   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RBP, Msr);
   @endcode
+  @note MSR_PENTIUM_4_MCG_RBP is defined as MSR_MCG_RBP in SDM.
 **/
 #define MSR_PENTIUM_4_MCG_RBP0x0186
 
@@ -511,6 +523,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RSP);
   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RSP, Msr);
   @endcode
+  @note MSR_PENTIUM_4_MCG_RSP is defined as MSR_MCG_RSP in SDM.
 **/
 #define MSR_PENTIUM_4_MCG_RSP0x0187
 
@@ -532,6 +545,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RFLAGS);
   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RFLAGS, Msr);
   @endcode
+  @note MSR_PENTIUM_4_MCG_RFLAGS is defined as MSR_MCG_RFLAGS in SDM.
 **/
 #define MSR_PENTIUM_4_MCG_RFLAGS 0x0188
 
@@ -553,6 +567,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RIP);
   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RIP, Msr);
   @endcode
+  @note MSR_PENTIUM_4_MCG_RIP is defined as MSR_MCG_RIP in SDM.
 **/
 #define MSR_PENTIUM_4_MCG_RIP0x0189
 
@@ -574,6 +589,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_MCG_MISC);
   AsmWriteMsr64 

[edk2] [Patch 09/20] UefiCpuPkg/NehalemMsr.h: add MSR reference from SDM in comment

[Jeff Fan]

Cc: Michael Kinney 
Cc: Feng Tian 
Cc: Giri P Mudusuru 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan 
---
 UefiCpuPkg/Include/Register/Msr/NehalemMsr.h | 465 +++
 1 file changed, 465 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Msr/NehalemMsr.h 
b/UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
index cc24a23..6f3d4f4 100644
--- a/UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
@@ -41,6 +41,7 @@
 
   Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PLATFORM_ID);
   @endcode
+  @note MSR_NEHALEM_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.
 **/
 #define MSR_NEHALEM_PLATFORM_ID  0x0017
 
@@ -82,6 +83,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_SMI_COUNT);
   @endcode
+  @note MSR_NEHALEM_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
 **/
 #define MSR_NEHALEM_SMI_COUNT0x0034
 
@@ -127,6 +129,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PLATFORM_INFO);
   AsmWriteMsr64 (MSR_NEHALEM_PLATFORM_INFO, Msr.Uint64);
   @endcode
+  @note MSR_NEHALEM_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
 **/
 #define MSR_NEHALEM_PLATFORM_INFO0x00CE
 
@@ -195,6 +198,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PKG_CST_CONFIG_CONTROL);
   AsmWriteMsr64 (MSR_NEHALEM_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
   @endcode
+  @note MSR_NEHALEM_PKG_CST_CONFIG_CONTROL is defined as 
MSR_PKG_CST_CONFIG_CONTROL in SDM.
 **/
 #define MSR_NEHALEM_PKG_CST_CONFIG_CONTROL   0x00E2
 
@@ -281,6 +285,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PMG_IO_CAPTURE_BASE);
   AsmWriteMsr64 (MSR_NEHALEM_PMG_IO_CAPTURE_BASE, Msr.Uint64);
   @endcode
+  @note MSR_NEHALEM_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE 
in SDM.
 **/
 #define MSR_NEHALEM_PMG_IO_CAPTURE_BASE  0x00E4
 
@@ -340,6 +345,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_IA32_MISC_ENABLE);
   AsmWriteMsr64 (MSR_NEHALEM_IA32_MISC_ENABLE, Msr.Uint64);
   @endcode
+  @note MSR_NEHALEM_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
 **/
 #define MSR_NEHALEM_IA32_MISC_ENABLE 0x01A0
 
@@ -440,6 +446,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TEMPERATURE_TARGET);
   AsmWriteMsr64 (MSR_NEHALEM_TEMPERATURE_TARGET, Msr.Uint64);
   @endcode
+  @note MSR_NEHALEM_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in 
SDM.
 **/
 #define MSR_NEHALEM_TEMPERATURE_TARGET   0x01A2
 
@@ -487,6 +494,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_MISC_FEATURE_CONTROL);
   AsmWriteMsr64 (MSR_NEHALEM_MISC_FEATURE_CONTROL, Msr.Uint64);
   @endcode
+  @note MSR_NEHALEM_MISC_FEATURE_CONTROL is defined as 
MSR_MISC_FEATURE_CONTROL in SDM.
 **/
 #define MSR_NEHALEM_MISC_FEATURE_CONTROL 0x01A4
 
@@ -551,6 +559,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_OFFCORE_RSP_0);
   AsmWriteMsr64 (MSR_NEHALEM_OFFCORE_RSP_0, Msr);
   @endcode
+  @note MSR_NEHALEM_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.
 **/
 #define MSR_NEHALEM_OFFCORE_RSP_00x01A6
 
@@ -571,6 +580,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_MISC_PWR_MGMT);
   AsmWriteMsr64 (MSR_NEHALEM_MISC_PWR_MGMT, Msr.Uint64);
   @endcode
+  @note MSR_NEHALEM_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.
 **/
 #define MSR_NEHALEM_MISC_PWR_MGMT0x01AA
 
@@ -626,6 +636,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT);
   AsmWriteMsr64 (MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT, Msr.Uint64);
   @endcode
+  @note MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT is defined as 
MSR_TURBO_POWER_CURRENT_LIMIT in SDM.
 **/
 #define MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT0x01AC
 
@@ -686,6 +697,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TURBO_RATIO_LIMIT);
   @endcode
+  @note MSR_NEHALEM_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in 
SDM.
 **/
 #define MSR_NEHALEM_TURBO_RATIO_LIMIT0x01AD
 
@@ -747,6 +759,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_LBR_SELECT);
   AsmWriteMsr64 (MSR_NEHALEM_LBR_SELECT, Msr.Uint64);
   @endcode
+  @note MSR_NEHALEM_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
 **/
 #define MSR_NEHALEM_LBR_SELECT   0x01C8
 
@@ -824,6 +837,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_TOS);
   AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_TOS, Msr);
   @endcode
+  @note MSR_NEHALEM_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
 **/
 #define MSR_NEHALEM_LASTBRANCH_TOS   0x01C9
 
@@ -843,6 +857,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_NEHALEM_LER_FROM_LIP);
   @endcode
+  @note MSR_NEHALEM_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in 

[edk2] [Patch 10/20] UefiCpuPkg/P6Msr.h: add MSR reference from SDM in comment

[Jeff Fan]

Cc: Michael Kinney 
Cc: Feng Tian 
Cc: Giri P Mudusuru 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan 
---
 UefiCpuPkg/Include/Register/Msr/P6Msr.h | 83 +
 1 file changed, 83 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Msr/P6Msr.h 
b/UefiCpuPkg/Include/Register/Msr/P6Msr.h
index 7ee0b28..a196330 100644
--- a/UefiCpuPkg/Include/Register/Msr/P6Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/P6Msr.h
@@ -40,6 +40,7 @@
   Msr = AsmReadMsr64 (MSR_P6_P5_MC_ADDR);
   AsmWriteMsr64 (MSR_P6_P5_MC_ADDR, Msr);
   @endcode
+  @note MSR_P6_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
 **/
 #define MSR_P6_P5_MC_ADDR0x
 
@@ -58,6 +59,7 @@
   Msr = AsmReadMsr64 (MSR_P6_P5_MC_TYPE);
   AsmWriteMsr64 (MSR_P6_P5_MC_TYPE, Msr);
   @endcode
+  @note MSR_P6_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
 **/
 #define MSR_P6_P5_MC_TYPE0x0001
 
@@ -76,6 +78,7 @@
   Msr = AsmReadMsr64 (MSR_P6_TSC);
   AsmWriteMsr64 (MSR_P6_TSC, Msr);
   @endcode
+  @note MSR_P6_TSC is defined as TSC in SDM.
 **/
 #define MSR_P6_TSC   0x0010
 
@@ -96,6 +99,7 @@
 
   Msr.Uint64 = AsmReadMsr64 (MSR_P6_IA32_PLATFORM_ID);
   @endcode
+  @note MSR_P6_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM.
 **/
 #define MSR_P6_IA32_PLATFORM_ID  0x0017
 
@@ -158,6 +162,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_P6_APIC_BASE);
   AsmWriteMsr64 (MSR_P6_APIC_BASE, Msr.Uint64);
   @endcode
+  @note MSR_P6_APIC_BASE is defined as APIC_BASE in SDM.
 **/
 #define MSR_P6_APIC_BASE 0x001B
 
@@ -214,6 +219,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_P6_EBL_CR_POWERON);
   AsmWriteMsr64 (MSR_P6_EBL_CR_POWERON, Msr.Uint64);
   @endcode
+  @note MSR_P6_EBL_CR_POWERON is defined as EBL_CR_POWERON in SDM.
 **/
 #define MSR_P6_EBL_CR_POWERON0x002A
 
@@ -338,6 +344,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_P6_TEST_CTL);
   AsmWriteMsr64 (MSR_P6_TEST_CTL, Msr.Uint64);
   @endcode
+  @note MSR_P6_TEST_CTL is defined as TEST_CTL in SDM.
 **/
 #define MSR_P6_TEST_CTL  0x0033
 
@@ -385,6 +392,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_BIOS_UPDT_TRIG);
   AsmWriteMsr64 (MSR_P6_BIOS_UPDT_TRIG, Msr);
   @endcode
+  @note MSR_P6_BIOS_UPDT_TRIG is defined as BIOS_UPDT_TRIG in SDM.
 **/
 #define MSR_P6_BIOS_UPDT_TRIG0x0079
 
@@ -403,6 +411,9 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_BBL_CR_D0);
   AsmWriteMsr64 (MSR_P6_BBL_CR_D0, Msr);
   @endcode
+  @note MSR_P6_BBL_CR_D0 is defined as BBL_CR_D0 in SDM.
+MSR_P6_BBL_CR_D1 is defined as BBL_CR_D1 in SDM.
+MSR_P6_BBL_CR_D2 is defined as BBL_CR_D2 in SDM.
   @{
 **/
 #define MSR_P6_BBL_CR_D0 0x0088
@@ -426,6 +437,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_BIOS_SIGN);
   AsmWriteMsr64 (MSR_P6_BIOS_SIGN, Msr);
   @endcode
+  @note MSR_P6_BIOS_SIGN is defined as BIOS_SIGN in SDM.
 **/
 #define MSR_P6_BIOS_SIGN 0x008B
 
@@ -444,6 +456,8 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_PERFCTR0);
   AsmWriteMsr64 (MSR_P6_PERFCTR0, Msr);
   @endcode
+  @note MSR_P6_PERFCTR0 is defined as PERFCTR0 in SDM.
+MSR_P6_PERFCTR1 is defined as PERFCTR1 in SDM.
   @{
 **/
 #define MSR_P6_PERFCTR0  0x00C1
@@ -465,6 +479,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_MTRRCAP);
   AsmWriteMsr64 (MSR_P6_MTRRCAP, Msr);
   @endcode
+  @note MSR_P6_MTRRCAP is defined as MTRRCAP in SDM.
 **/
 #define MSR_P6_MTRRCAP   0x00FE
 
@@ -486,6 +501,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_ADDR);
   AsmWriteMsr64 (MSR_P6_BBL_CR_ADDR, Msr.Uint64);
   @endcode
+  @note MSR_P6_BBL_CR_ADDR is defined as BBL_CR_ADDR in SDM.
 **/
 #define MSR_P6_BBL_CR_ADDR   0x0116
 
@@ -529,6 +545,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_BBL_CR_DECC);
   AsmWriteMsr64 (MSR_P6_BBL_CR_DECC, Msr);
   @endcode
+  @note MSR_P6_BBL_CR_DECC is defined as BBL_CR_DECC in SDM.
 **/
 #define MSR_P6_BBL_CR_DECC   0x0118
 
@@ -550,6 +567,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_CTL);
   AsmWriteMsr64 (MSR_P6_BBL_CR_CTL, Msr.Uint64);
   @endcode
+  @note MSR_P6_BBL_CR_CTL is defined as BBL_CR_CTL in SDM.
 **/
 #define MSR_P6_BBL_CR_CTL0x0119
 
@@ -637,6 +655,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_BBL_CR_TRIG);
   AsmWriteMsr64 (MSR_P6_BBL_CR_TRIG, Msr);
   @endcode
+  @note MSR_P6_BBL_CR_TRIG is defined as BBL_CR_TRIG in SDM.
 **/
 #define MSR_P6_BBL_CR_TRIG   0x011A
 
@@ -656,6 +675,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_BBL_CR_BUSY);
   AsmWriteMsr64 

[edk2] [Patch 08/20] UefiCpuPkg/IvyBridgeMsr.h: add MSR reference from SDM in comment

[Jeff Fan]

Cc: Michael Kinney 
Cc: Feng Tian 
Cc: Giri P Mudusuru 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan 
---
 UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h | 218 +
 1 file changed, 218 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h 
b/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
index 0b08c0a..d278d52 100644
--- a/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
@@ -42,6 +42,7 @@
   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO, Msr.Uint64);
   @endcode
+  @note MSR_IVY_BRIDGE_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
 **/
 #define MSR_IVY_BRIDGE_PLATFORM_INFO 0x00CE
 
@@ -127,6 +128,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
   @endcode
+  @note MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL is defined as 
MSR_PKG_CST_CONFIG_CONTROL in SDM.
 **/
 #define MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL0x00E2
 
@@ -213,6 +215,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL);
   @endcode
+  @note MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL 
in SDM.
 **/
 #define MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL0x0648
 
@@ -258,6 +261,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1);
   @endcode
+  @note MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 
in SDM.
 **/
 #define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 0x0649
 
@@ -315,6 +319,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2);
   @endcode
+  @note MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 
in SDM.
 **/
 #define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 0x064A
 
@@ -373,6 +378,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL, Msr.Uint64);
   @endcode
+  @note MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL 
in SDM.
 **/
 #define MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL0x064B
 
@@ -423,6 +429,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO, Msr.Uint64);
   @endcode
+  @note MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO is defined as 
MSR_TURBO_ACTIVATION_RATIO in SDM.
 **/
 #define MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO0x064C
 
@@ -474,6 +481,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_PPIN_CTL, Msr.Uint64);
   @endcode
+  @note MSR_IVY_BRIDGE_PPIN_CTL is defined as MSR_PPIN_CTL in SDM.
 **/
 #define MSR_IVY_BRIDGE_PPIN_CTL  0x004E
 
@@ -535,6 +543,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN);
   @endcode
+  @note MSR_IVY_BRIDGE_PPIN is defined as MSR_PPIN in SDM.
 **/
 #define MSR_IVY_BRIDGE_PPIN  0x004F
 
@@ -555,6 +564,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1, Msr.Uint64);
   @endcode
+  @note MSR_IVY_BRIDGE_PLATFORM_INFO_1 is defined as MSR_PLATFORM_INFO_1 in 
SDM.
 **/
 #define MSR_IVY_BRIDGE_PLATFORM_INFO_1   0x00CE
 
@@ -636,6 +646,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL, Msr.Uint64);
   @endcode
+  @note MSR_IVY_BRIDGE_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.
 **/
 #define MSR_IVY_BRIDGE_ERROR_CONTROL 0x017F
 
@@ -683,6 +694,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET, Msr.Uint64);
   @endcode
+  @note MSR_IVY_BRIDGE_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET 
in SDM.
 **/
 #define MSR_IVY_BRIDGE_TEMPERATURE_TARGET0x01A2
 
@@ -737,6 +749,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1);
   @endcode
+  @note MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 
in SDM.
 **/
 #define MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT10x01AE
 
@@ -822,6 +835,33 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_MC5_CTL);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_MC5_CTL, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_MC5_CTL  is defined as MSR_MC5_CTL  in SDM.
+MSR_IVY_BRIDGE_MC6_CTL  is defined as MSR_MC6_CTL  in SDM.
+MSR_IVY_BRIDGE_MC7_CTL  is defined as MSR_MC7_CTL  in SDM.
+MSR_IVY_BRIDGE_MC8_CTL  is defined as MSR_MC8_CTL  in SDM.
+MSR_IVY_BRIDGE_MC9_CTL  is defined as MSR_MC9_CTL 

[edk2] [Patch 02/20] UefiCpuPkg/AtomMsr.h: add MSR reference from SDM in comment

[Jeff Fan]

Cc: Michael Kinney 
Cc: Feng Tian 
Cc: Giri P Mudusuru 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan 
---
 UefiCpuPkg/Include/Register/Msr/AtomMsr.h | 37 +++
 1 file changed, 37 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Msr/AtomMsr.h 
b/UefiCpuPkg/Include/Register/Msr/AtomMsr.h
index 01e0d9a..25e0927 100644
--- a/UefiCpuPkg/Include/Register/Msr/AtomMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/AtomMsr.h
@@ -41,6 +41,7 @@
 
   Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PLATFORM_ID);
   @endcode
+  @note MSR_ATOM_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.
 **/
 #define MSR_ATOM_PLATFORM_ID 0x0017
 
@@ -88,6 +89,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_EBL_CR_POWERON);
   AsmWriteMsr64 (MSR_ATOM_EBL_CR_POWERON, Msr.Uint64);
   @endcode
+  @note MSR_ATOM_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
 **/
 #define MSR_ATOM_EBL_CR_POWERON  0x002A
 
@@ -193,6 +195,14 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP);
   AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP, Msr);
   @endcode
+  @note MSR_ATOM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP 
in SDM.
+MSR_ATOM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP 
in SDM.
+MSR_ATOM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP 
in SDM.
+MSR_ATOM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP 
in SDM.
+MSR_ATOM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP 
in SDM.
+MSR_ATOM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP 
in SDM.
+MSR_ATOM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP 
in SDM.
+MSR_ATOM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP 
in SDM.
   @{
 **/
 #define MSR_ATOM_LASTBRANCH_0_FROM_IP0x0040
@@ -223,6 +233,14 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP);
   AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP, Msr);
   @endcode
+  @note MSR_ATOM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in 
SDM.
+MSR_ATOM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in 
SDM.
+MSR_ATOM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in 
SDM.
+MSR_ATOM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in 
SDM.
+MSR_ATOM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in 
SDM.
+MSR_ATOM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in 
SDM.
+MSR_ATOM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in 
SDM.
+MSR_ATOM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in 
SDM.
   @{
 **/
 #define MSR_ATOM_LASTBRANCH_0_TO_IP  0x0060
@@ -252,6 +270,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_FSB_FREQ);
   @endcode
+  @note MSR_ATOM_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
 **/
 #define MSR_ATOM_FSB_FREQ0x00CD
 
@@ -310,6 +329,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_BBL_CR_CTL3);
   AsmWriteMsr64 (MSR_ATOM_BBL_CR_CTL3, Msr.Uint64);
   @endcode
+  @note MSR_ATOM_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
 **/
 #define MSR_ATOM_BBL_CR_CTL3 0x011E
 
@@ -368,6 +388,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PERF_STATUS);
   AsmWriteMsr64 (MSR_ATOM_PERF_STATUS, Msr.Uint64);
   @endcode
+  @note MSR_ATOM_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.
 **/
 #define MSR_ATOM_PERF_STATUS 0x0198
 
@@ -415,6 +436,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_THERM2_CTL);
   AsmWriteMsr64 (MSR_ATOM_THERM2_CTL, Msr.Uint64);
   @endcode
+  @note MSR_ATOM_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
 **/
 #define MSR_ATOM_THERM2_CTL  0x019D
 
@@ -466,6 +488,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_IA32_MISC_ENABLE);
   AsmWriteMsr64 (MSR_ATOM_IA32_MISC_ENABLE, Msr.Uint64);
   @endcode
+  @note MSR_ATOM_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
 **/
 #define MSR_ATOM_IA32_MISC_ENABLE0x01A0
 
@@ -586,6 +609,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_TOS);
   AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_TOS, Msr);
   @endcode
+  @note MSR_ATOM_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
 **/
 #define MSR_ATOM_LASTBRANCH_TOS  0x01C9
 
@@ -605,6 +629,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_ATOM_LER_FROM_LIP);
   @endcode
+  @note MSR_ATOM_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
 **/
 #define MSR_ATOM_LER_FROM_LIP0x01DD
 
@@ -625,6 +650,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_ATOM_LER_TO_LIP);
   @endcode
+  @note MSR_ATOM_LER_TO_LIP is defined as MSR_LER_TO_LIP in 

[edk2] [Patch 07/20] UefiCpuPkg/HaswellMsr.h: add MSR reference from SDM in comment

[Jeff Fan]

Cc: Michael Kinney 
Cc: Feng Tian 
Cc: Giri P Mudusuru 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan 
---
 UefiCpuPkg/Include/Register/Msr/HaswellMsr.h | 58 
 1 file changed, 58 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h 
b/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
index 78915ec..f7cb6ce 100644
--- a/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
@@ -42,6 +42,7 @@
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PLATFORM_INFO);
   AsmWriteMsr64 (MSR_HASWELL_PLATFORM_INFO, Msr.Uint64);
   @endcode
+  @note MSR_HASWELL_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
 **/
 #define MSR_HASWELL_PLATFORM_INFO0x00CE
 
@@ -126,6 +127,9 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0);
   AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0, Msr.Uint64);
   @endcode
+  @note MSR_HASWELL_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM.
+MSR_HASWELL_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM.
+MSR_HASWELL_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.
   @{
 **/
 #define MSR_HASWELL_IA32_PERFEVTSEL0 0x0186
@@ -226,6 +230,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2);
   AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2, Msr.Uint64);
   @endcode
+  @note MSR_HASWELL_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM.
 **/
 #define MSR_HASWELL_IA32_PERFEVTSEL2 0x0188
 
@@ -330,6 +335,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_LBR_SELECT);
   AsmWriteMsr64 (MSR_HASWELL_LBR_SELECT, Msr.Uint64);
   @endcode
+  @note MSR_HASWELL_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
 **/
 #define MSR_HASWELL_LBR_SELECT   0x01C8
 
@@ -416,6 +422,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL1);
   AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL1, Msr.Uint64);
   @endcode
+  @note MSR_HASWELL_PKGC_IRTL1 is defined as MSR_PKGC_IRTL1 in SDM.
 **/
 #define MSR_HASWELL_PKGC_IRTL1   0x060B
 
@@ -487,6 +494,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL2);
   AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL2, Msr.Uint64);
   @endcode
+  @note MSR_HASWELL_PKGC_IRTL2 is defined as MSR_PKGC_IRTL2 in SDM.
 **/
 #define MSR_HASWELL_PKGC_IRTL2   0x060C
 
@@ -550,6 +558,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_HASWELL_PKG_PERF_STATUS);
   @endcode
+  @note MSR_HASWELL_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.
 **/
 #define MSR_HASWELL_PKG_PERF_STATUS  0x0613
 
@@ -567,6 +576,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_ENERGY_STATUS);
   @endcode
+  @note MSR_HASWELL_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in 
SDM.
 **/
 #define MSR_HASWELL_DRAM_ENERGY_STATUS   0x0619
 
@@ -585,6 +595,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_PERF_STATUS);
   @endcode
+  @note MSR_HASWELL_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
 **/
 #define MSR_HASWELL_DRAM_PERF_STATUS 0x061B
 
@@ -604,6 +615,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_NOMINAL);
   @endcode
+  @note MSR_HASWELL_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in 
SDM.
 **/
 #define MSR_HASWELL_CONFIG_TDP_NOMINAL   0x0648
 
@@ -649,6 +661,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL1);
   @endcode
+  @note MSR_HASWELL_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in 
SDM.
 **/
 #define MSR_HASWELL_CONFIG_TDP_LEVEL10x0649
 
@@ -705,6 +718,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL2);
   @endcode
+  @note MSR_HASWELL_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in 
SDM.
 **/
 #define MSR_HASWELL_CONFIG_TDP_LEVEL20x064A
 
@@ -762,6 +776,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL);
   AsmWriteMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL, Msr.Uint64);
   @endcode
+  @note MSR_HASWELL_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in 
SDM.
 **/
 #define MSR_HASWELL_CONFIG_TDP_CONTROL   0x064B
 
@@ -812,6 +827,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO);
   AsmWriteMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO, Msr.Uint64);
   @endcode
+  @note MSR_HASWELL_TURBO_ACTIVATION_RATIO is defined as 
MSR_TURBO_ACTIVATION_RATIO in SDM.
 **/
 #define MSR_HASWELL_TURBO_ACTIVATION_RATIO   0x064C
 
@@ -861,6 +877,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_IA32_DEBUG_FEATURE);
   AsmWriteMsr64 (MSR_HASWELL_IA32_DEBUG_FEATURE, Msr);
   @endcode
+  @note MSR_HASWELL_IA32_DEBUG_FEATURE is defined as 

[edk2] [Patch 06/20] UefiCpuPkg/HaswellEMsr.h: add MSR reference from SDM in comment

[Jeff Fan]

Cc: Michael Kinney 
Cc: Feng Tian 
Cc: Giri P Mudusuru 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan 
---
 UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h | 360 ++
 1 file changed, 360 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h 
b/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
index ae9f406..f201e9c 100644
--- a/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
@@ -44,6 +44,7 @@
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL);
   AsmWriteMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
   @endcode
+  @note MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL is defined as 
MSR_PKG_CST_CONFIG_CONTROL in SDM.
 **/
 #define MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL 0x00E2
 
@@ -129,6 +130,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_MCG_CAP);
   @endcode
+  @note MSR_HASWELL_E_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.
 **/
 #define MSR_HASWELL_E_IA32_MCG_CAP   0x0179
 
@@ -208,6 +210,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_SMM_MCA_CAP);
   AsmWriteMsr64 (MSR_HASWELL_E_SMM_MCA_CAP, Msr.Uint64);
   @endcode
+  @note MSR_HASWELL_E_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.
 **/
 #define MSR_HASWELL_E_SMM_MCA_CAP0x017D
 
@@ -258,6 +261,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_ERROR_CONTROL);
   AsmWriteMsr64 (MSR_HASWELL_E_ERROR_CONTROL, Msr.Uint64);
   @endcode
+  @note MSR_HASWELL_E_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.
 **/
 #define MSR_HASWELL_E_ERROR_CONTROL  0x017F
 
@@ -305,6 +309,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT);
   @endcode
+  @note MSR_HASWELL_E_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in 
SDM.
 **/
 #define MSR_HASWELL_E_TURBO_RATIO_LIMIT  0x01AD
 
@@ -380,6 +385,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT1);
   @endcode
+  @note MSR_HASWELL_E_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 
in SDM.
 **/
 #define MSR_HASWELL_E_TURBO_RATIO_LIMIT1 0x01AE
 
@@ -455,6 +461,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT2);
   @endcode
+  @note MSR_HASWELL_E_TURBO_RATIO_LIMIT2 is defined as MSR_TURBO_RATIO_LIMIT2 
in SDM.
 **/
 #define MSR_HASWELL_E_TURBO_RATIO_LIMIT2 0x01AF
 
@@ -524,6 +531,23 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_MC5_CTL);
   AsmWriteMsr64 (MSR_HASWELL_E_MC5_CTL, Msr);
   @endcode
+  @note MSR_HASWELL_E_MC5_CTL  is defined as MSR_MC5_CTL  in SDM.
+MSR_HASWELL_E_MC6_CTL  is defined as MSR_MC6_CTL  in SDM.
+MSR_HASWELL_E_MC7_CTL  is defined as MSR_MC7_CTL  in SDM.
+MSR_HASWELL_E_MC8_CTL  is defined as MSR_MC8_CTL  in SDM.
+MSR_HASWELL_E_MC9_CTL  is defined as MSR_MC9_CTL  in SDM.
+MSR_HASWELL_E_MC10_CTL is defined as MSR_MC10_CTL in SDM.
+MSR_HASWELL_E_MC11_CTL is defined as MSR_MC11_CTL in SDM.
+MSR_HASWELL_E_MC12_CTL is defined as MSR_MC12_CTL in SDM.
+MSR_HASWELL_E_MC13_CTL is defined as MSR_MC13_CTL in SDM.
+MSR_HASWELL_E_MC14_CTL is defined as MSR_MC14_CTL in SDM.
+MSR_HASWELL_E_MC15_CTL is defined as MSR_MC15_CTL in SDM.
+MSR_HASWELL_E_MC16_CTL is defined as MSR_MC16_CTL in SDM.
+MSR_HASWELL_E_MC17_CTL is defined as MSR_MC17_CTL in SDM.
+MSR_HASWELL_E_MC18_CTL is defined as MSR_MC18_CTL in SDM.
+MSR_HASWELL_E_MC19_CTL is defined as MSR_MC19_CTL in SDM.
+MSR_HASWELL_E_MC20_CTL is defined as MSR_MC20_CTL in SDM.
+MSR_HASWELL_E_MC21_CTL is defined as MSR_MC21_CTL in SDM.
   @{
 **/
 #define MSR_HASWELL_E_MC5_CTL0x0414
@@ -561,6 +585,23 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_MC5_STATUS);
   AsmWriteMsr64 (MSR_HASWELL_E_MC5_STATUS, Msr);
   @endcode
+  @note MSR_HASWELL_E_MC5_STATUS  is defined as MSR_MC5_STATUS  in SDM.
+MSR_HASWELL_E_MC6_STATUS  is defined as MSR_MC6_STATUS  in SDM.
+MSR_HASWELL_E_MC7_STATUS  is defined as MSR_MC7_STATUS  in SDM.
+MSR_HASWELL_E_MC8_STATUS  is defined as MSR_MC8_STATUS  in SDM.
+MSR_HASWELL_E_MC9_STATUS  is defined as MSR_MC9_STATUS  in SDM.
+MSR_HASWELL_E_MC10_STATUS is defined as MSR_MC10_STATUS in SDM.
+MSR_HASWELL_E_MC11_STATUS is defined as MSR_MC11_STATUS in SDM.
+MSR_HASWELL_E_MC12_STATUS is defined as MSR_MC12_STATUS in SDM.
+MSR_HASWELL_E_MC13_STATUS is defined as MSR_MC13_STATUS in SDM.
+MSR_HASWELL_E_MC14_STATUS is defined as MSR_MC14_STATUS in SDM.
+MSR_HASWELL_E_MC15_STATUS is defined as MSR_MC15_STATUS in SDM.
+MSR_HASWELL_E_MC16_STATUS is defined as MSR_MC16_STATUS in SDM.
+

[edk2] [Patch 01/20] UefiCpuPkg/ArchitecturalMsr.h: add MSR reference from SDM in comment

[Jeff Fan]

Cc: Michael Kinney 
Cc: Feng Tian 
Cc: Giri P Mudusuru 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan 
---
 UefiCpuPkg/Include/Register/ArchitecturalMsr.h | 352 +
 1 file changed, 352 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h 
b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
index 4d4ade4..7de1c4b 100644
--- a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
+++ b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
@@ -38,6 +38,7 @@
   Msr = AsmReadMsr64 (MSR_IA32_P5_MC_ADDR);
   AsmWriteMsr64 (MSR_IA32_P5_MC_ADDR, Msr);
   @endcode
+  @note MSR_IA32_P5_MC_ADDR is defined as IA32_P5_MC_ADDR in SDM.
 **/
 #define MSR_IA32_P5_MC_ADDR  0x
 
@@ -56,6 +57,7 @@
   Msr = AsmReadMsr64 (MSR_IA32_P5_MC_TYPE);
   AsmWriteMsr64 (MSR_IA32_P5_MC_TYPE, Msr);
   @endcode
+  @note MSR_IA32_P5_MC_TYPE is defined as IA32_P5_MC_TYPE in SDM.
 **/
 #define MSR_IA32_P5_MC_TYPE  0x0001
 
@@ -75,6 +77,7 @@
   Msr = AsmReadMsr64 (MSR_IA32_MONITOR_FILTER_SIZE);
   AsmWriteMsr64 (MSR_IA32_MONITOR_FILTER_SIZE, Msr);
   @endcode
+  @note MSR_IA32_MONITOR_FILTER_SIZE is defined as IA32_MONITOR_FILTER_SIZE in 
SDM.
 **/
 #define MSR_IA32_MONITOR_FILTER_SIZE 0x0006
 
@@ -94,6 +97,7 @@
   Msr = AsmReadMsr64 (MSR_IA32_TIME_STAMP_COUNTER);
   AsmWriteMsr64 (MSR_IA32_TIME_STAMP_COUNTER, Msr);
   @endcode
+  @note MSR_IA32_TIME_STAMP_COUNTER is defined as IA32_TIME_STAMP_COUNTER in 
SDM.
 **/
 #define MSR_IA32_TIME_STAMP_COUNTER  0x0010
 
@@ -115,6 +119,7 @@
 
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID);
   @endcode
+  @note MSR_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM.
 **/
 #define MSR_IA32_PLATFORM_ID 0x0017
 
@@ -168,6 +173,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
   AsmWriteMsr64 (MSR_IA32_APIC_BASE, Msr.Uint64);
   @endcode
+  @note MSR_IA32_APIC_BASE is defined as IA32_APIC_BASE in SDM.
 **/
 #define MSR_IA32_APIC_BASE   0x001B
 
@@ -227,6 +233,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FEATURE_CONTROL);
   AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, Msr.Uint64);
   @endcode
+  @note MSR_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.
 **/
 #define MSR_IA32_FEATURE_CONTROL 0x003A
 
@@ -326,6 +333,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_TSC_ADJUST);
   AsmWriteMsr64 (MSR_IA32_TSC_ADJUST, Msr);
   @endcode
+  @note MSR_IA32_TSC_ADJUST is defined as IA32_TSC_ADJUST in SDM.
 **/
 #define MSR_IA32_TSC_ADJUST  0x003B
 
@@ -348,6 +356,7 @@ typedef union {
   Msr = 0;
   AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, Msr);
   @endcode
+  @note MSR_IA32_BIOS_UPDT_TRIG is defined as IA32_BIOS_UPDT_TRIG in SDM.
 **/
 #define MSR_IA32_BIOS_UPDT_TRIG  0x0079
 
@@ -370,6 +379,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BIOS_SIGN_ID);
   @endcode
+  @note MSR_IA32_BIOS_SIGN_ID is defined as IA32_BIOS_SIGN_ID in SDM.
 **/
 #define MSR_IA32_BIOS_SIGN_ID0x008B
 
@@ -417,6 +427,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL);
   AsmWriteMsr64 (MSR_IA32_SMM_MONITOR_CTL, Msr.Uint64);
   @endcode
+  @note MSR_IA32_SMM_MONITOR_CTL is defined as IA32_SMM_MONITOR_CTL in SDM.
 **/
 #define MSR_IA32_SMM_MONITOR_CTL 0x009B
 
@@ -475,6 +486,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_IA32_SMBASE);
   @endcode
+  @note MSR_IA32_SMBASE is defined as IA32_SMBASE in SDM.
 **/
 #define MSR_IA32_SMBASE  0x009E
 
@@ -494,6 +506,14 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_PMC0);
   AsmWriteMsr64 (MSR_IA32_PMC0, Msr);
   @endcode
+  @note MSR_IA32_PMC0 is defined as IA32_PMC0 in SDM.
+MSR_IA32_PMC1 is defined as IA32_PMC1 in SDM.
+MSR_IA32_PMC2 is defined as IA32_PMC2 in SDM.
+MSR_IA32_PMC3 is defined as IA32_PMC3 in SDM.
+MSR_IA32_PMC4 is defined as IA32_PMC4 in SDM.
+MSR_IA32_PMC5 is defined as IA32_PMC5 in SDM.
+MSR_IA32_PMC6 is defined as IA32_PMC6 in SDM.
+MSR_IA32_PMC7 is defined as IA32_PMC7 in SDM.
   @{
 **/
 #define MSR_IA32_PMC00x00C1
@@ -524,6 +544,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_MPERF);
   AsmWriteMsr64 (MSR_IA32_MPERF, Msr);
   @endcode
+  @note MSR_IA32_MPERF is defined as IA32_MPERF in SDM.
 **/
 #define MSR_IA32_MPERF   0x00E7
 
@@ -545,6 +566,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_APERF);
   AsmWriteMsr64 (MSR_IA32_APERF, Msr);
   @endcode
+  @note MSR_IA32_APERF is defined as IA32_APERF in SDM.
 **/
 #define MSR_IA32_APERF   0x00E8
 
@@ -565,6 +587,7 @@ typedef union {
 
   Msr.Uint64 = 

[edk2] [Patch 04/20] UefiCpuPkg/Core2Msr.h: add MSR reference from SDM in comment

[Jeff Fan]

Cc: Michael Kinney 
Cc: Feng Tian 
Cc: Giri P Mudusuru 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan 
---
 UefiCpuPkg/Include/Register/Msr/Core2Msr.h | 52 ++
 1 file changed, 52 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Msr/Core2Msr.h 
b/UefiCpuPkg/Include/Register/Msr/Core2Msr.h
index 5fbde51..44da688 100644
--- a/UefiCpuPkg/Include/Register/Msr/Core2Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/Core2Msr.h
@@ -41,6 +41,7 @@
 
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PLATFORM_ID);
   @endcode
+  @note MSR_CORE2_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.
 **/
 #define MSR_CORE2_PLATFORM_ID0x0017
 
@@ -89,6 +90,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_EBL_CR_POWERON);
   AsmWriteMsr64 (MSR_CORE2_EBL_CR_POWERON, Msr.Uint64);
   @endcode
+  @note MSR_CORE2_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
 **/
 #define MSR_CORE2_EBL_CR_POWERON 0x002A
 
@@ -202,6 +204,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_FEATURE_CONTROL);
   AsmWriteMsr64 (MSR_CORE2_FEATURE_CONTROL, Msr.Uint64);
   @endcode
+  @note MSR_CORE2_FEATURE_CONTROL is defined as MSR_FEATURE_CONTROL in SDM.
 **/
 #define MSR_CORE2_FEATURE_CONTROL0x003A
 
@@ -253,6 +256,10 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_0_FROM_IP);
   AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_0_FROM_IP, Msr);
   @endcode
+  @note MSR_CORE2_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP 
in SDM.
+MSR_CORE2_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP 
in SDM.
+MSR_CORE2_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP 
in SDM.
+MSR_CORE2_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP 
in SDM.
   @{
 **/
 #define MSR_CORE2_LASTBRANCH_0_FROM_IP   0x0040
@@ -279,6 +286,10 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_0_TO_IP);
   AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_0_TO_IP, Msr);
   @endcode
+  @note MSR_CORE2_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in 
SDM.
+MSR_CORE2_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in 
SDM.
+MSR_CORE2_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in 
SDM.
+MSR_CORE2_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in 
SDM.
   @{
 **/
 #define MSR_CORE2_LASTBRANCH_0_TO_IP 0x0060
@@ -306,6 +317,7 @@ typedef union {
   Msr.Uint64 = 0;
   AsmWriteMsr64 (MSR_CORE2_SMRR_PHYSBASE, Msr.Uint64);
   @endcode
+  @note MSR_CORE2_SMRR_PHYSBASE is defined as MSR_SMRR_PHYSBASE in SDM.
 **/
 #define MSR_CORE2_SMRR_PHYSBASE  0x00A0
 
@@ -353,6 +365,7 @@ typedef union {
   Msr.Uint64 = 0;
   AsmWriteMsr64 (MSR_CORE2_SMRR_PHYSMASK, Msr.Uint64);
   @endcode
+  @note MSR_CORE2_SMRR_PHYSMASK is defined as MSR_SMRR_PHYSMASK in SDM.
 **/
 #define MSR_CORE2_SMRR_PHYSMASK  0x00A1
 
@@ -402,6 +415,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_FSB_FREQ);
   @endcode
+  @note MSR_CORE2_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
 **/
 #define MSR_CORE2_FSB_FREQ   0x00CD
 
@@ -460,6 +474,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_BBL_CR_CTL3);
   AsmWriteMsr64 (MSR_CORE2_BBL_CR_CTL3, Msr.Uint64);
   @endcode
+  @note MSR_CORE2_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
 **/
 #define MSR_CORE2_BBL_CR_CTL30x011E
 
@@ -518,6 +533,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PERF_STATUS);
   AsmWriteMsr64 (MSR_CORE2_PERF_STATUS, Msr.Uint64);
   @endcode
+  @note MSR_CORE2_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.
 **/
 #define MSR_CORE2_PERF_STATUS0x0198
 
@@ -577,6 +593,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_THERM2_CTL);
   AsmWriteMsr64 (MSR_CORE2_THERM2_CTL, Msr.Uint64);
   @endcode
+  @note MSR_CORE2_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
 **/
 #define MSR_CORE2_THERM2_CTL 0x019D
 
@@ -628,6 +645,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_IA32_MISC_ENABLE);
   AsmWriteMsr64 (MSR_CORE2_IA32_MISC_ENABLE, Msr.Uint64);
   @endcode
+  @note MSR_CORE2_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
 **/
 #define MSR_CORE2_IA32_MISC_ENABLE   0x01A0
 
@@ -795,6 +813,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_TOS);
   AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_TOS, Msr);
   @endcode
+  @note MSR_CORE2_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
 **/
 #define MSR_CORE2_LASTBRANCH_TOS 0x01C9
 
@@ -814,6 +833,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_CORE2_LER_FROM_LIP);
   @endcode
+  @note MSR_CORE2_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
 **/
 #define 

[edk2] [Patch 05/20] UefiCpuPkg/CoreMsr.h: add MSR reference from SDM in comment

[Jeff Fan]

Cc: Michael Kinney 
Cc: Feng Tian 
Cc: Giri P Mudusuru 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan 
---
 UefiCpuPkg/Include/Register/Msr/CoreMsr.h | 58 +++
 1 file changed, 58 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Msr/CoreMsr.h 
b/UefiCpuPkg/Include/Register/Msr/CoreMsr.h
index 11956fb..ac45e6f 100644
--- a/UefiCpuPkg/Include/Register/Msr/CoreMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/CoreMsr.h
@@ -40,6 +40,7 @@
   Msr = AsmReadMsr64 (MSR_CORE_P5_MC_ADDR);
   AsmWriteMsr64 (MSR_CORE_P5_MC_ADDR, Msr);
   @endcode
+  @note MSR_CORE_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
 **/
 #define MSR_CORE_P5_MC_ADDR  0x
 
@@ -58,6 +59,7 @@
   Msr = AsmReadMsr64 (MSR_CORE_P5_MC_TYPE);
   AsmWriteMsr64 (MSR_CORE_P5_MC_TYPE, Msr);
   @endcode
+  @note MSR_CORE_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
 **/
 #define MSR_CORE_P5_MC_TYPE  0x0001
 
@@ -79,6 +81,7 @@
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE_EBL_CR_POWERON);
   AsmWriteMsr64 (MSR_CORE_EBL_CR_POWERON, Msr.Uint64);
   @endcode
+  @note MSR_CORE_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
 **/
 #define MSR_CORE_EBL_CR_POWERON  0x002A
 
@@ -189,6 +192,14 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_0);
   AsmWriteMsr64 (MSR_CORE_LASTBRANCH_0, Msr);
   @endcode
+  @note MSR_CORE_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.
+MSR_CORE_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.
+MSR_CORE_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.
+MSR_CORE_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.
+MSR_CORE_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM.
+MSR_CORE_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM.
+MSR_CORE_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM.
+MSR_CORE_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.
   @{
 **/
 #define MSR_CORE_LASTBRANCH_00x0040
@@ -218,6 +229,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE_FSB_FREQ);
   @endcode
+  @note MSR_CORE_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
 **/
 #define MSR_CORE_FSB_FREQ0x00CD
 
@@ -270,6 +282,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE_BBL_CR_CTL3);
   AsmWriteMsr64 (MSR_CORE_BBL_CR_CTL3, Msr.Uint64);
   @endcode
+  @note MSR_CORE_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
 **/
 #define MSR_CORE_BBL_CR_CTL3 0x011E
 
@@ -328,6 +341,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE_THERM2_CTL);
   AsmWriteMsr64 (MSR_CORE_THERM2_CTL, Msr.Uint64);
   @endcode
+  @note MSR_CORE_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
 **/
 #define MSR_CORE_THERM2_CTL  0x019D
 
@@ -379,6 +393,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_MISC_ENABLE);
   AsmWriteMsr64 (MSR_CORE_IA32_MISC_ENABLE, Msr.Uint64);
   @endcode
+  @note MSR_CORE_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
 **/
 #define MSR_CORE_IA32_MISC_ENABLE0x01A0
 
@@ -479,6 +494,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_TOS);
   AsmWriteMsr64 (MSR_CORE_LASTBRANCH_TOS, Msr);
   @endcode
+  @note MSR_CORE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
 **/
 #define MSR_CORE_LASTBRANCH_TOS  0x01C9
 
@@ -498,6 +514,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_CORE_LER_FROM_LIP);
   @endcode
+  @note MSR_CORE_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
 **/
 #define MSR_CORE_LER_FROM_LIP0x01DD
 
@@ -518,6 +535,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_CORE_LER_TO_LIP);
   @endcode
+  @note MSR_CORE_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
 **/
 #define MSR_CORE_LER_TO_LIP  0x01DE
 
@@ -538,6 +556,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE_ROB_CR_BKUPTMPDR6);
   AsmWriteMsr64 (MSR_CORE_ROB_CR_BKUPTMPDR6, Msr.Uint64);
   @endcode
+  @note MSR_CORE_ROB_CR_BKUPTMPDR6 is defined as ROB_CR_BKUPTMPDR6 in SDM.
 **/
 #define MSR_CORE_ROB_CR_BKUPTMPDR6   0x01E0
 
@@ -582,6 +601,14 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSBASE0);
   AsmWriteMsr64 (MSR_CORE_MTRRPHYSBASE0, Msr);
   @endcode
+  @note MSR_CORE_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM.
+MSR_CORE_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM.
+MSR_CORE_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM.
+MSR_CORE_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM.
+MSR_CORE_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM.
+MSR_CORE_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM.
+MSR_CORE_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM.
+MSR_CORE_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in 

[edk2] [Patch 03/20] UefiCpuPkg/BroadwellMsr.h: add MSR reference from SDM in comment

[Jeff Fan]

Cc: Michael Kinney 
Cc: Feng Tian 
Cc: Giri P Mudusuru 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan 
---
 UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h 
b/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
index 69c404e..0673685 100644
--- a/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
@@ -43,6 +43,7 @@
   Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS);
   AsmWriteMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS, Msr.Uint64);
   @endcode
+  @note MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS is defined as 
IA32_PERF_GLOBAL_STAUS in SDM.
 **/
 #define MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS 0x038E
 
@@ -128,6 +129,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL);
   AsmWriteMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
   @endcode
+  @note MSR_BROADWELL_PKG_CST_CONFIG_CONTROL is defined as 
MSR_PKG_CST_CONFIG_CONTROL in SDM.
 **/
 #define MSR_BROADWELL_PKG_CST_CONFIG_CONTROL 0x00E2
 
@@ -213,6 +215,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_TURBO_RATIO_LIMIT);
   @endcode
+  @note MSR_BROADWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in 
SDM.
 **/
 #define MSR_BROADWELL_TURBO_RATIO_LIMIT  0x01AD
 
-- 
2.9.3.windows.2

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Re: [edk2] Persistent Variable Storage and PlatformBootTimeOut

[Ard Biesheuvel]

On 6 September 2016 at 12:13, Bhupesh Sharma  wrote:
> Hi EDK2 experts,
>
> We have recently added the support for storing UEFI run-time variables on 
> underlying NOR
> Flash slave on our ARMV8 NXP board.
>
> We are successfully able to change the values of variables like boot-order 
> using the latest
> MdeModulePkg BDS:
>
> MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
>
> and retrieve them on next board boot.
>
> While this works almost on all the places, we see that the Auto Boot Time we 
> have set using the
> following PCD:
> gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|20
>
> Doesn't work when one enters the BIOS screen and enters the Boot Maintenance 
> Manager to change this
> value from say 20 to 10.
>
> On the next board boot, the PlatformBootTimeOut value is still 20.
>
> The same issue is replicable on latest EDK2 (master branch) on qemu for 
> aarch64.
>
> Is this a known issue or are we missing something here?
>

You should declare it as

[PcdsDynamicHii.common.DEFAULT]
  
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|10
# Variable: L"Timeout"

to connect the dynamic PCD to the EFI variable.
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[edk2] Persistent Variable Storage and PlatformBootTimeOut

[Bhupesh Sharma]

Hi EDK2 experts,

We have recently added the support for storing UEFI run-time variables on 
underlying NOR
Flash slave on our ARMV8 NXP board.

We are successfully able to change the values of variables like boot-order 
using the latest
MdeModulePkg BDS:

MdeModulePkg/Universal/BdsDxe/BdsDxe.inf

and retrieve them on next board boot.

While this works almost on all the places, we see that the Auto Boot Time we 
have set using the
following PCD:
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|20

Doesn't work when one enters the BIOS screen and enters the Boot Maintenance 
Manager to change this
value from say 20 to 10.

On the next board boot, the PlatformBootTimeOut value is still 20.

The same issue is replicable on latest EDK2 (master branch) on qemu for aarch64.

Is this a known issue or are we missing something here?

Regards,
Bhupesh
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Re: [edk2] Ingebrigtsen: The End of Gmane?

[Rafael Machado]

Hi Laszlo.

Thanks for the answer, even being terrible news.
The archive helped me a lot to solve several situations in the past.

We know how this kind of information is important for the community.
Hope someone could give us some light on that.

Not sure if I can help to solve this, in case there is something I can do
let me know.

Rafael R. Machado

Em ter, 6 de set de 2016 às 06:25, Laszlo Ersek 
escreveu:

> On 09/05/16 19:51, Rafael Machado wrote:
> > Hi everyone.
> >
> > Sorry for the possibly stupid question, maybe I lose something. Did we
> > get to a conclusion about this?
> > I tried to access the link https://lists.01.org/pipermail/edk2-devel/
> > but didn't find to much information. Just e-mails from 3 moths ago.
>
> The gmane web interface is gone, and I'm unaware of anyone who has
> picked up the archive and exposed it under the same URLs (via domain
> name transfer etc). So, at the moment (to my knowledge) all our
> historical gmane links are broken. Neither do I know how someone could
> access edk2-devel messages that predate Mike's enablement of the
> built-in  archive.
>
> Sorry :(
> Laszlo
>
> > Em seg, 1 de ago de 2016 às 10:25, Laszlo Ersek  > > escreveu:
> >
> > On 07/31/16 04:25, Bruce Cran wrote:
> > > On 7/28/2016 1:19 PM, Andrew Fish wrote:
> > >
> > >> Seems he will send you the disks. What could go wrong?
> > >
> > > I'm actually tempted to take him up on that offer.
> > > Just today I went looking for information about UefiDebugLib to
> see if
> > > it was possible for a driver to print debug information to the
> serial
> > > port (or other sort of debug device) instead of the console, and
> came
> > > across the thread at
> > > http://comments.gmane.org/gmane.comp.bios.tianocore.devel/3024
> where
> > > thanks to Google's cache I learned that:
> > >
> > > "The EDK used some Tiano and implementation defined protocols to
> > support
> > > DEBUG and ASSERT macros. So DEBUG
> > > and ASSERT from the EDK can only be reliably used if you compile
> > all the
> > > EDK firmware together. As Liming
> > > points out it is much safer to use a UEFI console based debug
> message
> > > for developing generic drivers and
> > > applications."
> > >
> > > It's a shame to lose information like that.
> >
> > I think the Internet Archive intends to pick up the DB + WebUI:
> >
> >
> https://lars.ingebrigtsen.no/2016/07/28/the-end-of-gmane/comment-page-1/#comment-13501
> >
> > Also, from Lars Ingebrigtsen (speaking to a yet to be determined
> > entity):
> >
> > "I hand over the gmane.org  domain to you [...]
> > All previous
> > permalink.gmane.org  (etc.) links
> > continue to work as before, but they’ll
> > look new and spiffy in your new and spiffy web interface."
> >
> >
> https://lars.ingebrigtsen.no/2016/07/28/the-end-of-gmane/comment-page-1/#comment-13502
> >
> > (Actually, I'm a huge fan of the current (oldie but goldie) WebUI, so
> > "new and spiffy" is a minus for me, but at least the links should
> > continue to work.)
> >
> > Going forward I'll have to constrain myself to the builtin mailman2
> > links at . (Thanks again
> > Bruce and Mike for enabling those.)
> >
> > Thanks
> > Laszlo
> > ___
> > edk2-devel mailing list
> > edk2-devel@lists.01.org 
> > https://lists.01.org/mailman/listinfo/edk2-devel
> >
>
>
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Re: [edk2] [Patch] MdeModulePkg: Support classless IP for DHCPv4 TransmitReceive()

[Wu, Jiaxin]

Hi Naveen,

The patch has been committed:

SHA-1: 8c5f78a2cc15199e3f77ae4b156023af366fd6c7
* MdeModulePkg: Support classless IP for DHCPv4 TransmitReceive()

Thanks,
Jiaxin

> -Original Message-
> From: Santhapur Naveen [mailto:nave...@amiindia.co.in]
> Sent: Friday, September 2, 2016 2:16 PM
> To: Wu, Jiaxin ; edk2-devel@lists.01.org
> Cc: Ye, Ting ; Fu, Siyuan 
> Subject: RE: [edk2] [Patch] MdeModulePkg: Support classless IP for DHCPv4
> TransmitReceive()
> 
> Hello Jiaxin,
> 
>   My sincere apologies for the delayed response.
> 
>   I've verified the patch from my side and PXE boot is happening
> successfully even in classless IP network.
> 
>   May I know whether this will be included in EDK2? If yes, can you
> please provide any schedule for the same?
> 
> Best regards,
> Naveen
> 
> -Original Message-
> From: Santhapur Naveen
> Sent: Thursday, August 18, 2016 11:14 AM
> To: 'Wu, Jiaxin'; edk2-devel@lists.01.org
> Cc: Ye, Ting; Fu, Siyuan; Sivaraman Nainar; Madhan B. Santharam
> Subject: RE: [edk2] [Patch] MdeModulePkg: Support classless IP for DHCPv4
> TransmitReceive()
> 
> Jiaxin,
> 
> We will verify the patch and update you the result.
> 
> Thanks,
> Naveen
> 
> -Original Message-
> From: Wu, Jiaxin [mailto:jiaxin...@intel.com]
> Sent: Thursday, August 18, 2016 11:12 AM
> To: Santhapur Naveen; Wu, Jiaxin; edk2-devel@lists.01.org
> Cc: Ye, Ting; Fu, Siyuan; Sivaraman Nainar; Madhan B. Santharam
> Subject: RE: [edk2] [Patch] MdeModulePkg: Support classless IP for DHCPv4
> TransmitReceive()
> 
> Naveen,
> 
> Can you help to verify this patch to support the classless IP.
> 
> Thanks,
> Jiaxin
> 
> > -Original Message-
> > From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
> > Jiaxin Wu
> > Sent: Thursday, August 18, 2016 1:39 PM
> > To: edk2-devel@lists.01.org
> > Cc: Ye, Ting ; Fu, Siyuan ;
> > Santhapur Naveen 
> > Subject: [edk2] [Patch] MdeModulePkg: Support classless IP for DHCPv4
> > TransmitReceive()
> >
> > The IP address should not be treated as classful one if DHCP options
> > contain a classless IP with its true subnet mask. Otherwise, DHCPv4
> > TransmitReceive() will failed. This real subnet mask will be parsed
> > and recorded in DhcpSb->Netmask. So, we need check it before get the
> > IP's corresponding subnet mask.
> >
> > Cc: Santhapur Naveen 
> > Cc: Ye Ting 
> > Cc: Fu Siyuan 
> > Contributed-under: TianoCore Contribution Agreement 1.0
> > Signed-off-by: Jiaxin Wu 
> > ---
> >  .../Universal/Network/Dhcp4Dxe/Dhcp4Impl.c | 28
> +++-
> > --
> >  1 file changed, 20 insertions(+), 8 deletions(-)
> >
> > diff --git a/MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Impl.c
> > b/MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Impl.c
> > index 4f491b4..79f7cde 100644
> > --- a/MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Impl.c
> > +++ b/MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Impl.c
> > @@ -1,9 +1,9 @@
> >  /** @file
> >This file implement the EFI_DHCP4_PROTOCOL interface.
> >
> > -Copyright (c) 2006 - 2015, Intel Corporation. All rights
> > reserved.
> > +Copyright (c) 2006 - 2016, Intel Corporation. All rights
> > +reserved.
> >  This program and the accompanying materials  are licensed and made
> > available under the terms and conditions of the BSD License  which
> > accompanies this distribution.  The full text of the license may be
> > found at http://opensource.org/licenses/bsd-license.php
> >
> > @@ -1186,18 +1186,20 @@ Dhcp4InstanceConfigUdpIo (
> >IN UDP_IO   *UdpIo,
> >IN VOID *Context
> >)
> >  {
> >DHCP_PROTOCOL *Instance;
> > +  DHCP_SERVICE  *DhcpSb;
> >EFI_DHCP4_TRANSMIT_RECEIVE_TOKEN  *Token;
> >EFI_UDP4_CONFIG_DATA  UdpConfigData;
> >IP4_ADDR  ClientAddr;
> >IP4_ADDR  Ip;
> >INTN  Class;
> >IP4_ADDR  SubnetMask;
> >
> >Instance = (DHCP_PROTOCOL *) Context;
> > +  DhcpSb   = Instance->Service;
> >Token= Instance->Token;
> >
> >ZeroMem (, sizeof (EFI_UDP4_CONFIG_DATA));
> >
> >UdpConfigData.AcceptBroadcast= TRUE;
> > @@ -1206,14 +1208,19 @@ Dhcp4InstanceConfigUdpIo (
> >UdpConfigData.DoNotFragment  = TRUE;
> >
> >ClientAddr = EFI_NTOHL (Token->Packet->Dhcp4.Header.ClientAddr);
> >Ip = HTONL (ClientAddr);
> >CopyMem (, , sizeof
> > (EFI_IPv4_ADDRESS));
> > -
> > -  Class = NetGetIpClass (ClientAddr);
> > -  ASSERT (Class < IP4_ADDR_CLASSE);
> > -  SubnetMask = gIp4AllMasks[Class << 3];
> > +
> > +  if (DhcpSb->Netmask == 0) {
> > +Class = NetGetIpClass (ClientAddr);
> > +ASSERT (Class < IP4_ADDR_CLASSE);
> > +SubnetMask = 

Re: [edk2] [PATCH 0/7] MdeModulePkg ArmVirtPkg: fixes for 64-bit PCI DMA

[Ard Biesheuvel]

On 6 September 2016 at 09:54, Ni, Ruiyu  wrote:
> Ard,
> The patch to MdeModulePkg/PciHostBridgeDxe is good.
>
> Reviewed-by: Ruiyu Ni 
>

Thanks Ray!

Who is responsible for the AtapPassThru, USB, NVME and SDHCI drivers?

>> -Original Message-
>> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
>> Ard Biesheuvel
>> Sent: Tuesday, September 6, 2016 3:48 PM
>> To: edk2-devel-01 ; Tian, Feng
>> ; Zeng, Star ; Gao, Liming
>> 
>> Cc: Laszlo Ersek ; Leif Lindholm
>> ; Ard Biesheuvel 
>> Subject: Re: [edk2] [PATCH 0/7] MdeModulePkg ArmVirtPkg: fixes for 64-bit
>> PCI DMA
>>
>> Feng, Star: do you have any feedback on these patches? Thanks.
>>
>> On 5 September 2016 at 10:17, Ard Biesheuvel 
>> wrote:
>> > After moving ArmVirtQemu to the generic PciHostBridgeDxe, we noticed
>> > that setting DmaAbove4G resulted in problems with the emulated EHCI
>> > USB host controller, which were caused by the fact that the PCI layer
>> > was providing DMA buffers allocated above 4 GB while the emulated EHCI
>> > controller in QEMU does not indicate support for 64-bit addressing.
>> >
>> > As it turns out, the PCI drivers in MdeModulePkg *completely* ignore
>> > the EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute, and simply
>> assume
>> > that no PCI root bridge driver will produce mappings above 4 GB. On
>> > ARM, this is problematic, since not all platforms have memory below 4
>> > GB, and so having full support for DMA above 4 GB is indispensable.
>> >
>> > So first, make the various drivers under MdeModulePkg/Pci/Bus set the
>> > EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE attributes for devices that
>> > can support 64-bit DMA addressing (patches #1 - #5). Then, we can
>> > update the host bridge driver to actually take these attributes into
>> > account, and only create mappings above 4 GB for devices that have
>> indicated support for it.
>> >
>> > Finally, in patch #7 we can remove the 4 GB DMA limit from ArmVirtPkg.
>> >
>> > Branch can be found here:
>> > https://git.linaro.org/people/ard.biesheuvel/uefi-next.git/shortlog/re
>> > fs/heads/pci-64bit-dma-fixes
>> >
>> > Ard Biesheuvel (7):
>> >   MdeModulePkg/AtaAtapiPassThru: enable 64-bit PCI DMA
>> >   MdeModulePkg/EhciDxe: enable 64-bit PCI DMA
>> >   MdeModulePkg/NvmExpressDxe: enable 64-bit PCI DMA
>> >   MdeModulePkg/SdMmcPciHcDxe: enable 64-bit PCI DMA
>> >   MdeModulePkg/XhciDxe: enable 64-bit PCI DMA
>> >   MdeModulePkg/PciHostBridgeDxe: restrict 64-bit DMA to devices that
>> > support it
>> >   ArmVirtPkg/FdtPciHostBridgeLib: enable 64-bit PCI DMA
>> >
>> >  ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c |  2 +-
>> >  MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c | 20
>> +-
>> >  MdeModulePkg/Bus/Pci/EhciDxe/Ehci.c  | 22
>> +++-
>> >  MdeModulePkg/Bus/Pci/EhciDxe/Ehci.h  |  2 ++
>> >  MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c |  2 +-
>> >  MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c   | 13
>> 
>> >  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c  | 14
>> +
>> >  MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c   | 20
>> ++
>> >  MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c  | 22
>> +++-
>> >  MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h  |  2 ++
>> >  10 files changed, 110 insertions(+), 9 deletions(-)
>> >
>> > --
>> > 2.7.4
>> >
>> ___
>> edk2-devel mailing list
>> edk2-devel@lists.01.org
>> https://lists.01.org/mailman/listinfo/edk2-devel
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Re: [edk2] [PATCH v2] NetworkPkg/DnsDxe: Handle CNAME type responded from the name server

[Hegde, Nagaraj P]

Tested-by: Hegde Nagaraj P 

-Original Message-
From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Fu, 
Siyuan
Sent: Tuesday, September 06, 2016 2:37 PM
To: Wu, Jiaxin ; edk2-devel@lists.01.org
Cc: Ye, Ting 
Subject: Re: [edk2] [PATCH v2] NetworkPkg/DnsDxe: Handle CNAME type responded 
from the name server

Reviewed-by: Fu Siyuan 


> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of 
> Jiaxin Wu
> Sent: Tuesday, September 6, 2016 4:51 PM
> To: edk2-devel@lists.01.org
> Cc: Ye, Ting ; Fu, Siyuan 
> Subject: [edk2] [PATCH v2] NetworkPkg/DnsDxe: Handle CNAME type 
> responded from the name server
> 
> v2:
> * Code refine.
> * For DnsCache, the minimum value of TTL is selected between CNAME and 
> A/ record.
> 
> According RFC 1034 - 3.6.2, if the query name is an alias, the name 
> server will include the CNAME record in the response and restart the 
> query at the domain name specified in the data field of the CNAME 
> record. RFC also provides one example server action when A query 
> received:
> 
> Suppose a name server was processing a query with for USCISIC.ARPA, 
> asking for type A information, and had the following resource records:
> USC-ISIC.ARPA IN CNAME C.ISI.EDU
> C.ISI.EDU IN A 10.0.0.52
> Both of these RRs would be returned in the response to the type A query.
> 
> Currently, DnsDxe driver doesn't handle the CNAME type response, which 
> will cause any exception result. The driver need continue the packet 
> parsing while CNAME type record parsed. So, this patch is used to 
> handle it correctly.
> 
> Cc: Hegde Nagaraj P 
> Cc: Fu Siyuan 
> Cc: Ye Ting 
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Jiaxin Wu 
> ---
>  NetworkPkg/DnsDxe/DnsImpl.c | 81 
> +---
> -
>  1 file changed, 52 insertions(+), 29 deletions(-)
> 
> diff --git a/NetworkPkg/DnsDxe/DnsImpl.c b/NetworkPkg/DnsDxe/DnsImpl.c 
> index 360f68e..cfaa4c7 100644
> --- a/NetworkPkg/DnsDxe/DnsImpl.c
> +++ b/NetworkPkg/DnsDxe/DnsImpl.c
> @@ -1125,10 +1125,11 @@ ParseDnsResponse (
>DNS6_TOKEN_ENTRY  *Dns6TokenEntry;
> 
>UINT32IpCount;
>UINT32RRCount;
>UINT32AnswerSectionNum;
> +  UINT32CNameTtl;
> 
>EFI_IPv4_ADDRESS  *HostAddr4;
>EFI_IPv6_ADDRESS  *HostAddr6;
> 
>EFI_DNS4_CACHE_ENTRY  *Dns4CacheEntry; @@ -1146,10 +1147,11 @@ 
> ParseDnsResponse (
>Dns6TokenEntry   = NULL;
> 
>IpCount  = 0;
>RRCount  = 0;
>AnswerSectionNum = 0;
> +  CNameTtl = 0;
> 
>HostAddr4= NULL;
>HostAddr6= NULL;
> 
>Dns4CacheEntry   = NULL;
> @@ -1231,17 +1233,10 @@ ParseDnsResponse (
>if (DnsHeader->Flags.Bits.RCode != DNS_FLAGS_RCODE_NO_ERROR ||
> DnsHeader->AnswersNum < 1 || \
>DnsHeader->Flags.Bits.QR != DNS_FLAGS_QR_RESPONSE) {
>Status = EFI_ABORTED;
>goto ON_EXIT;
>}
> -
> -  //
> -  // Free the sending packet.
> -  //
> -  if (Item->Value != NULL) {
> -NetbufFree ((NET_BUF *) (Item->Value));
> -  }
> 
>//
>// Do some buffer allocations.
>//
>if (Instance->Service->IpVersion == IP_VERSION_4) { @@ -1288,40 
> +1283,42 @@ ParseDnsResponse (
>//
>// It's the GeneralLookUp querying.
>//
>Dns6TokenEntry->Token->RspData.GLookupData = AllocatePool 
> (sizeof (DNS_RESOURCE_RECORD));
>if (Dns6TokenEntry->Token->RspData.GLookupData == NULL) {
> -Status = EFI_UNSUPPORTED;
> +Status = EFI_OUT_OF_RESOURCES;
>  goto ON_EXIT;
>}
>Dns6TokenEntry->Token->RspData.GLookupData->RRList = 
> AllocatePool (DnsHeader->AnswersNum * sizeof (DNS_RESOURCE_RECORD));
>if (Dns6TokenEntry->Token->RspData.GLookupData->RRList == NULL) {
> -Status = EFI_UNSUPPORTED;
> +Status = EFI_OUT_OF_RESOURCES;
>  goto ON_EXIT;
>}
>  } else {
>//
>// It's not the GeneralLookUp querying. Check the Query type.
>//
>if (QuerySection->Type == DNS_TYPE_) {
>  Dns6TokenEntry->Token->RspData.H2AData = AllocatePool (sizeof 
> (DNS6_HOST_TO_ADDR_DATA));
>  if (Dns6TokenEntry->Token->RspData.H2AData == NULL) {
> -  Status = EFI_UNSUPPORTED;
> +  Status = EFI_OUT_OF_RESOURCES;
>goto ON_EXIT;
>  }
>  Dns6TokenEntry->Token->RspData.H2AData->IpList = AllocatePool 
> (DnsHeader->AnswersNum * sizeof (EFI_IPv6_ADDRESS));
>  if (Dns6TokenEntry->Token->RspData.H2AData->IpList == NULL) {
> -  Status = EFI_UNSUPPORTED;
> +  Status = EFI_OUT_OF_RESOURCES;
>goto ON_EXIT;
>  }
>} 

Re: [edk2] Ingebrigtsen: The End of Gmane?

[Laszlo Ersek]

On 09/05/16 19:51, Rafael Machado wrote:
> Hi everyone.
> 
> Sorry for the possibly stupid question, maybe I lose something. Did we
> get to a conclusion about this?
> I tried to access the link https://lists.01.org/pipermail/edk2-devel/ 
> but didn't find to much information. Just e-mails from 3 moths ago.

The gmane web interface is gone, and I'm unaware of anyone who has
picked up the archive and exposed it under the same URLs (via domain
name transfer etc). So, at the moment (to my knowledge) all our
historical gmane links are broken. Neither do I know how someone could
access edk2-devel messages that predate Mike's enablement of the
built-in  archive.

Sorry :(
Laszlo

> Em seg, 1 de ago de 2016 às 10:25, Laszlo Ersek  > escreveu:
> 
> On 07/31/16 04:25, Bruce Cran wrote:
> > On 7/28/2016 1:19 PM, Andrew Fish wrote:
> >
> >> Seems he will send you the disks. What could go wrong?
> >
> > I'm actually tempted to take him up on that offer.
> > Just today I went looking for information about UefiDebugLib to see if
> > it was possible for a driver to print debug information to the serial
> > port (or other sort of debug device) instead of the console, and came
> > across the thread at
> > http://comments.gmane.org/gmane.comp.bios.tianocore.devel/3024 where
> > thanks to Google's cache I learned that:
> >
> > "The EDK used some Tiano and implementation defined protocols to
> support
> > DEBUG and ASSERT macros. So DEBUG
> > and ASSERT from the EDK can only be reliably used if you compile
> all the
> > EDK firmware together. As Liming
> > points out it is much safer to use a UEFI console based debug message
> > for developing generic drivers and
> > applications."
> >
> > It's a shame to lose information like that.
> 
> I think the Internet Archive intends to pick up the DB + WebUI:
> 
> 
> https://lars.ingebrigtsen.no/2016/07/28/the-end-of-gmane/comment-page-1/#comment-13501
> 
> Also, from Lars Ingebrigtsen (speaking to a yet to be determined
> entity):
> 
> "I hand over the gmane.org  domain to you [...]
> All previous
> permalink.gmane.org  (etc.) links
> continue to work as before, but they’ll
> look new and spiffy in your new and spiffy web interface."
> 
> 
> https://lars.ingebrigtsen.no/2016/07/28/the-end-of-gmane/comment-page-1/#comment-13502
> 
> (Actually, I'm a huge fan of the current (oldie but goldie) WebUI, so
> "new and spiffy" is a minus for me, but at least the links should
> continue to work.)
> 
> Going forward I'll have to constrain myself to the builtin mailman2
> links at . (Thanks again
> Bruce and Mike for enabling those.)
> 
> Thanks
> Laszlo
> ___
> edk2-devel mailing list
> edk2-devel@lists.01.org 
> https://lists.01.org/mailman/listinfo/edk2-devel
> 

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Re: [edk2] [PATCH v2] NetworkPkg/DnsDxe: Handle CNAME type responded from the name server

[Fu, Siyuan]

Reviewed-by: Fu Siyuan 


> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
> Jiaxin Wu
> Sent: Tuesday, September 6, 2016 4:51 PM
> To: edk2-devel@lists.01.org
> Cc: Ye, Ting ; Fu, Siyuan 
> Subject: [edk2] [PATCH v2] NetworkPkg/DnsDxe: Handle CNAME type responded
> from the name server
> 
> v2:
> * Code refine.
> * For DnsCache, the minimum value of TTL is selected between CNAME and
> A/ record.
> 
> According RFC 1034 - 3.6.2, if the query name is an alias, the name server
> will include the CNAME record in the response and restart the query at the
> domain name specified in the data field of the CNAME record. RFC also
> provides
> one example server action when A query received:
> 
> Suppose a name server was processing a query with for USCISIC.ARPA, asking
> for
> type A information, and had the following resource records:
> USC-ISIC.ARPA IN CNAME C.ISI.EDU
> C.ISI.EDU IN A 10.0.0.52
> Both of these RRs would be returned in the response to the type A query.
> 
> Currently, DnsDxe driver doesn't handle the CNAME type response, which
> will cause
> any exception result. The driver need continue the packet parsing while
> CNAME type
> record parsed. So, this patch is used to handle it correctly.
> 
> Cc: Hegde Nagaraj P 
> Cc: Fu Siyuan 
> Cc: Ye Ting 
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Jiaxin Wu 
> ---
>  NetworkPkg/DnsDxe/DnsImpl.c | 81 +---
> -
>  1 file changed, 52 insertions(+), 29 deletions(-)
> 
> diff --git a/NetworkPkg/DnsDxe/DnsImpl.c b/NetworkPkg/DnsDxe/DnsImpl.c
> index 360f68e..cfaa4c7 100644
> --- a/NetworkPkg/DnsDxe/DnsImpl.c
> +++ b/NetworkPkg/DnsDxe/DnsImpl.c
> @@ -1125,10 +1125,11 @@ ParseDnsResponse (
>DNS6_TOKEN_ENTRY  *Dns6TokenEntry;
> 
>UINT32IpCount;
>UINT32RRCount;
>UINT32AnswerSectionNum;
> +  UINT32CNameTtl;
> 
>EFI_IPv4_ADDRESS  *HostAddr4;
>EFI_IPv6_ADDRESS  *HostAddr6;
> 
>EFI_DNS4_CACHE_ENTRY  *Dns4CacheEntry;
> @@ -1146,10 +1147,11 @@ ParseDnsResponse (
>Dns6TokenEntry   = NULL;
> 
>IpCount  = 0;
>RRCount  = 0;
>AnswerSectionNum = 0;
> +  CNameTtl = 0;
> 
>HostAddr4= NULL;
>HostAddr6= NULL;
> 
>Dns4CacheEntry   = NULL;
> @@ -1231,17 +1233,10 @@ ParseDnsResponse (
>if (DnsHeader->Flags.Bits.RCode != DNS_FLAGS_RCODE_NO_ERROR ||
> DnsHeader->AnswersNum < 1 || \
>DnsHeader->Flags.Bits.QR != DNS_FLAGS_QR_RESPONSE) {
>Status = EFI_ABORTED;
>goto ON_EXIT;
>}
> -
> -  //
> -  // Free the sending packet.
> -  //
> -  if (Item->Value != NULL) {
> -NetbufFree ((NET_BUF *) (Item->Value));
> -  }
> 
>//
>// Do some buffer allocations.
>//
>if (Instance->Service->IpVersion == IP_VERSION_4) {
> @@ -1288,40 +1283,42 @@ ParseDnsResponse (
>//
>// It's the GeneralLookUp querying.
>//
>Dns6TokenEntry->Token->RspData.GLookupData = AllocatePool (sizeof
> (DNS_RESOURCE_RECORD));
>if (Dns6TokenEntry->Token->RspData.GLookupData == NULL) {
> -Status = EFI_UNSUPPORTED;
> +Status = EFI_OUT_OF_RESOURCES;
>  goto ON_EXIT;
>}
>Dns6TokenEntry->Token->RspData.GLookupData->RRList = AllocatePool
> (DnsHeader->AnswersNum * sizeof (DNS_RESOURCE_RECORD));
>if (Dns6TokenEntry->Token->RspData.GLookupData->RRList == NULL) {
> -Status = EFI_UNSUPPORTED;
> +Status = EFI_OUT_OF_RESOURCES;
>  goto ON_EXIT;
>}
>  } else {
>//
>// It's not the GeneralLookUp querying. Check the Query type.
>//
>if (QuerySection->Type == DNS_TYPE_) {
>  Dns6TokenEntry->Token->RspData.H2AData = AllocatePool (sizeof
> (DNS6_HOST_TO_ADDR_DATA));
>  if (Dns6TokenEntry->Token->RspData.H2AData == NULL) {
> -  Status = EFI_UNSUPPORTED;
> +  Status = EFI_OUT_OF_RESOURCES;
>goto ON_EXIT;
>  }
>  Dns6TokenEntry->Token->RspData.H2AData->IpList = AllocatePool
> (DnsHeader->AnswersNum * sizeof (EFI_IPv6_ADDRESS));
>  if (Dns6TokenEntry->Token->RspData.H2AData->IpList == NULL) {
> -  Status = EFI_UNSUPPORTED;
> +  Status = EFI_OUT_OF_RESOURCES;
>goto ON_EXIT;
>  }
>} else {
>  Status = EFI_UNSUPPORTED;
>  goto ON_EXIT;
>}
>  }
>}
> 
> +  Status = EFI_NOT_FOUND;
> +
>//
>// Processing AnswerSection.
>//
>while (AnswerSectionNum < DnsHeader->AnswersNum) {
>  //
> @@ -1348,51 +1345,53 @@ ParseDnsResponse (
>//
>// Fill the ResourceRecord.
>//
>Dns4RR[RRCount].QName = AllocateZeroPool (AsciiStrLen 

Re: [edk2] [PATCH 0/7] MdeModulePkg ArmVirtPkg: fixes for 64-bit PCI DMA

[Ni, Ruiyu]

Ard,
The patch to MdeModulePkg/PciHostBridgeDxe is good.

Reviewed-by: Ruiyu Ni 

Thanks/Ray

> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
> Ard Biesheuvel
> Sent: Tuesday, September 6, 2016 3:48 PM
> To: edk2-devel-01 ; Tian, Feng
> ; Zeng, Star ; Gao, Liming
> 
> Cc: Laszlo Ersek ; Leif Lindholm
> ; Ard Biesheuvel 
> Subject: Re: [edk2] [PATCH 0/7] MdeModulePkg ArmVirtPkg: fixes for 64-bit
> PCI DMA
> 
> Feng, Star: do you have any feedback on these patches? Thanks.
> 
> On 5 September 2016 at 10:17, Ard Biesheuvel 
> wrote:
> > After moving ArmVirtQemu to the generic PciHostBridgeDxe, we noticed
> > that setting DmaAbove4G resulted in problems with the emulated EHCI
> > USB host controller, which were caused by the fact that the PCI layer
> > was providing DMA buffers allocated above 4 GB while the emulated EHCI
> > controller in QEMU does not indicate support for 64-bit addressing.
> >
> > As it turns out, the PCI drivers in MdeModulePkg *completely* ignore
> > the EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute, and simply
> assume
> > that no PCI root bridge driver will produce mappings above 4 GB. On
> > ARM, this is problematic, since not all platforms have memory below 4
> > GB, and so having full support for DMA above 4 GB is indispensable.
> >
> > So first, make the various drivers under MdeModulePkg/Pci/Bus set the
> > EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE attributes for devices that
> > can support 64-bit DMA addressing (patches #1 - #5). Then, we can
> > update the host bridge driver to actually take these attributes into
> > account, and only create mappings above 4 GB for devices that have
> indicated support for it.
> >
> > Finally, in patch #7 we can remove the 4 GB DMA limit from ArmVirtPkg.
> >
> > Branch can be found here:
> > https://git.linaro.org/people/ard.biesheuvel/uefi-next.git/shortlog/re
> > fs/heads/pci-64bit-dma-fixes
> >
> > Ard Biesheuvel (7):
> >   MdeModulePkg/AtaAtapiPassThru: enable 64-bit PCI DMA
> >   MdeModulePkg/EhciDxe: enable 64-bit PCI DMA
> >   MdeModulePkg/NvmExpressDxe: enable 64-bit PCI DMA
> >   MdeModulePkg/SdMmcPciHcDxe: enable 64-bit PCI DMA
> >   MdeModulePkg/XhciDxe: enable 64-bit PCI DMA
> >   MdeModulePkg/PciHostBridgeDxe: restrict 64-bit DMA to devices that
> > support it
> >   ArmVirtPkg/FdtPciHostBridgeLib: enable 64-bit PCI DMA
> >
> >  ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c |  2 +-
> >  MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c | 20
> +-
> >  MdeModulePkg/Bus/Pci/EhciDxe/Ehci.c  | 22
> +++-
> >  MdeModulePkg/Bus/Pci/EhciDxe/Ehci.h  |  2 ++
> >  MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c |  2 +-
> >  MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c   | 13
> 
> >  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c  | 14
> +
> >  MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c   | 20
> ++
> >  MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c  | 22
> +++-
> >  MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h  |  2 ++
> >  10 files changed, 110 insertions(+), 9 deletions(-)
> >
> > --
> > 2.7.4
> >
> ___
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> https://lists.01.org/mailman/listinfo/edk2-devel
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[edk2] [PATCH v2] NetworkPkg/DnsDxe: Handle CNAME type responded from the name server

[Jiaxin Wu]

v2:
* Code refine.
* For DnsCache, the minimum value of TTL is selected between CNAME and A/ 
record.

According RFC 1034 - 3.6.2, if the query name is an alias, the name server
will include the CNAME record in the response and restart the query at the
domain name specified in the data field of the CNAME record. RFC also provides
one example server action when A query received:

Suppose a name server was processing a query with for USCISIC.ARPA, asking for
type A information, and had the following resource records:
USC-ISIC.ARPA IN CNAME C.ISI.EDU
C.ISI.EDU IN A 10.0.0.52
Both of these RRs would be returned in the response to the type A query.

Currently, DnsDxe driver doesn't handle the CNAME type response, which will 
cause
any exception result. The driver need continue the packet parsing while CNAME 
type
record parsed. So, this patch is used to handle it correctly.

Cc: Hegde Nagaraj P 
Cc: Fu Siyuan 
Cc: Ye Ting 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiaxin Wu 
---
 NetworkPkg/DnsDxe/DnsImpl.c | 81 +
 1 file changed, 52 insertions(+), 29 deletions(-)

diff --git a/NetworkPkg/DnsDxe/DnsImpl.c b/NetworkPkg/DnsDxe/DnsImpl.c
index 360f68e..cfaa4c7 100644
--- a/NetworkPkg/DnsDxe/DnsImpl.c
+++ b/NetworkPkg/DnsDxe/DnsImpl.c
@@ -1125,10 +1125,11 @@ ParseDnsResponse (
   DNS6_TOKEN_ENTRY  *Dns6TokenEntry;
   
   UINT32IpCount;
   UINT32RRCount;
   UINT32AnswerSectionNum;
+  UINT32CNameTtl;
   
   EFI_IPv4_ADDRESS  *HostAddr4;
   EFI_IPv6_ADDRESS  *HostAddr6;
 
   EFI_DNS4_CACHE_ENTRY  *Dns4CacheEntry;
@@ -1146,10 +1147,11 @@ ParseDnsResponse (
   Dns6TokenEntry   = NULL;
   
   IpCount  = 0;
   RRCount  = 0;
   AnswerSectionNum = 0;
+  CNameTtl = 0;
   
   HostAddr4= NULL;
   HostAddr6= NULL;
   
   Dns4CacheEntry   = NULL;
@@ -1231,17 +1233,10 @@ ParseDnsResponse (
   if (DnsHeader->Flags.Bits.RCode != DNS_FLAGS_RCODE_NO_ERROR || 
DnsHeader->AnswersNum < 1 || \
   DnsHeader->Flags.Bits.QR != DNS_FLAGS_QR_RESPONSE) {
   Status = EFI_ABORTED;
   goto ON_EXIT;
   }
-
-  //
-  // Free the sending packet.
-  //
-  if (Item->Value != NULL) {
-NetbufFree ((NET_BUF *) (Item->Value));
-  }
   
   //
   // Do some buffer allocations.
   //
   if (Instance->Service->IpVersion == IP_VERSION_4) {
@@ -1288,40 +1283,42 @@ ParseDnsResponse (
   //
   // It's the GeneralLookUp querying.
   //
   Dns6TokenEntry->Token->RspData.GLookupData = AllocatePool (sizeof 
(DNS_RESOURCE_RECORD));
   if (Dns6TokenEntry->Token->RspData.GLookupData == NULL) {
-Status = EFI_UNSUPPORTED;
+Status = EFI_OUT_OF_RESOURCES;
 goto ON_EXIT;
   }
   Dns6TokenEntry->Token->RspData.GLookupData->RRList = AllocatePool 
(DnsHeader->AnswersNum * sizeof (DNS_RESOURCE_RECORD));
   if (Dns6TokenEntry->Token->RspData.GLookupData->RRList == NULL) {
-Status = EFI_UNSUPPORTED;
+Status = EFI_OUT_OF_RESOURCES;
 goto ON_EXIT;
   }
 } else {
   //
   // It's not the GeneralLookUp querying. Check the Query type.
   //
   if (QuerySection->Type == DNS_TYPE_) {
 Dns6TokenEntry->Token->RspData.H2AData = AllocatePool (sizeof 
(DNS6_HOST_TO_ADDR_DATA));
 if (Dns6TokenEntry->Token->RspData.H2AData == NULL) {
-  Status = EFI_UNSUPPORTED;
+  Status = EFI_OUT_OF_RESOURCES;
   goto ON_EXIT;
 }
 Dns6TokenEntry->Token->RspData.H2AData->IpList = AllocatePool 
(DnsHeader->AnswersNum * sizeof (EFI_IPv6_ADDRESS));
 if (Dns6TokenEntry->Token->RspData.H2AData->IpList == NULL) {
-  Status = EFI_UNSUPPORTED;
+  Status = EFI_OUT_OF_RESOURCES;
   goto ON_EXIT;
 }
   } else {
 Status = EFI_UNSUPPORTED;
 goto ON_EXIT;
   }
 }
   }
 
+  Status = EFI_NOT_FOUND;
+
   //
   // Processing AnswerSection.
   //
   while (AnswerSectionNum < DnsHeader->AnswersNum) {
 //
@@ -1348,51 +1345,53 @@ ParseDnsResponse (
   //
   // Fill the ResourceRecord.
   //
   Dns4RR[RRCount].QName = AllocateZeroPool (AsciiStrLen (QueryName) + 1);
   if (Dns4RR[RRCount].QName == NULL) {
-Status = EFI_UNSUPPORTED;
+Status = EFI_OUT_OF_RESOURCES;
 goto ON_EXIT;
   }
   CopyMem (Dns4RR[RRCount].QName, QueryName, AsciiStrLen (QueryName));
   Dns4RR[RRCount].QType = AnswerSection->Type;
   Dns4RR[RRCount].QClass = AnswerSection->Class;
   Dns4RR[RRCount].TTL = AnswerSection->Ttl;
   Dns4RR[RRCount].DataLength = AnswerSection->DataLength;
   Dns4RR[RRCount].RData = AllocateZeroPool (Dns4RR[RRCount].DataLength);
   if (Dns4RR[RRCount].RData == NULL) {
-Status = EFI_UNSUPPORTED;
+Status = 

[edk2] [PATCH] Vlv2TbltDevicePkg/PlatformInitPei: Support USB init

[Jiewen Yao]

In order to support recovery in PEI phase, a platform need initialize
USB controller. This logic is missing in current PchInitPeim.

We removed MultiPlatformInfoInit() because it is already done in
PlatformEarlyInitEntry().

We also initialize XhciMemBaseAddr to 0, or it is garbage value.

Cc: David Wei 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao 
Reviewed-by: David Wei 
---
 Vlv2TbltDevicePkg/PlatformInitPei/PchInitPeim.c | 26 ++---
 1 file changed, 19 insertions(+), 7 deletions(-)

diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/PchInitPeim.c 
b/Vlv2TbltDevicePkg/PlatformInitPei/PchInitPeim.c
index 18ecda4..286ccee 100644
--- a/Vlv2TbltDevicePkg/PlatformInitPei/PchInitPeim.c
+++ b/Vlv2TbltDevicePkg/PlatformInitPei/PchInitPeim.c
@@ -53,6 +53,11 @@ PchInitInterrupt (
   IN SYSTEM_CONFIGURATION  *SystemConfiguration
   );
 
+EFI_STATUS
+InstallPeiPchUsbPolicy (
+  IN CONST  EFI_PEI_SERVICES  **PeiServices
+  );
+
 #ifndef __GNUC__
 #pragma warning (push)
 #pragma warning (disable : 4245)
@@ -541,8 +546,18 @@ PlatformPchInit (
   IN UINT16  PlatformType
   )
 {
+  EFI_STATUS Status;
+  EFI_BOOT_MODE  BootMode;
+
+  Status = PeiServicesGetBootMode ();
+  ASSERT_EFI_ERROR (Status);
+
   IchRcrbInit (PeiServices, SystemConfiguration);
 
+  if (BootMode == BOOT_IN_RECOVERY_MODE) {
+InstallPeiPchUsbPolicy(PeiServices);
+  }
+
   //
   // PCH Policy Initialization based on Setup variable.
   //
@@ -721,7 +736,8 @@ InstallPeiPchUsbPolicy (
   EFI_PEI_PPI_DESCRIPTOR  *PeiPchUsbPolicyPpiDesc;
   PCH_USB_POLICY_PPI  *PeiPchUsbPolicyPpi;
   PCH_USB_CONFIG  *UsbConfig;
-  EFI_PLATFORM_INFO_HOB   PlatformInfo;
+
+  DEBUG ((EFI_D_INFO, "InstallPeiPchUsbPolicy...\n"));
 
   //
   // Allocate descriptor and PPI structures.  Since these are dynamically 
updated
@@ -745,12 +761,6 @@ InstallPeiPchUsbPolicy (
   UsbConfig->UsbPerPortCtl= PCH_DEVICE_DISABLE;
   UsbConfig->Ehci1Usbr= PCH_DEVICE_DISABLE;
 
-  //
-  // Initialize PlatformInfo HOB
-  //
-  ZeroMem (, sizeof(PlatformInfo));
-  MultiPlatformInfoInit(PeiServices, );
-
   UsbConfig->Usb20OverCurrentPins[0] = PchUsbOverCurrentPin0;
 
   UsbConfig->Usb20OverCurrentPins[1] = PchUsbOverCurrentPin0;
@@ -784,6 +794,8 @@ InstallPeiPchUsbPolicy (
 
   PeiPchUsbPolicyPpi->EhciMemLength   = (UINT32) 0x400 * PchEhciControllerMax;
 
+  PeiPchUsbPolicyPpi->XhciMemBaseAddr = 0;
+
   PeiPchUsbPolicyPpi->UsbConfig   = UsbConfig;
 
   PeiPchUsbPolicyPpiDesc->Flags   = EFI_PEI_PPI_DESCRIPTOR_PPI | 
EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
-- 
2.7.4.windows.1

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[edk2] [PATCH] Vlv2TbltDevicePkg/dec: Correct wrong default value.

[Jiewen Yao]

The default PcdPeiIchEhciControllerMemoryBaseAddress value 0xFD00
conflict with the default TXE SECUMA MMIO address.
So we update to 0xFC00 to avoid conflict.

Cc: David Wei 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao 
Reviewed-by: David Wei 
---
 Vlv2TbltDevicePkg/PlatformPkg.dec | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Vlv2TbltDevicePkg/PlatformPkg.dec 
b/Vlv2TbltDevicePkg/PlatformPkg.dec
index e81b534..731fd05 100644
--- a/Vlv2TbltDevicePkg/PlatformPkg.dec
+++ b/Vlv2TbltDevicePkg/PlatformPkg.dec
@@ -146,7 +146,7 @@
   gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0xB7, 0xD6, 0x7A, 
0xC5, 0x15, 0x05, 0xA8, 0x40, 0x9D, 0x21, 0x55, 0x16, 0x52, 0x85, 0x4E, 0x37 
}|VOID*|0x4004
 
   
gEfiIchTokenSpaceGuid.PcdPeiIchUhciControllerIoPortBaseAddress|0x4000|UINT16|0x3017
-  
gEfiIchTokenSpaceGuid.PcdPeiIchEhciControllerMemoryBaseAddress|0xFD00|UINT32|0x3019
+  
gEfiIchTokenSpaceGuid.PcdPeiIchEhciControllerMemoryBaseAddress|0xFC00|UINT32|0x3019
 
 
   gPlatformModuleTokenSpaceGuid.PcdRamLogBaseAddress|0x2|UINT32|0x0013
-- 
2.7.4.windows.1

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Re: [edk2] [PATCH 0/7] MdeModulePkg ArmVirtPkg: fixes for 64-bit PCI DMA

[Zeng, Star]

Also cc Ruiyu to see if any comments.

Thanks,
Star
-Original Message-
From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org] 
Sent: Tuesday, September 6, 2016 3:48 PM
To: edk2-devel-01 ; Tian, Feng ; 
Zeng, Star ; Gao, Liming 
Cc: Laszlo Ersek ; Leif Lindholm ; 
Ard Biesheuvel 
Subject: Re: [PATCH 0/7] MdeModulePkg ArmVirtPkg: fixes for 64-bit PCI DMA

Feng, Star: do you have any feedback on these patches? Thanks.

On 5 September 2016 at 10:17, Ard Biesheuvel  wrote:
> After moving ArmVirtQemu to the generic PciHostBridgeDxe, we noticed 
> that setting DmaAbove4G resulted in problems with the emulated EHCI 
> USB host controller, which were caused by the fact that the PCI layer 
> was providing DMA buffers allocated above 4 GB while the emulated EHCI 
> controller in QEMU does not indicate support for 64-bit addressing.
>
> As it turns out, the PCI drivers in MdeModulePkg *completely* ignore 
> the EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute, and simply assume 
> that no PCI root bridge driver will produce mappings above 4 GB. On 
> ARM, this is problematic, since not all platforms have memory below 4 
> GB, and so having full support for DMA above 4 GB is indispensable.
>
> So first, make the various drivers under MdeModulePkg/Pci/Bus set the 
> EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE attributes for devices that 
> can support 64-bit DMA addressing (patches #1 - #5). Then, we can 
> update the host bridge driver to actually take these attributes into 
> account, and only create mappings above 4 GB for devices that have indicated 
> support for it.
>
> Finally, in patch #7 we can remove the 4 GB DMA limit from ArmVirtPkg.
>
> Branch can be found here:
> https://git.linaro.org/people/ard.biesheuvel/uefi-next.git/shortlog/re
> fs/heads/pci-64bit-dma-fixes
>
> Ard Biesheuvel (7):
>   MdeModulePkg/AtaAtapiPassThru: enable 64-bit PCI DMA
>   MdeModulePkg/EhciDxe: enable 64-bit PCI DMA
>   MdeModulePkg/NvmExpressDxe: enable 64-bit PCI DMA
>   MdeModulePkg/SdMmcPciHcDxe: enable 64-bit PCI DMA
>   MdeModulePkg/XhciDxe: enable 64-bit PCI DMA
>   MdeModulePkg/PciHostBridgeDxe: restrict 64-bit DMA to devices that
> support it
>   ArmVirtPkg/FdtPciHostBridgeLib: enable 64-bit PCI DMA
>
>  ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c |  2 +-
>  MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c | 20 
> +-
>  MdeModulePkg/Bus/Pci/EhciDxe/Ehci.c  | 22 
> +++-
>  MdeModulePkg/Bus/Pci/EhciDxe/Ehci.h  |  2 ++
>  MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c |  2 +-
>  MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c   | 13 
> 
>  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c  | 14 
> +
>  MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c   | 20 
> ++
>  MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c  | 22 
> +++-
>  MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h  |  2 ++
>  10 files changed, 110 insertions(+), 9 deletions(-)
>
> --
> 2.7.4
>
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Re: [edk2] [Patch] NetworkPkg/DnsDxe: Handle CNAME type responded from the name server

[Wu, Jiaxin]

Yes, take the minimum value of TTL is meaningful.

From: Fu, Siyuan
Sent: Tuesday, September 6, 2016 3:13 PM
To: Wu, Jiaxin ; edk2-devel@lists.01.org
Cc: Hegde Nagaraj P ; Ye, Ting 
Subject: RE: [Patch] NetworkPkg/DnsDxe: Handle CNAME type responded from the 
name server

Jiaxin,

For #2, it's ok, I didn't notice the change in your patch.

For #1, I think we shouldn't mix the CNAME RR and A RR, they are 2 different 
answers and may have different TTL.

Best Regards
Siyuan

From: Wu, Jiaxin
Sent: Tuesday, September 6, 2016 3:05 PM
To: Fu, Siyuan >; 
edk2-devel@lists.01.org
Cc: Hegde Nagaraj P >; 
Ye, Ting >
Subject: RE: [Patch] NetworkPkg/DnsDxe: Handle CNAME type responded from the 
name server

Hi Siyuan,

> I have 2 comments for the patch.
> 1. I think we can add the CNAME record to the DNS cache, just like the A and
>  records, so the driver won't need to repeat the query if user query the
> host again.

In my opinion , the CNAME is unnecessary to cache to avoid the repeat the 
query. Because if DnsCache is enabled, HostName and the corresponding IpAddress 
will be retrieved directly from  EFI_DNS4_CACHE_ENTRY.

> 2. We should hold the original query packet until the response is parsed
> successfully, otherwise the system will crash again if a retransmit is needed.

This patch already did the update to avoid the crash issue during retransmit by 
removing the below code after the parsing is complete.

  //
  // Parsing is complete, free the sending packet and signal Event here.
  //
  if (Item != NULL && Item->Value != NULL) {
NetbufFree ((NET_BUF *) (Item->Value));
  }

So, the original query packet is safe until the response is parsed.

>
> Best Regards
> Siyuan
>
>

Thanks,
Jiaxin

> > -Original Message-
> > From: Wu, Jiaxin
> > Sent: Tuesday, September 6, 2016 11:39 AM
> > To: edk2-devel@lists.01.org
> > Cc: Hegde Nagaraj P 
> > >; Fu, Siyuan
> > >; Ye, Ting 
> > >
> > Subject: [Patch] NetworkPkg/DnsDxe: Handle CNAME type responded from
> > the name server
> >
> > According RFC 1034 - 3.6.2, if the query name is an alias, the name
> > server will include the CNAME record in the response and restart the
> > query at the domain name specified in the data field of the CNAME
> > record. RFC also provides one example server action when A query
> > received:
> >
> > Suppose a name server was processing a query with for USCISIC.ARPA,
> > asking for type A information, and had the following resource records:
> > USC-ISIC.ARPA IN CNAME C.ISI.EDU
> > C.ISI.EDU IN A 10.0.0.52
> > Both of these RRs would be returned in the response to the type A query.
> >
> > Currently, DnsDxe driver doesn't handle the CNAME type response, which
> > will cause any exception result. The driver need continue the packet
> > parsing while CNAME type record parsed. So, this patch is used to
> > handle it correctly.
> >
> > Cc: Hegde Nagaraj P 
> > >
> > Cc: Fu Siyuan >
> > Cc: Ye Ting >
> > Contributed-under: TianoCore Contribution Agreement 1.0
> > Signed-off-by: Jiaxin Wu >
> > ---
> >  NetworkPkg/DnsDxe/DnsImpl.c | 60
> > ++--
> > -
> >  1 file changed, 35 insertions(+), 25 deletions(-)
> >
> > diff --git a/NetworkPkg/DnsDxe/DnsImpl.c
> b/NetworkPkg/DnsDxe/DnsImpl.c
> > index 360f68e..c68ec88 100644
> > --- a/NetworkPkg/DnsDxe/DnsImpl.c
> > +++ b/NetworkPkg/DnsDxe/DnsImpl.c
> > @@ -1231,17 +1231,10 @@ ParseDnsResponse (
> >if (DnsHeader->Flags.Bits.RCode != DNS_FLAGS_RCODE_NO_ERROR ||
> > DnsHeader->AnswersNum < 1 || \
> >DnsHeader->Flags.Bits.QR != DNS_FLAGS_QR_RESPONSE) {
> >Status = EFI_ABORTED;
> >goto ON_EXIT;
> >}
> > -
> > -  //
> > -  // Free the sending packet.
> > -  //
> > -  if (Item->Value != NULL) {
> > -NetbufFree ((NET_BUF *) (Item->Value));
> > -  }
> >
> >//
> >// Do some buffer allocations.
> >//
> >if (Instance->Service->IpVersion == IP_VERSION_4) { @@ -1288,40
> > +1281,42 @@ ParseDnsResponse (
> >//
> >// It's the GeneralLookUp querying.
> >//
> >Dns6TokenEntry->Token->RspData.GLookupData = AllocatePool
> > (sizeof (DNS_RESOURCE_RECORD));
> >if (Dns6TokenEntry->Token->RspData.GLookupData == NULL) {
> > -Status = EFI_UNSUPPORTED;
> > +Status = EFI_OUT_OF_RESOURCES;
> >  goto ON_EXIT;
> >}
> >

Re: [edk2] [PATCH 0/7] MdeModulePkg ArmVirtPkg: fixes for 64-bit PCI DMA

[Ard Biesheuvel]

Feng, Star: do you have any feedback on these patches? Thanks.

On 5 September 2016 at 10:17, Ard Biesheuvel  wrote:
> After moving ArmVirtQemu to the generic PciHostBridgeDxe, we noticed that
> setting DmaAbove4G resulted in problems with the emulated EHCI USB host
> controller, which were caused by the fact that the PCI layer was providing
> DMA buffers allocated above 4 GB while the emulated EHCI controller in QEMU
> does not indicate support for 64-bit addressing.
>
> As it turns out, the PCI drivers in MdeModulePkg *completely* ignore the
> EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute, and simply assume that no
> PCI root bridge driver will produce mappings above 4 GB. On ARM, this is
> problematic, since not all platforms have memory below 4 GB, and so having
> full support for DMA above 4 GB is indispensable.
>
> So first, make the various drivers under MdeModulePkg/Pci/Bus set the
> EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE attributes for devices that can
> support 64-bit DMA addressing (patches #1 - #5). Then, we can update the
> host bridge driver to actually take these attributes into account, and only
> create mappings above 4 GB for devices that have indicated support for it.
>
> Finally, in patch #7 we can remove the 4 GB DMA limit from ArmVirtPkg.
>
> Branch can be found here:
> https://git.linaro.org/people/ard.biesheuvel/uefi-next.git/shortlog/refs/heads/pci-64bit-dma-fixes
>
> Ard Biesheuvel (7):
>   MdeModulePkg/AtaAtapiPassThru: enable 64-bit PCI DMA
>   MdeModulePkg/EhciDxe: enable 64-bit PCI DMA
>   MdeModulePkg/NvmExpressDxe: enable 64-bit PCI DMA
>   MdeModulePkg/SdMmcPciHcDxe: enable 64-bit PCI DMA
>   MdeModulePkg/XhciDxe: enable 64-bit PCI DMA
>   MdeModulePkg/PciHostBridgeDxe: restrict 64-bit DMA to devices that
> support it
>   ArmVirtPkg/FdtPciHostBridgeLib: enable 64-bit PCI DMA
>
>  ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c |  2 +-
>  MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c | 20 
> +-
>  MdeModulePkg/Bus/Pci/EhciDxe/Ehci.c  | 22 
> +++-
>  MdeModulePkg/Bus/Pci/EhciDxe/Ehci.h  |  2 ++
>  MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c |  2 +-
>  MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c   | 13 
> 
>  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c  | 14 
> +
>  MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c   | 20 
> ++
>  MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c  | 22 
> +++-
>  MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h  |  2 ++
>  10 files changed, 110 insertions(+), 9 deletions(-)
>
> --
> 2.7.4
>
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Re: [edk2] [Patch] NetworkPkg/DnsDxe: Handle CNAME type responded from the name server

[Fu, Siyuan]

Jiaxin,

For #2, it's ok, I didn't notice the change in your patch.

For #1, I think we shouldn't mix the CNAME RR and A RR, they are 2 different 
answers and may have different TTL.

Best Regards
Siyuan

From: Wu, Jiaxin
Sent: Tuesday, September 6, 2016 3:05 PM
To: Fu, Siyuan ; edk2-devel@lists.01.org
Cc: Hegde Nagaraj P ; Ye, Ting 
Subject: RE: [Patch] NetworkPkg/DnsDxe: Handle CNAME type responded from the 
name server

Hi Siyuan,

> I have 2 comments for the patch.
> 1. I think we can add the CNAME record to the DNS cache, just like the A and
>  records, so the driver won't need to repeat the query if user query the
> host again.

In my opinion , the CNAME is unnecessary to cache to avoid the repeat the 
query. Because if DnsCache is enabled, HostName and the corresponding IpAddress 
will be retrieved directly from  EFI_DNS4_CACHE_ENTRY.

> 2. We should hold the original query packet until the response is parsed
> successfully, otherwise the system will crash again if a retransmit is needed.

This patch already did the update to avoid the crash issue during retransmit by 
removing the below code after the parsing is complete.

  //
  // Parsing is complete, free the sending packet and signal Event here.
  //
  if (Item != NULL && Item->Value != NULL) {
NetbufFree ((NET_BUF *) (Item->Value));
  }

So, the original query packet is safe until the response is parsed.

>
> Best Regards
> Siyuan
>
>

Thanks,
Jiaxin

> > -Original Message-
> > From: Wu, Jiaxin
> > Sent: Tuesday, September 6, 2016 11:39 AM
> > To: edk2-devel@lists.01.org
> > Cc: Hegde Nagaraj P 
> > >; Fu, Siyuan
> > >; Ye, Ting 
> > >
> > Subject: [Patch] NetworkPkg/DnsDxe: Handle CNAME type responded from
> > the name server
> >
> > According RFC 1034 - 3.6.2, if the query name is an alias, the name
> > server will include the CNAME record in the response and restart the
> > query at the domain name specified in the data field of the CNAME
> > record. RFC also provides one example server action when A query
> > received:
> >
> > Suppose a name server was processing a query with for USCISIC.ARPA,
> > asking for type A information, and had the following resource records:
> > USC-ISIC.ARPA IN CNAME C.ISI.EDU
> > C.ISI.EDU IN A 10.0.0.52
> > Both of these RRs would be returned in the response to the type A query.
> >
> > Currently, DnsDxe driver doesn't handle the CNAME type response, which
> > will cause any exception result. The driver need continue the packet
> > parsing while CNAME type record parsed. So, this patch is used to
> > handle it correctly.
> >
> > Cc: Hegde Nagaraj P 
> > >
> > Cc: Fu Siyuan >
> > Cc: Ye Ting >
> > Contributed-under: TianoCore Contribution Agreement 1.0
> > Signed-off-by: Jiaxin Wu >
> > ---
> >  NetworkPkg/DnsDxe/DnsImpl.c | 60
> > ++--
> > -
> >  1 file changed, 35 insertions(+), 25 deletions(-)
> >
> > diff --git a/NetworkPkg/DnsDxe/DnsImpl.c
> b/NetworkPkg/DnsDxe/DnsImpl.c
> > index 360f68e..c68ec88 100644
> > --- a/NetworkPkg/DnsDxe/DnsImpl.c
> > +++ b/NetworkPkg/DnsDxe/DnsImpl.c
> > @@ -1231,17 +1231,10 @@ ParseDnsResponse (
> >if (DnsHeader->Flags.Bits.RCode != DNS_FLAGS_RCODE_NO_ERROR ||
> > DnsHeader->AnswersNum < 1 || \
> >DnsHeader->Flags.Bits.QR != DNS_FLAGS_QR_RESPONSE) {
> >Status = EFI_ABORTED;
> >goto ON_EXIT;
> >}
> > -
> > -  //
> > -  // Free the sending packet.
> > -  //
> > -  if (Item->Value != NULL) {
> > -NetbufFree ((NET_BUF *) (Item->Value));
> > -  }
> >
> >//
> >// Do some buffer allocations.
> >//
> >if (Instance->Service->IpVersion == IP_VERSION_4) { @@ -1288,40
> > +1281,42 @@ ParseDnsResponse (
> >//
> >// It's the GeneralLookUp querying.
> >//
> >Dns6TokenEntry->Token->RspData.GLookupData = AllocatePool
> > (sizeof (DNS_RESOURCE_RECORD));
> >if (Dns6TokenEntry->Token->RspData.GLookupData == NULL) {
> > -Status = EFI_UNSUPPORTED;
> > +Status = EFI_OUT_OF_RESOURCES;
> >  goto ON_EXIT;
> >}
> >Dns6TokenEntry->Token->RspData.GLookupData->RRList =
> > AllocatePool (DnsHeader->AnswersNum * sizeof
> (DNS_RESOURCE_RECORD));
> >if (Dns6TokenEntry->Token->RspData.GLookupData->RRList == NULL) {
> > -Status = EFI_UNSUPPORTED;
> > +Status = EFI_OUT_OF_RESOURCES;
> >  goto ON_EXIT;
> >}
> >  } else {
> >//
> >// It's not the GeneralLookUp querying. Check the Query type.
> >//
> >if 

Re: [edk2] [Patch] NetworkPkg/DnsDxe: Handle CNAME type responded from the name server

[Wu, Jiaxin]

Hi Siyuan,

> I have 2 comments for the patch.
> 1. I think we can add the CNAME record to the DNS cache, just like the A and
>  records, so the driver won't need to repeat the query if user query the
> host again.

In my opinion , the CNAME is unnecessary to cache to avoid the repeat the 
query. Because if DnsCache is enabled, HostName and the corresponding IpAddress 
will be retrieved directly from  EFI_DNS4_CACHE_ENTRY.

> 2. We should hold the original query packet until the response is parsed
> successfully, otherwise the system will crash again if a retransmit is needed.

This patch already did the update to avoid the crash issue during retransmit by 
removing the below code after the parsing is complete.

  //
  // Parsing is complete, free the sending packet and signal Event here.
  //
  if (Item != NULL && Item->Value != NULL) {
NetbufFree ((NET_BUF *) (Item->Value));
  }

So, the original query packet is safe until the response is parsed.

> 
> Best Regards
> Siyuan
> 
> 

Thanks,
Jiaxin

> > -Original Message-
> > From: Wu, Jiaxin
> > Sent: Tuesday, September 6, 2016 11:39 AM
> > To: edk2-devel@lists.01.org
> > Cc: Hegde Nagaraj P ; Fu, Siyuan
> > ; Ye, Ting 
> > Subject: [Patch] NetworkPkg/DnsDxe: Handle CNAME type responded from
> > the name server
> >
> > According RFC 1034 - 3.6.2, if the query name is an alias, the name
> > server will include the CNAME record in the response and restart the
> > query at the domain name specified in the data field of the CNAME
> > record. RFC also provides one example server action when A query
> > received:
> >
> > Suppose a name server was processing a query with for USCISIC.ARPA,
> > asking for type A information, and had the following resource records:
> > USC-ISIC.ARPA IN CNAME C.ISI.EDU
> > C.ISI.EDU IN A 10.0.0.52
> > Both of these RRs would be returned in the response to the type A query.
> >
> > Currently, DnsDxe driver doesn't handle the CNAME type response, which
> > will cause any exception result. The driver need continue the packet
> > parsing while CNAME type record parsed. So, this patch is used to
> > handle it correctly.
> >
> > Cc: Hegde Nagaraj P 
> > Cc: Fu Siyuan 
> > Cc: Ye Ting 
> > Contributed-under: TianoCore Contribution Agreement 1.0
> > Signed-off-by: Jiaxin Wu 
> > ---
> >  NetworkPkg/DnsDxe/DnsImpl.c | 60
> > ++--
> > -
> >  1 file changed, 35 insertions(+), 25 deletions(-)
> >
> > diff --git a/NetworkPkg/DnsDxe/DnsImpl.c
> b/NetworkPkg/DnsDxe/DnsImpl.c
> > index 360f68e..c68ec88 100644
> > --- a/NetworkPkg/DnsDxe/DnsImpl.c
> > +++ b/NetworkPkg/DnsDxe/DnsImpl.c
> > @@ -1231,17 +1231,10 @@ ParseDnsResponse (
> >if (DnsHeader->Flags.Bits.RCode != DNS_FLAGS_RCODE_NO_ERROR ||
> > DnsHeader->AnswersNum < 1 || \
> >DnsHeader->Flags.Bits.QR != DNS_FLAGS_QR_RESPONSE) {
> >Status = EFI_ABORTED;
> >goto ON_EXIT;
> >}
> > -
> > -  //
> > -  // Free the sending packet.
> > -  //
> > -  if (Item->Value != NULL) {
> > -NetbufFree ((NET_BUF *) (Item->Value));
> > -  }
> >
> >//
> >// Do some buffer allocations.
> >//
> >if (Instance->Service->IpVersion == IP_VERSION_4) { @@ -1288,40
> > +1281,42 @@ ParseDnsResponse (
> >//
> >// It's the GeneralLookUp querying.
> >//
> >Dns6TokenEntry->Token->RspData.GLookupData = AllocatePool
> > (sizeof (DNS_RESOURCE_RECORD));
> >if (Dns6TokenEntry->Token->RspData.GLookupData == NULL) {
> > -Status = EFI_UNSUPPORTED;
> > +Status = EFI_OUT_OF_RESOURCES;
> >  goto ON_EXIT;
> >}
> >Dns6TokenEntry->Token->RspData.GLookupData->RRList =
> > AllocatePool (DnsHeader->AnswersNum * sizeof
> (DNS_RESOURCE_RECORD));
> >if (Dns6TokenEntry->Token->RspData.GLookupData->RRList == NULL) {
> > -Status = EFI_UNSUPPORTED;
> > +Status = EFI_OUT_OF_RESOURCES;
> >  goto ON_EXIT;
> >}
> >  } else {
> >//
> >// It's not the GeneralLookUp querying. Check the Query type.
> >//
> >if (QuerySection->Type == DNS_TYPE_) {
> >  Dns6TokenEntry->Token->RspData.H2AData = AllocatePool (sizeof
> > (DNS6_HOST_TO_ADDR_DATA));
> >  if (Dns6TokenEntry->Token->RspData.H2AData == NULL) {
> > -  Status = EFI_UNSUPPORTED;
> > +  Status = EFI_OUT_OF_RESOURCES;
> >goto ON_EXIT;
> >  }
> >  Dns6TokenEntry->Token->RspData.H2AData->IpList = AllocatePool
> > (DnsHeader->AnswersNum * sizeof (EFI_IPv6_ADDRESS));
> >  if (Dns6TokenEntry->Token->RspData.H2AData->IpList == NULL) {
> > -  Status = EFI_UNSUPPORTED;
> > +  Status = EFI_OUT_OF_RESOURCES;
> >goto ON_EXIT;
> >  }
> >} else {
> >  Status = EFI_UNSUPPORTED;
> > 

Re: [edk2] [Patch] NetworkPkg/IpSecDxe: Generate SPI randomly and correct IKE_SPI_BASE value

[Ye, Ting]

Reviewed-by: Ye Ting  

-Original Message-
From: Wu, Jiaxin 
Sent: Tuesday, September 06, 2016 11:39 AM
To: edk2-devel@lists.01.org
Cc: Ye, Ting ; Fu, Siyuan 
Subject: [Patch] NetworkPkg/IpSecDxe: Generate SPI randomly and correct 
IKE_SPI_BASE value

This path made the following update:
* Generate SPI randomly.
* Correct IKE_SPI_BASE value according RFC 4302/4303.

Cc: Ye Ting 
Cc: Fu Siyuan 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiaxin Wu 
---
 NetworkPkg/IpSecDxe/IkeCommon.c | 102 +++-
 NetworkPkg/IpSecDxe/IkeCommon.h |  20 ---
 NetworkPkg/IpSecDxe/Ikev2/Utility.c |  11 +++-
 3 files changed, 112 insertions(+), 21 deletions(-)

diff --git a/NetworkPkg/IpSecDxe/IkeCommon.c b/NetworkPkg/IpSecDxe/IkeCommon.c 
index 6fc7c06..b1e4321 100644
--- a/NetworkPkg/IpSecDxe/IkeCommon.c
+++ b/NetworkPkg/IpSecDxe/IkeCommon.c
@@ -1,9 +1,9 @@
 /** @file
   Common operation of the IKE
   
-  Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.
+  Copyright (c) 2010 - 2016, Intel Corporation. All rights 
+ reserved.
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
   http://opensource.org/licenses/bsd-license.php.
@@ -16,14 +16,56 @@
 #include "Ike.h"
 #include "IkeCommon.h"
 #include "IpSecConfigImpl.h"
 #include "IpSecDebug.h"
 
-//
-// Initial the SPI
-//
-UINT32mNextSpi  = IKE_SPI_BASE;
+/**
+  Check whether the new generated Spi has existed.
+
+  @param[in]   IkeSaSession   Pointer to the Child SA Session.
+  @param[in]   SpiValue   SPI Value.
+
+  @retval  TRUEThis SpiValue has existed in the Child SA Session
+  @retval  FALSE   This SpiValue doesn't exist in the Child SA Session.
+  
+**/
+BOOLEAN
+IkeSpiValueExisted (
+  IN IKEV2_SA_SESSION  *IkeSaSession,
+  IN UINT32SpiValue
+  )
+{
+  LIST_ENTRY  *Entry;
+  LIST_ENTRY  *Next;
+  IKEV2_CHILD_SA_SESSION  *SaSession;
+
+  Entry = NULL;
+  Next  = NULL;
+  SaSession = NULL;
+
+  //
+  // Check whether the SPI value has existed in ChildSaEstablishSessionList.
+  //
+  NET_LIST_FOR_EACH_SAFE (Entry, Next, 
>ChildSaEstablishSessionList) {
+SaSession= IKEV2_CHILD_SA_SESSION_BY_IKE_SA (Entry);
+if (SaSession->LocalPeerSpi == SpiValue) {
+  return TRUE;
+}
+  }
+
+  //
+  // Check whether the SPI value has existed in ChildSaSessionList.
+  //
+  NET_LIST_FOR_EACH_SAFE (Entry, Next, >ChildSaSessionList) {
+SaSession= IKEV2_CHILD_SA_SESSION_BY_IKE_SA (Entry);
+if (SaSession->LocalPeerSpi == SpiValue) {
+  return TRUE;
+}
+  }
+
+  return FALSE;
+}
 
 /**
   Call Crypto Lib to generate a random value with eight-octet length.
   
   @return the 64 byte vaule.
@@ -156,23 +198,57 @@ IkePayloadFree (
   FreePool (IkePayload);
 }
 
 /**
   Generate an new SPI.
-
-  @return a SPI in 4 bytes.
+  
+  @param[in]  IkeSaSession   Pointer to IKEV2_SA_SESSION related to this 
Child SA 
+ Session.
+  @param[in out]  SpiValue   Pointer to the new generated SPI value. 
+  
+  @retval EFI_SUCCESS The operation performs successfully.
+  @retval Otherwise   The operation is failed.
 
 **/
-UINT32
+EFI_STATUS
 IkeGenerateSpi (
-  VOID
+  IN  IKEV2_SA_SESSION *IkeSaSession,
+  OUT UINT32   *SpiValue
   )
 {
-  //
-  // TODO: should generate SPI randomly to avoid security issue
-  //
-  return mNextSpi++;
+  EFI_STATUS   Status;
+
+  Status = EFI_SUCCESS;
+ 
+  while (TRUE) {
+//
+// Generate SPI randomly
+//
+Status = IpSecCryptoIoGenerateRandomBytes ((UINT8 *)SpiValue, sizeof 
(UINT32));
+if (EFI_ERROR (Status)) {
+  break;
+}
+
+//
+// The set of SPI values in the range 1 through 255 are reserved by the 
+// Internet Assigned Numbers Authority (IANA) for future use; a reserved 
+// SPI value will not normally be assigned by IANA unless the use of the 
+// assigned SPI value is specified in an RFC.
+//
+if (*SpiValue < IKE_SPI_BASE) {
+  *SpiValue += IKE_SPI_BASE; 
+}
+
+//
+// Check whether the new generated SPI has existed.
+//
+if (!IkeSpiValueExisted (IkeSaSession, *SpiValue)) {
+  break;
+}
+  }
+  
+  return Status;
 }
 
 /**
   Generate a random data for IV
 
diff --git a/NetworkPkg/IpSecDxe/IkeCommon.h b/NetworkPkg/IpSecDxe/IkeCommon.h 
index 714ecaa..7f7fd4d 100644
--- a/NetworkPkg/IpSecDxe/IkeCommon.h
+++ b/NetworkPkg/IpSecDxe/IkeCommon.h
@@ -1,9 +1,9 @@
 /** @file
   Common operation of the IKE.
 
-  Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.
+  Copyright (c) 2010 - 2016, 

[edk2] [PATCH] ShellPkg: pci -i -_e to print next capability

[Abdul Lateef Attar]

According to PCI spec the next AER capability is relative to
the beginning of PCI configuration space. Hence substract the
base offset to get the next capability.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Abdul Lateef Attar 
---
 ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c 
b/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c
index 337495e..664c22b 100644
--- a/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c
+++ b/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c
@@ -2370,7 +2370,7 @@ PCI_CONFIG_SPACE  *mConfigSpace = NULL;
 STATIC CONST SHELL_PARAM_ITEM ParamList[] = {
   {L"-s", TypeValue},
   {L"-i", TypeFlag},
-  {L"-_e", TypeFlag},
+  {L"-_e", TypeValue},
   {NULL, TypeMax}
   };
 
@@ -5914,7 +5914,7 @@ PciExplainPciExpress (
   // Advance to the next item if it exists
   //
   if (ExtHdr->NextCapabilityOffset != 0) {
-ExtHdr = (PCI_EXP_EXT_HDR*)((UINT8*)ExRegBuffer + 
ExtHdr->NextCapabilityOffset);
+ExtHdr = (PCI_EXP_EXT_HDR*)((UINT8*)ExRegBuffer + 
ExtHdr->NextCapabilityOffset - EFI_PCIE_CAPABILITY_BASE_OFFSET);
   } else {
 break;
   }
-- 
2.7.4

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