[edk2] [PATCH edk2-non-osi v3 0/7] Improve D0x platforms and bug fix

[Heyi Guo]

The major features of this patchset:
1 Upgrade trusted firmware to 1.4
2 Workarounds for CVE-2017-5715 on Cortex A57/A72/A73 and A75 #1214
3 Delete some binary for open-source version
4 Update binary follow changing DmaLib to CoherentDmaLib

Code can also be found in github: 
https://github.com/hisilicon/OpenPlatformPkg.git
branch: rp-1802-osi-v3


Heyi Guo (6):
  Hisilicon D0x: Fix network interface order issue
  Hisilicon D0x: Delete SnpPlatform
  Hisilicon D03/D05: Update SasDriverDxe binary
  Hisilicon D03/D05: Update NativeOhci binary
  Hisilicon/D03: Update binary of trusted-firmware
  Hisilicon/D05: Update binary of trusted-firmware

Jason Zhang (1):
  Hisilicon D03/D05: Delete SasPlatform

 Platform/Hisilicon/D03/Drivers/Net/SnpPV600Dxe/SnpPV600Dxe.efi | Bin 26688 -> 
27392 bytes
 Platform/Hisilicon/D03/Drivers/Net/SnpPlatform/SnpPlatform.efi | Bin 3040 -> 0 
bytes
 Platform/Hisilicon/D03/Drivers/Net/SnpPlatform/SnpPlatform.inf |  24 

 Platform/Hisilicon/D03/Drivers/OhciDxe/NativeOhci.efi  | Bin 21664 -> 
22336 bytes
 Platform/Hisilicon/D03/Drivers/Sas/SasDriverDxe.efi| Bin 98112 -> 
100224 bytes
 Platform/Hisilicon/D03/Drivers/SasPlatform/SasPlatform.efi | Bin 3040 -> 0 
bytes
 Platform/Hisilicon/D03/Drivers/SasPlatform/SasPlatform.inf |  24 

 Platform/Hisilicon/D03/bl1.bin | Bin 14336 -> 
12416 bytes
 Platform/Hisilicon/D03/fip.bin | Bin 62513 -> 
66758 bytes
 Platform/Hisilicon/D05/Drivers/Net/SnpPV600Dxe/SnpPV600Dxe.efi | Bin 28544 -> 
27680 bytes
 Platform/Hisilicon/D05/Drivers/Net/SnpPlatform/SnpPlatform.efi | Bin 3392 -> 0 
bytes
 Platform/Hisilicon/D05/Drivers/Net/SnpPlatform/SnpPlatform.inf |  24 

 Platform/Hisilicon/D05/Drivers/OhciDxe/NativeOhci.efi  | Bin 23328 -> 
22624 bytes
 Platform/Hisilicon/D05/Drivers/Sas/SasDriverDxe.efi| Bin 112832 -> 
115008 bytes
 Platform/Hisilicon/D05/Drivers/SasPlatform/SasPlatform.efi | Bin 3424 -> 0 
bytes
 Platform/Hisilicon/D05/Drivers/SasPlatform/SasPlatform.inf |  24 

 Platform/Hisilicon/D05/bl1.bin | Bin 14344 -> 
12424 bytes
 Platform/Hisilicon/D05/fip.bin | Bin 41493 -> 
37546 bytes
 18 files changed, 96 deletions(-)
 delete mode 100644 
Platform/Hisilicon/D03/Drivers/Net/SnpPlatform/SnpPlatform.efi
 delete mode 100644 
Platform/Hisilicon/D03/Drivers/Net/SnpPlatform/SnpPlatform.inf
 delete mode 100644 Platform/Hisilicon/D03/Drivers/SasPlatform/SasPlatform.efi
 delete mode 100644 Platform/Hisilicon/D03/Drivers/SasPlatform/SasPlatform.inf
 delete mode 100644 
Platform/Hisilicon/D05/Drivers/Net/SnpPlatform/SnpPlatform.efi
 delete mode 100644 
Platform/Hisilicon/D05/Drivers/Net/SnpPlatform/SnpPlatform.inf
 delete mode 100644 Platform/Hisilicon/D05/Drivers/SasPlatform/SasPlatform.efi
 delete mode 100644 Platform/Hisilicon/D05/Drivers/SasPlatform/SasPlatform.inf

-- 
1.9.1

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[edk2] [PATCH edk2-non-osi v3 2/7] Hisilicon D0x: Fix network interface order issue

[Heyi Guo]

1. Rebuild SnpPV600Dxe binary for switching DmaLib to CoherentDmaLib.
2. Fixed bug:Confusing Ethernet port sequence.
Move the most right Ethernet port (when looking from the front of the
chassis) to the first one in BootManage for PXE boot.
https://bugs.linaro.org/show_bug.cgi?id=2657

Note:
This patch is related to "Open SnpPlatform source code" and
"Change DmaLib to CoherentDmaLib" in edk2-platform.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jason Zhang 
Signed-off-by: Ming Huang 
Signed-off-by: Heyi Guo 
Reviewed-by: Ard Biesheuvel 
Reviewed-by: Leif Lindholm 
---
 Platform/Hisilicon/D03/Drivers/Net/SnpPV600Dxe/SnpPV600Dxe.efi | Bin 26688 -> 
27392 bytes
 Platform/Hisilicon/D05/Drivers/Net/SnpPV600Dxe/SnpPV600Dxe.efi | Bin 28544 -> 
27680 bytes
 2 files changed, 0 insertions(+), 0 deletions(-)

diff --git a/Platform/Hisilicon/D03/Drivers/Net/SnpPV600Dxe/SnpPV600Dxe.efi 
b/Platform/Hisilicon/D03/Drivers/Net/SnpPV600Dxe/SnpPV600Dxe.efi
index 8ce6a6d..bcb3e4f 100644
Binary files a/Platform/Hisilicon/D03/Drivers/Net/SnpPV600Dxe/SnpPV600Dxe.efi 
and b/Platform/Hisilicon/D03/Drivers/Net/SnpPV600Dxe/SnpPV600Dxe.efi differ
diff --git a/Platform/Hisilicon/D05/Drivers/Net/SnpPV600Dxe/SnpPV600Dxe.efi 
b/Platform/Hisilicon/D05/Drivers/Net/SnpPV600Dxe/SnpPV600Dxe.efi
index bc7942a..582f645 100644
Binary files a/Platform/Hisilicon/D05/Drivers/Net/SnpPV600Dxe/SnpPV600Dxe.efi 
and b/Platform/Hisilicon/D05/Drivers/Net/SnpPV600Dxe/SnpPV600Dxe.efi differ
-- 
1.9.1

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[edk2] [PATCH edk2-non-osi v3 1/7] Hisilicon D03/D05: Delete SasPlatform

[Heyi Guo]

From: Jason Zhang 

An open-source version coming to edk2-platfroms replaces this version.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jason Zhang 
Signed-off-by: Ming Huang 
Signed-off-by: Heyi Guo 
Reviewed-by: Ard Biesheuvel 
Reviewed-by: Leif Lindholm 
---
 Platform/Hisilicon/D03/Drivers/SasPlatform/SasPlatform.efi | Bin 3040 -> 0 
bytes
 Platform/Hisilicon/D03/Drivers/SasPlatform/SasPlatform.inf |  24 

 Platform/Hisilicon/D05/Drivers/SasPlatform/SasPlatform.efi | Bin 3424 -> 0 
bytes
 Platform/Hisilicon/D05/Drivers/SasPlatform/SasPlatform.inf |  24 

 4 files changed, 48 deletions(-)

diff --git a/Platform/Hisilicon/D03/Drivers/SasPlatform/SasPlatform.efi 
b/Platform/Hisilicon/D03/Drivers/SasPlatform/SasPlatform.efi
deleted file mode 100644
index 4255641..000
Binary files a/Platform/Hisilicon/D03/Drivers/SasPlatform/SasPlatform.efi and 
/dev/null differ
diff --git a/Platform/Hisilicon/D03/Drivers/SasPlatform/SasPlatform.inf 
b/Platform/Hisilicon/D03/Drivers/SasPlatform/SasPlatform.inf
deleted file mode 100644
index 0d747a1..000
--- a/Platform/Hisilicon/D03/Drivers/SasPlatform/SasPlatform.inf
+++ /dev/null
@@ -1,24 +0,0 @@
-#/** @file
-#
-#Copyright (c) 2017, Hisilicon Limited. All rights reserved.
-#Copyright (c) 2017, Linaro Limited. All rights reserved.
-#
-#This program and the accompanying materials
-#are licensed and made available under the terms and conditions of the BSD 
License
-#which accompanies this distribution. The full text of the license may be 
found at
-#http://opensource.org/licenses/bsd-license.php
-#
-#THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
-#
-#**/
-
-[Defines]
-  INF_VERSION= 0x00010019
-  BASE_NAME  = SasPlatform
-  FILE_GUID  = 102D8FC9-20a4-42EB-aC14-1C98BA5b26A4
-  MODULE_TYPE= DXE_DRIVER
-  VERSION_STRING = 1.0
-
-[Binaries.AARCH64]
-  PE32|SasPlatform.efi|*
diff --git a/Platform/Hisilicon/D05/Drivers/SasPlatform/SasPlatform.efi 
b/Platform/Hisilicon/D05/Drivers/SasPlatform/SasPlatform.efi
deleted file mode 100644
index d2685ab..000
Binary files a/Platform/Hisilicon/D05/Drivers/SasPlatform/SasPlatform.efi and 
/dev/null differ
diff --git a/Platform/Hisilicon/D05/Drivers/SasPlatform/SasPlatform.inf 
b/Platform/Hisilicon/D05/Drivers/SasPlatform/SasPlatform.inf
deleted file mode 100644
index 0d747a1..000
--- a/Platform/Hisilicon/D05/Drivers/SasPlatform/SasPlatform.inf
+++ /dev/null
@@ -1,24 +0,0 @@
-#/** @file
-#
-#Copyright (c) 2017, Hisilicon Limited. All rights reserved.
-#Copyright (c) 2017, Linaro Limited. All rights reserved.
-#
-#This program and the accompanying materials
-#are licensed and made available under the terms and conditions of the BSD 
License
-#which accompanies this distribution. The full text of the license may be 
found at
-#http://opensource.org/licenses/bsd-license.php
-#
-#THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
-#
-#**/
-
-[Defines]
-  INF_VERSION= 0x00010019
-  BASE_NAME  = SasPlatform
-  FILE_GUID  = 102D8FC9-20a4-42EB-aC14-1C98BA5b26A4
-  MODULE_TYPE= DXE_DRIVER
-  VERSION_STRING = 1.0
-
-[Binaries.AARCH64]
-  PE32|SasPlatform.efi|*
-- 
1.9.1

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[edk2] [PATCH edk2-non-osi v3 3/7] Hisilicon D0x: Delete SnpPlatform

[Heyi Guo]

An open-source version coming to edk2-platforms replaces this version.
This patch is related to "Open SnpPlatform source code" and
"Change DmaLib to CoherentDmaLib".

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang 
Signed-off-by: Heyi Guo 
Signed-off-by: Jason Zhang 
Reviewed-by: Ard Biesheuvel 
Reviewed-by: Leif Lindholm 
---
 Platform/Hisilicon/D03/Drivers/Net/SnpPlatform/SnpPlatform.efi | Bin 3040 -> 0 
bytes
 Platform/Hisilicon/D03/Drivers/Net/SnpPlatform/SnpPlatform.inf |  24 

 Platform/Hisilicon/D05/Drivers/Net/SnpPlatform/SnpPlatform.efi | Bin 3392 -> 0 
bytes
 Platform/Hisilicon/D05/Drivers/Net/SnpPlatform/SnpPlatform.inf |  24 

 4 files changed, 48 deletions(-)

diff --git a/Platform/Hisilicon/D03/Drivers/Net/SnpPlatform/SnpPlatform.efi 
b/Platform/Hisilicon/D03/Drivers/Net/SnpPlatform/SnpPlatform.efi
deleted file mode 100644
index 5e7d8bd..000
Binary files a/Platform/Hisilicon/D03/Drivers/Net/SnpPlatform/SnpPlatform.efi 
and /dev/null differ
diff --git a/Platform/Hisilicon/D03/Drivers/Net/SnpPlatform/SnpPlatform.inf 
b/Platform/Hisilicon/D03/Drivers/Net/SnpPlatform/SnpPlatform.inf
deleted file mode 100644
index 10b2003..000
--- a/Platform/Hisilicon/D03/Drivers/Net/SnpPlatform/SnpPlatform.inf
+++ /dev/null
@@ -1,24 +0,0 @@
-#/** @file
-#
-#Copyright (c) 2017, Hisilicon Limited. All rights reserved.
-#Copyright (c) 2017, Linaro Limited. All rights reserved.
-#
-#This program and the accompanying materials
-#are licensed and made available under the terms and conditions of the BSD 
License
-#which accompanies this distribution. The full text of the license may be 
found at
-#http://opensource.org/licenses/bsd-license.php
-#
-#THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
-#
-#**/
-
-[Defines]
-  INF_VERSION= 0x00010019
-  BASE_NAME  = SnpPlatform
-  FILE_GUID  = 102D8FC9-20A4-42EB-AC14-1C98BA5B17A8
-  MODULE_TYPE= DXE_DRIVER
-  VERSION_STRING = 1.0
-
-[Binaries.AARCH64]
-  PE32|SnpPlatform.efi|*
diff --git a/Platform/Hisilicon/D05/Drivers/Net/SnpPlatform/SnpPlatform.efi 
b/Platform/Hisilicon/D05/Drivers/Net/SnpPlatform/SnpPlatform.efi
deleted file mode 100644
index 42c26de..000
Binary files a/Platform/Hisilicon/D05/Drivers/Net/SnpPlatform/SnpPlatform.efi 
and /dev/null differ
diff --git a/Platform/Hisilicon/D05/Drivers/Net/SnpPlatform/SnpPlatform.inf 
b/Platform/Hisilicon/D05/Drivers/Net/SnpPlatform/SnpPlatform.inf
deleted file mode 100644
index 10b2003..000
--- a/Platform/Hisilicon/D05/Drivers/Net/SnpPlatform/SnpPlatform.inf
+++ /dev/null
@@ -1,24 +0,0 @@
-#/** @file
-#
-#Copyright (c) 2017, Hisilicon Limited. All rights reserved.
-#Copyright (c) 2017, Linaro Limited. All rights reserved.
-#
-#This program and the accompanying materials
-#are licensed and made available under the terms and conditions of the BSD 
License
-#which accompanies this distribution. The full text of the license may be 
found at
-#http://opensource.org/licenses/bsd-license.php
-#
-#THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
-#
-#**/
-
-[Defines]
-  INF_VERSION= 0x00010019
-  BASE_NAME  = SnpPlatform
-  FILE_GUID  = 102D8FC9-20A4-42EB-AC14-1C98BA5B17A8
-  MODULE_TYPE= DXE_DRIVER
-  VERSION_STRING = 1.0
-
-[Binaries.AARCH64]
-  PE32|SnpPlatform.efi|*
-- 
1.9.1

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[edk2] [PATCH edk2-non-osi v3 4/7] Hisilicon D03/D05: Update SasDriverDxe binary

[Heyi Guo]

Update SasDriverDxe binary for changing DmaLib to CoherentDmaLib.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang 
Signed-off-by: Heyi Guo 
Reviewed-by: Leif Lindholm 
---
 Platform/Hisilicon/D03/Drivers/Sas/SasDriverDxe.efi | Bin 98112 -> 100224 bytes
 Platform/Hisilicon/D05/Drivers/Sas/SasDriverDxe.efi | Bin 112832 -> 115008 
bytes
 2 files changed, 0 insertions(+), 0 deletions(-)

diff --git a/Platform/Hisilicon/D03/Drivers/Sas/SasDriverDxe.efi 
b/Platform/Hisilicon/D03/Drivers/Sas/SasDriverDxe.efi
index c37b922..6b61504 100644
Binary files a/Platform/Hisilicon/D03/Drivers/Sas/SasDriverDxe.efi and 
b/Platform/Hisilicon/D03/Drivers/Sas/SasDriverDxe.efi differ
diff --git a/Platform/Hisilicon/D05/Drivers/Sas/SasDriverDxe.efi 
b/Platform/Hisilicon/D05/Drivers/Sas/SasDriverDxe.efi
index a57b8e1..b74c23b 100644
Binary files a/Platform/Hisilicon/D05/Drivers/Sas/SasDriverDxe.efi and 
b/Platform/Hisilicon/D05/Drivers/Sas/SasDriverDxe.efi differ
-- 
1.9.1

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Re: [edk2] [PATCH] BaseTools: Update Expression.py for VOID* support L'a' and 'a'

[Feng, YunhuaX]

Yes, you are right.

L"String" and "String" still support,  and we add L'String' and 'String'
L"ab"  ==> {0x61, 0x00, 0x62, 0x00, 0x00, 0x00}
L'ab'   ==> {0x61, 0x00, 0x62, 0x00} 

Any question, please let me know. Thanks.

Best Regards
Feng, Yunhua

-Original Message-
From: Yao, Jiewen 
Sent: Friday, February 2, 2018 8:17 PM
To: Feng, YunhuaX ; edk2-devel@lists.01.org
Cc: Gao, Liming ; Yao, Jiewen 
Subject: RE: [PATCH] BaseTools: Update Expression.py for VOID* support L'a' and 
'a'

Hello
May I know why we do not support L"String" ?

My understanding is that L'String' is a string without NULL terminator, 
L"String" is a string with NULL terminator, right?

Thank you
Yao Jiewen

> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of 
> Feng, YunhuaX
> Sent: Friday, February 2, 2018 5:02 PM
> To: edk2-devel@lists.01.org
> Cc: Gao, Liming 
> Subject: [edk2] [PATCH] BaseTools: Update Expression.py for VOID* support L'a'
> and 'a'
> 
> Type VOID* support L'a' and 'a', the value transfer to c style value.
> L'a' --> {0x61, 0x00}
> L'ab' --> {0x61, 0x00, 0x62, 0x00}
> 'a'  --> {0x61}
> 'ab' --> {0x61, 0x62}
> 
> when the value is L'' or '', will report error
> 
> Cc: Liming Gao 
> Cc: Yonghong Zhu 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Yunhua Feng 
> ---
>  BaseTools/Source/Python/Common/Expression.py | 19 ---
>  BaseTools/Source/Python/Common/Misc.py   |  4 
>  2 files changed, 20 insertions(+), 3 deletions(-)
> 
> diff --git a/BaseTools/Source/Python/Common/Expression.py
> b/BaseTools/Source/Python/Common/Expression.py
> index b8c48460ff..6a1103df2c 100644
> --- a/BaseTools/Source/Python/Common/Expression.py
> +++ b/BaseTools/Source/Python/Common/Expression.py
> @@ -740,7 +740,12 @@ class ValueExpressionEx(ValueExpression):
>  try:
>  PcdValue = ValueExpression.__call__(self, RealValue, Depth)
>  if self.PcdType == 'VOID*' and (PcdValue.startswith("'") 
> or
> PcdValue.startswith("L'")):
> -raise BadExpression
> +PcdValue, Size = ParseFieldValue(PcdValue)
> +PcdValueList = []
> +for I in range(Size):
> +PcdValueList.append('0x%02X'%(PcdValue & 0xff))
> +PcdValue = PcdValue >> 8
> +PcdValue = '{' + ','.join(PcdValueList) + '}'
>  elif self.PcdType in ['UINT8', 'UINT16', 'UINT32', 
> 'UINT64', 'BOOLEAN'] and (PcdValue.startswith("'") or \
>PcdValue.startswith('"') or 
> PcdValue.startswith("L'") or PcdValue.startswith('L"') or 
> PcdValue.startswith('{')):
>  raise BadExpression
> @@ -755,6 +760,8 @@ class ValueExpressionEx(ValueExpression):
>  TmpValue = 0
>  Size = 0
>  for Item in PcdValue:
> +if Item.startswith('UINT8'):
> +ItemSize = 1
>  if Item.startswith('UINT16'):
>  ItemSize = 2
>  elif Item.startswith('UINT32'):
> @@ -776,7 +783,10 @@ class ValueExpressionEx(ValueExpression):
>  TmpValue = (ItemValue << (Size * 8)) | TmpValue
>  Size = Size + ItemSize
>  else:
> -TmpValue, Size = ParseFieldValue(PcdValue)
> +try:
> +TmpValue, Size = ParseFieldValue(PcdValue)
> +except BadExpression:
> +raise BadExpression("Type: %s, Value: %s, 
> + format
> or value error" % (self.PcdType, PcdValue))
>  if type(TmpValue) == type(''):
>  TmpValue = int(TmpValue)
>  else:
> @@ -858,7 +868,7 @@ class ValueExpressionEx(ValueExpression):
>  else:
>  raise BadExpression('%s not 
> defined before use' % Offset)
>  ValueType = ""
> -if Item.startswith('UINT16'):
> +if Item.startswith('UINT8'):
>  ItemSize = 1
>  ValueType = "UINT8"
>  elif Item.startswith('UINT16'):
> @@ -887,6 +897,9 @@ class ValueExpressionEx(ValueExpression):
> 
>  if Size > 0:
>  PcdValue = '{' + ValueStr[:-2] + '}'
> +else:
> +raise  BadExpression("Type: %s, Value: %s, 
> + format
> or value error"%(self.PcdType, PcdValue))
> +
>  if PcdValue == 'True':
>  PcdValue = '1'
>  if 

Re: [edk2] [PATCH 1/3] UefiCpuPkg/PiSmmCpuDxeSmm: update comments in IA32 SmmStartup()

[Laszlo Ersek]

On 02/02/18 11:06, Ard Biesheuvel wrote:
> On 31 January 2018 at 10:40, Laszlo Ersek  wrote:
>> On 01/30/18 23:25, Kinney, Michael D wrote:
>>> Laszlo,
>>>
>>> I agree that the function is better than a macro.
>>>
>>> I thought of the alignment issues as well.  CopyMem()
>>> is a good solution.  We could also consider
>>> WriteUnalignedxx() functions in BaseLib.
>>
>> IMO, the WriteUnalignedxx functions are a bit pointless in the exact
>> form they are declared (this was discussed earlier esp. with regard to
>> aarch64). The functions take pointers to objects that already have the
>> target type, such as
>>
>> UINT32
>> EFIAPI
>> WriteUnaligned32 (
>>   OUT UINT32*Buffer,
>>   IN  UINT32Value
>>   )
>>
>> Here the type of Buffer should be (VOID *), not (UINT32 *). Otherwise,
>> the undefined behavior (due to mis-alignment) surfaces as soon as the
>> function is called with an unaligned pointer (i.e. before the target
>> area is actually written).
>>
>>> I was originally thinking this functionality would go
>>> into BaseLib.  But with the use of CopyMem(), we can't
>>> do that.
>>
>> Can we put it in BaseMemoryLib instead (which is where CopyMem() is
>> from)? That library class is still low-level enough. And, while I count
>> 9 library instances, PatchAssembly() is not a large function, we could
>> tolerate adding it to all 9 instances, identically.
>>
>> Let me also ask the opposite question: should we perhaps make the
>> PatchAssembly() API *less* abstract? (Also suggested by your naming of
>> the macro, PATCH_X86_ASM.) If the instruction encoding on e.g. AARCH64
>> doesn't lend itself to such patching (= expressed through the address
>> right after the instruction), then even BaseMemoryLib may be too generic
>> for the API.
>>
>>> Maybe we should use WriteUnalignedxx() and
>>> add some ASSERT() checks.
>>>
>>> VOID
>>> PatchAssembly (
>>>   VOID*BufferEnd,
>>>   UINT64  PatchValue,
>>>   UINTN   ValueSize
>>>   )
>>> {
>>>   ASSERT ((UINTN)BufferEnd > ValueSize);
>>>   switch (ValueSize) {
>>>   case 1:
>>> ASSERT (PatchValue <= MAX_UINT8);
>>> *((UINT8 *)BufferEnd - 1) = (UINT8)PatchValue;
>>>   case 2:
>>> ASSERT (PatchValue <= MAX_UINT16);
>>> WriteUnaligned16 ((UINT16 *)(BufferEnd) - 1, (UINT16)PatchValue));
>>> break;
>>>   case 4:
>>> ASSERT (PatchValue <= MAX_UINT32);
>>> WriteUnaligned32 ((UINT32 *)(BufferEnd) - 1, (UINT32)PatchValue));
>>> break;
>>>   case 8:
>>> WriteUnaligned64 ((UINT64 *)(BufferEnd) - 1, PatchValue));
>>> break;
>>>   default:
>>> ASSERT (FALSE);
>>>   }
>>> }
>>
>> In my opinion:
>>
>> - If Ard and Leif say that PatchAssembly() API makes sense for AARCH64,
>>   then I think we can go with the above generic implementation (for
>>   BaseLib).
>>
> 
> Code patching on ARM/AARCH64 has some hoops to jump through, i.e.,
> clean the D-cache to the point of unification, invalidate the I-cache,
> probably some barriers in case the patching function happened to end
> up in the same cache line as the patchee (which may not be a concern
> for this specific use case, but it does need to be taken into account
> if this is turned into a patch-any-assembly-anywhere function)
> 
> So if the PatchAssembly() prototype does end up in a generic library
> class, we'd have to provide ARM and AARCH64 specific implementations
> anyway, and given that I don't see any use for this on ARM/AARCH64 in
> the first place, I think this should belong in an IA32/X64 specific
> package.

Thank you for the response!

For now I'm going to post the series with the function introduced as
PatchInstructionX86() to BaseLib, visibly only to IA32 and X64 edk2
platforms. If a better place than BaseLib looks necessary, I can move it
according to review comments.

Thanks!
Laszlo

> 
>> - If Ard and Leif say the API is only useful on x86, then I suggest that
>>   we implement the API separately for all arches (still in BaseLib):
>>
>>   - On x86, we should simply open-code the unaligned accesses (like you
>> originall suggested). The pointer arithmetic will look a bit wild,
>> but it's safely hidden behind a BaseLib API, so client code will
>> look nice.
>>
>>   - On all other arches, we should implement the function with
>> ASSERT(FALSE).
>>
>> Thanks!
>> Laszlo
>>
>>>
>>> Mike
>>>
 -Original Message-
 From: Laszlo Ersek [mailto:ler...@redhat.com]
 Sent: Tuesday, January 30, 2018 1:45 PM
 To: Kinney, Michael D ; edk2-
 devel-01 
 Cc: Ni, Ruiyu ; Paolo Bonzini
 ; Yao, Jiewen
 ; Dong, Eric 
 Subject: Re: [edk2] [PATCH 1/3]
 UefiCpuPkg/PiSmmCpuDxeSmm: update comments in IA32
 SmmStartup()

 On 01/30/18 21:31, Kinney, Michael D wrote:
> Laszlo,
>
> We have already used this technique in other NASM 

Re: [edk2] [PATCH 1/3] UefiCpuPkg/PiSmmCpuDxeSmm: update comments in IA32 SmmStartup()

[Laszlo Ersek]

On 02/02/18 14:28, Leif Lindholm wrote:
> On Fri, Feb 02, 2018 at 10:06:07AM +, Ard Biesheuvel wrote:
>> On 31 January 2018 at 10:40, Laszlo Ersek  wrote:
>>> On 01/30/18 23:25, Kinney, Michael D wrote:
 Laszlo,

 I agree that the function is better than a macro.

 I thought of the alignment issues as well.  CopyMem()
 is a good solution.  We could also consider
 WriteUnalignedxx() functions in BaseLib.
>>>
>>> IMO, the WriteUnalignedxx functions are a bit pointless in the exact
>>> form they are declared (this was discussed earlier esp. with regard to
>>> aarch64). The functions take pointers to objects that already have the
>>> target type, such as
>>>
>>> UINT32
>>> EFIAPI
>>> WriteUnaligned32 (
>>>   OUT UINT32*Buffer,
>>>   IN  UINT32Value
>>>   )
>>>
>>> Here the type of Buffer should be (VOID *), not (UINT32 *). Otherwise,
>>> the undefined behavior (due to mis-alignment) surfaces as soon as the
>>> function is called with an unaligned pointer (i.e. before the target
>>> area is actually written).
>>>
 I was originally thinking this functionality would go
 into BaseLib.  But with the use of CopyMem(), we can't
 do that.
>>>
>>> Can we put it in BaseMemoryLib instead (which is where CopyMem() is
>>> from)? That library class is still low-level enough. And, while I count
>>> 9 library instances, PatchAssembly() is not a large function, we could
>>> tolerate adding it to all 9 instances, identically.
>>>
>>> Let me also ask the opposite question: should we perhaps make the
>>> PatchAssembly() API *less* abstract? (Also suggested by your naming of
>>> the macro, PATCH_X86_ASM.) If the instruction encoding on e.g. AARCH64
>>> doesn't lend itself to such patching (= expressed through the address
>>> right after the instruction), then even BaseMemoryLib may be too generic
>>> for the API.
>>>
 Maybe we should use WriteUnalignedxx() and
 add some ASSERT() checks.

 VOID
 PatchAssembly (
   VOID*BufferEnd,
   UINT64  PatchValue,
   UINTN   ValueSize
   )
 {
   ASSERT ((UINTN)BufferEnd > ValueSize);
   switch (ValueSize) {
   case 1:
 ASSERT (PatchValue <= MAX_UINT8);
 *((UINT8 *)BufferEnd - 1) = (UINT8)PatchValue;
   case 2:
 ASSERT (PatchValue <= MAX_UINT16);
 WriteUnaligned16 ((UINT16 *)(BufferEnd) - 1, (UINT16)PatchValue));
 break;
   case 4:
 ASSERT (PatchValue <= MAX_UINT32);
 WriteUnaligned32 ((UINT32 *)(BufferEnd) - 1, (UINT32)PatchValue));
 break;
   case 8:
 WriteUnaligned64 ((UINT64 *)(BufferEnd) - 1, PatchValue));
 break;
   default:
 ASSERT (FALSE);
   }
 }
>>>
>>> In my opinion:
>>>
>>> - If Ard and Leif say that PatchAssembly() API makes sense for AARCH64,
>>>   then I think we can go with the above generic implementation (for
>>>   BaseLib).
>>>
>>
>> Code patching on ARM/AARCH64 has some hoops to jump through, i.e.,
>> clean the D-cache to the point of unification, invalidate the I-cache,
>> probably some barriers in case the patching function happened to end
>> up in the same cache line as the patchee
> 
> Not just the same cache line. Prefetching can happen whenever, for
> whatever reason.
> 
>> (which may not be a concern
>> for this specific use case, but it does need to be taken into account
>> if this is turned into a patch-any-assembly-anywhere function)
>>
>> So if the PatchAssembly() prototype does end up in a generic library
>> class, we'd have to provide ARM and AARCH64 specific implementations
>> anyway, and given that I don't see any use for this on ARM/AARCH64 in
>> the first place, I think this should belong in an IA32/X64 specific
>> package.
> 
> I also don't see a specific use for this on ARM* at the moment. But if
> this is going to become more widespread, it would be useful to
> introduce a higher-level layer with more portable semantics (I don't
> know RISC-V, but could imagine they require similar).
> However, at that point, we would probably want something
> buffer-oriented rather than instruction-oriented, since we'd like to
> keep the overhead down if writing more than one register's worth.

I'll CC you and Ard on the BaseLib patches; hopefully
PatchInstructionX86() will be possible to reimplement in terms of the
more generic, buffer-oriented API, once we introduce that.

Thanks!
Laszlo
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Re: [edk2] [PATCH] BaseTools: Update Expression.py for VOID* support L'a' and 'a'

[Yao, Jiewen]

Good.

I am just confused on the commit message --- when the value is L'' or '', will 
report error.

Would you please clarify what does that mean?

Thank you
Yao Jiewen


> -Original Message-
> From: Feng, YunhuaX
> Sent: Friday, February 2, 2018 9:42 PM
> To: Yao, Jiewen ; edk2-devel@lists.01.org
> Cc: Gao, Liming 
> Subject: RE: [PATCH] BaseTools: Update Expression.py for VOID* support L'a' 
> and
> 'a'
> 
> Yes, you are right.
> 
> L"String" and "String" still support,  and we add L'String' and 'String'
> L"ab"  ==> {0x61, 0x00, 0x62, 0x00, 0x00, 0x00}
> L'ab'   ==> {0x61, 0x00, 0x62, 0x00}
> 
> Any question, please let me know. Thanks.
> 
> Best Regards
> Feng, Yunhua
> 
> -Original Message-
> From: Yao, Jiewen
> Sent: Friday, February 2, 2018 8:17 PM
> To: Feng, YunhuaX ; edk2-devel@lists.01.org
> Cc: Gao, Liming ; Yao, Jiewen 
> Subject: RE: [PATCH] BaseTools: Update Expression.py for VOID* support L'a' 
> and
> 'a'
> 
> Hello
> May I know why we do not support L"String" ?
> 
> My understanding is that L'String' is a string without NULL terminator, 
> L"String" is
> a string with NULL terminator, right?
> 
> Thank you
> Yao Jiewen
> 
> > -Original Message-
> > From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
> > Feng, YunhuaX
> > Sent: Friday, February 2, 2018 5:02 PM
> > To: edk2-devel@lists.01.org
> > Cc: Gao, Liming 
> > Subject: [edk2] [PATCH] BaseTools: Update Expression.py for VOID* support
> L'a'
> > and 'a'
> >
> > Type VOID* support L'a' and 'a', the value transfer to c style value.
> > L'a' --> {0x61, 0x00}
> > L'ab' --> {0x61, 0x00, 0x62, 0x00}
> > 'a'  --> {0x61}
> > 'ab' --> {0x61, 0x62}
> >
> > when the value is L'' or '', will report error
> >
> > Cc: Liming Gao 
> > Cc: Yonghong Zhu 
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Yunhua Feng 
> > ---
> >  BaseTools/Source/Python/Common/Expression.py | 19
> ---
> >  BaseTools/Source/Python/Common/Misc.py   |  4 
> >  2 files changed, 20 insertions(+), 3 deletions(-)
> >
> > diff --git a/BaseTools/Source/Python/Common/Expression.py
> > b/BaseTools/Source/Python/Common/Expression.py
> > index b8c48460ff..6a1103df2c 100644
> > --- a/BaseTools/Source/Python/Common/Expression.py
> > +++ b/BaseTools/Source/Python/Common/Expression.py
> > @@ -740,7 +740,12 @@ class ValueExpressionEx(ValueExpression):
> >  try:
> >  PcdValue = ValueExpression.__call__(self, RealValue, Depth)
> >  if self.PcdType == 'VOID*' and (PcdValue.startswith("'")
> > or
> > PcdValue.startswith("L'")):
> > -raise BadExpression
> > +PcdValue, Size = ParseFieldValue(PcdValue)
> > +PcdValueList = []
> > +for I in range(Size):
> > +PcdValueList.append('0x%02X'%(PcdValue & 0xff))
> > +PcdValue = PcdValue >> 8
> > +PcdValue = '{' + ','.join(PcdValueList) + '}'
> >  elif self.PcdType in ['UINT8', 'UINT16', 'UINT32',
> > 'UINT64', 'BOOLEAN'] and (PcdValue.startswith("'") or \
> >PcdValue.startswith('"') or
> > PcdValue.startswith("L'") or PcdValue.startswith('L"') or
> PcdValue.startswith('{')):
> >  raise BadExpression
> > @@ -755,6 +760,8 @@ class ValueExpressionEx(ValueExpression):
> >  TmpValue = 0
> >  Size = 0
> >  for Item in PcdValue:
> > +if Item.startswith('UINT8'):
> > +ItemSize = 1
> >  if Item.startswith('UINT16'):
> >  ItemSize = 2
> >  elif Item.startswith('UINT32'):
> > @@ -776,7 +783,10 @@ class ValueExpressionEx(ValueExpression):
> >  TmpValue = (ItemValue << (Size * 8)) | TmpValue
> >  Size = Size + ItemSize
> >  else:
> > -TmpValue, Size = ParseFieldValue(PcdValue)
> > +try:
> > +TmpValue, Size = ParseFieldValue(PcdValue)
> > +except BadExpression:
> > +raise BadExpression("Type: %s, Value: %s,
> > + format
> > or value error" % (self.PcdType, PcdValue))
> >  if type(TmpValue) == type(''):
> >  TmpValue = int(TmpValue)
> >  else:
> > @@ -858,7 +868,7 @@ class ValueExpressionEx(ValueExpression):
> >  else:
> >  raise BadExpression('%s not
> > defined before use' % Offset)
> >  ValueType = ""
> > -if 

[edk2] [PATCH 03/14] UefiCpuPkg/PiSmmCpuDxeSmm: remove *.S and *.asm assembly files

[Laszlo Ersek]

All edk2 toolchains use NASM for compiling X86 assembly source code. We
plan to remove X86 *.S and *.asm files globally, in order to reduce
maintenance and confusion:

4A89E2EF3DFEDB4C8BFDE51014F606A14E1B9F76@SHSMSX104.ccr.corp.intel.com">http://mid.mail-archive.com/4A89E2EF3DFEDB4C8BFDE51014F606A14E1B9F76@SHSMSX104.ccr.corp.intel.com

Let's start with UefiCpuPkg/PiSmmCpuDxeSmm: remove the *.S and *.asm
dialects (both Ia32 and X64) of the SmmInit, SmiEntry, SmiException and
MpFuncs sources.

Cc: Eric Dong 
Cc: Jiewen Yao 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ruiyu Ni 
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek 
---
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf|  20 -
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/MpFuncs.S| 165 -
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/MpFuncs.asm  | 168 -
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S   | 215 --
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm | 223 --
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.S   | 696 ---
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.asm | 713 
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.S|  84 ---
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.asm  |  94 ---
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/MpFuncs.S | 204 --
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/MpFuncs.asm   | 206 --
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S| 243 ---
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm  | 242 ---
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.S| 365 --
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.asm  | 383 ---
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.S | 141 
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.asm   | 132 
 17 files changed, 4294 deletions(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf 
b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
index e37ac5f84ee1..52d8c550752b 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
@@ -53,42 +53,22 @@ [Sources.Ia32]
   Ia32/SmmFuncsArch.c
   Ia32/SmmProfileArch.c
   Ia32/SmmProfileArch.h
-  Ia32/SmmInit.asm
-  Ia32/SmiEntry.asm
-  Ia32/SmiException.asm
-  Ia32/MpFuncs.asm
-
   Ia32/SmmInit.nasm
   Ia32/SmiEntry.nasm
   Ia32/SmiException.nasm
   Ia32/MpFuncs.nasm
 
-  Ia32/SmmInit.S
-  Ia32/SmiEntry.S
-  Ia32/SmiException.S
-  Ia32/MpFuncs.S
-
 [Sources.X64]
   X64/Semaphore.c
   X64/PageTbl.c
   X64/SmmFuncsArch.c
   X64/SmmProfileArch.c
   X64/SmmProfileArch.h
-  X64/SmmInit.asm
-  X64/SmiEntry.asm
-  X64/SmiException.asm
-  X64/MpFuncs.asm
-
   X64/SmmInit.nasm
   X64/SmiEntry.nasm
   X64/SmiException.nasm
   X64/MpFuncs.nasm
 
-  X64/SmmInit.S
-  X64/SmiEntry.S
-  X64/SmiException.S
-  X64/MpFuncs.S
-
 [Packages]
   MdePkg/MdePkg.dec
   MdeModulePkg/MdeModulePkg.dec
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/MpFuncs.S 
b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/MpFuncs.S
deleted file mode 100644
index 75aa312a6e8a..
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/MpFuncs.S
+++ /dev/null
@@ -1,165 +0,0 @@
-#--
-#
-# Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD 
License
-# which accompanies this distribution.  The full text of the license may be 
found at
-# http://opensource.org/licenses/bsd-license.php.
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-# Module Name:
-#
-#   MpFuncs.S
-#
-# Abstract:
-#
-#   This is the assembly code for Multi-processor S3 support
-#
-#--
-
-.equ   VacantFlag,   0x0
-.equ   NotVacantFlag,0xff
-
-.equ   LockLocation, RendezvousFunnelProcEnd - 
RendezvousFunnelProcStart
-.equ   StackStart,   RendezvousFunnelProcEnd - 
RendezvousFunnelProcStart + 0x04
-.equ   StackSize,RendezvousFunnelProcEnd - 
RendezvousFunnelProcStart + 0x08
-.equ   RendezvousProc,   RendezvousFunnelProcEnd - 
RendezvousFunnelProcStart + 0x0C
-.equ   GdtrProfile,  RendezvousFunnelProcEnd - 
RendezvousFunnelProcStart + 0x10
-.equ   IdtrProfile,  RendezvousFunnelProcEnd - 
RendezvousFunnelProcStart + 0x16
-.equ   BufferStart,  RendezvousFunnelProcEnd - 
RendezvousFunnelProcStart + 0x1C
-
-#-
-#RendezvousFunnelProc  procedure follows. All APs execute their 

[edk2] [PATCH 09/14] UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmmCr3" with PatchInstructionX86()

[Laszlo Ersek]

Rename the variable to "gPatchSmmCr3" so that its association with
PatchInstructionX86() is clear from the declaration, change its type to
UINT8, and patch it with PatchInstructionX86(). This lets us remove the
binary (DB) encoding of some instructions in "SmmInit.nasm".

Cc: Eric Dong 
Cc: Jiewen Yao 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ruiyu Ni 
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek 
---
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h  | 2 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c  | 2 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm | 6 +++---
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm  | 6 +++---
 4 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h 
b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
index a2babb987732..c862f48a2fea 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
@@ -309,7 +309,7 @@ extern IA32_FAR_ADDRESS gSmmJmpAddr;
 extern CONST UINT8  gcSmmInitTemplate[];
 extern CONST UINT16 gcSmmInitSize;
 extern UINT32   gSmmCr0;
-extern UINT32   gSmmCr3;
+extern UINT8gPatchSmmCr3;
 extern UINT32   gSmmCr4;
 extern UINTNgSmmInitStack;
 
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c 
b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
index a27d1f4684f5..804727acc218 100755
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
@@ -406,7 +406,7 @@ SmmRelocateBases (
   // Patch ASM code template with current CR0, CR3, and CR4 values
   //
   gSmmCr0 = (UINT32)AsmReadCr0 ();
-  gSmmCr3 = (UINT32)AsmReadCr3 ();
+  PatchInstructionX86 (, AsmReadCr3 (), 4);
   gSmmCr4 = (UINT32)AsmReadCr4 ();
 
   //
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm 
b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
index d64fcd48d03e..f7bb9b9a82e5 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
@@ -22,7 +22,7 @@ extern ASM_PFX(SmmInitHandler)
 extern ASM_PFX(mRebasedFlag)
 extern ASM_PFX(mSmmRelocationOriginalAddress)
 
-global ASM_PFX(gSmmCr3)
+global ASM_PFX(gPatchSmmCr3)
 global ASM_PFX(gSmmCr4)
 global ASM_PFX(gSmmCr0)
 global ASM_PFX(gSmmJmpAddr)
@@ -49,8 +49,8 @@ ASM_PFX(SmmStartup):
 mov ebx, edx; rdmsr will change edx. keep it in 
ebx.
 and ebx, BIT20  ; extract NX capability bit
 shr ebx, 9  ; shift bit to IA32_EFER.NXE[BIT11] 
position
-DB  0x66, 0xb8  ; mov eax, imm32
-ASM_PFX(gSmmCr3): DD 0
+mov eax, strict dword 0 ; source operand will be patched
+ASM_PFX(gPatchSmmCr3):
 mov cr3, eax
 o32 lgdt[cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]
 DB  0x66, 0xb8  ; mov eax, imm32
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm 
b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
index 2eaf1433dcd6..2df22a1f6cd1 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
@@ -22,7 +22,7 @@ extern ASM_PFX(SmmInitHandler)
 extern ASM_PFX(mRebasedFlag)
 extern ASM_PFX(mSmmRelocationOriginalAddress)
 
-global ASM_PFX(gSmmCr3)
+global ASM_PFX(gPatchSmmCr3)
 global ASM_PFX(gSmmCr4)
 global ASM_PFX(gSmmCr0)
 global ASM_PFX(gSmmJmpAddr)
@@ -47,8 +47,8 @@ ASM_PFX(SmmStartup):
 mov eax, 0x8001 ; read capability
 cpuid
 mov ebx, edx; rdmsr will change edx. keep it in 
ebx.
-DB  0x66, 0xb8   ; mov eax, imm32
-ASM_PFX(gSmmCr3): DD 0
+mov eax, strict dword 0 ; source operand will be patched
+ASM_PFX(gPatchSmmCr3):
 mov cr3, eax
 o32 lgdt[cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]
 DB  0x66, 0xb8   ; mov eax, imm32
-- 
2.14.1.3.gb7cf6e02401b


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[edk2] [PATCH 08/14] UefiCpuPkg/PiSmmCpuDxeSmm: remove unneeded DBs from X64 SmmStartup()

[Laszlo Ersek]

(This patch is the 64-bit variant of commit e75ee97224e5,
"UefiCpuPkg/PiSmmCpuDxeSmm: remove unneeded DBs from IA32 SmmStartup()",
2018-01-31.)

The SmmStartup() function executes in SMM, which is very similar to real
mode. Add "BITS 16" before it and "BITS 64" after it (just before the
@LongMode label).

Remove the manual 0x66 operand-size override prefixes, for selecting
32-bit operands -- the sizes of our operands trigger NASM to insert the
prefixes automatically in almost every spot. The one place where we have
to add it back manually is the LGDT instruction. In the LGDT instruction
we also replace the binary 0x2E prefix with the normal NASM syntax for CS
segment override.

The stores to the Control Registers were always 32-bit wide; the source
code only used RAX as source operand because it generated the expected
object code (with NASM compiling the source as if in BITS 64). With BITS
16 added, we can use the actual register width in the source operands
(EAX).

This patch causes NASM to generate byte-identical object code (determined
by disassembling both the pre-patch and post-patch versions, and comparing
the listings), except:

> @@ -231,7 +231,7 @@
>  01D2  6689D3mov ebx,edx
>  01D5  66B8  mov eax,0x0
>  01DB  0F22D8mov cr3,eax
> -01DE  662E670F0155F6o32 lgdt [cs:ebp-0xa]
> +01DE  2E66670F0155F6o32 lgdt [cs:ebp-0xa]
>  01E5  66B8  mov eax,0x0
>  01EB  80CC02or ah,0x2
>  01EE  0F22E0mov cr4,eax

The only difference is the prefix list order, it changes from:

- 0x66, 0x2E, 0x67

to

- 0x2E, 0x66, 0x67

Cc: Eric Dong 
Cc: Jiewen Yao 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ruiyu Ni 
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek 
---
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm | 17 -
 1 file changed, 8 insertions(+), 9 deletions(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm 
b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
index b147e7218019..2eaf1433dcd6 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
@@ -41,26 +41,23 @@ ASM_PFX(gcSmiInitGdtr):
 DQ  0
 
 global ASM_PFX(SmmStartup)
+
+BITS 16
 ASM_PFX(SmmStartup):
-DB  0x66
 mov eax, 0x8001 ; read capability
 cpuid
-DB  0x66
 mov ebx, edx; rdmsr will change edx. keep it in 
ebx.
 DB  0x66, 0xb8   ; mov eax, imm32
 ASM_PFX(gSmmCr3): DD 0
-mov cr3, rax
-DB  0x66, 0x2e
-lgdt[ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]
+mov cr3, eax
+o32 lgdt[cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]
 DB  0x66, 0xb8   ; mov eax, imm32
 ASM_PFX(gSmmCr4): DD 0
 or  ah,  2  ; enable XMM registers access
-mov cr4, rax
-DB  0x66
+mov cr4, eax
 mov ecx, 0xc080 ; IA32_EFER MSR
 rdmsr
 or  ah, BIT0; set LME bit
-DB  0x66
 testebx, BIT20  ; check NXE capability
 jz  .1
 or  ah, BIT3; set NXE bit
@@ -68,9 +65,11 @@ ASM_PFX(gSmmCr4): DD 0
 wrmsr
 DB  0x66, 0xb8   ; mov eax, imm32
 ASM_PFX(gSmmCr0): DD 0
-mov cr0, rax; enable protected mode & paging
+mov cr0, eax; enable protected mode & paging
 DB  0x66, 0xea   ; far jmp to long mode
 ASM_PFX(gSmmJmpAddr): DQ 0;@LongMode
+
+BITS 64
 @LongMode:  ; long-mode starts here
 DB  0x48, 0xbc   ; mov rsp, imm64
 ASM_PFX(gSmmInitStack): DQ 0
-- 
2.14.1.3.gb7cf6e02401b


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[edk2] [PATCH 06/14] UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmiCr3" with PatchInstructionX86()

[Laszlo Ersek]

Rename the variable to "gPatchSmiCr3" so that its association with
PatchInstructionX86() is clear from the declaration, change its type to
UINT8, and patch it with PatchInstructionX86(). This lets us remove the
binary (DB) encoding of some instructions in "SmiEntry.nasm".

Cc: Eric Dong 
Cc: Jiewen Yao 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ruiyu Ni 
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek 
---
 UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c   | 4 ++--
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 6 +++---
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm  | 6 +++---
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c 
b/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
index 73253016060d..c61963403477 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
@@ -107,7 +107,7 @@ typedef struct {
 ///
 extern UINT8gPatchSmbase;
 extern UINT8gPatchSmiStack;
-extern UINT32   gSmiCr3;
+extern UINT8gPatchSmiCr3;
 extern volatile UINT8   gcSmiHandlerTemplate[];
 extern CONST UINT16 gcSmiHandlerSize;
 
@@ -719,7 +719,7 @@ InstallSmiHandler (
   //
   CpuSmiStack = (UINT32)((UINTN)SmiStack + StackSize - sizeof (UINTN));
   PatchInstructionX86 (, CpuSmiStack, 4);
-  gSmiCr3   = Cr3;
+  PatchInstructionX86 (, Cr3, 4);
   PatchInstructionX86 (, SmBase, 4);
   gSmiHandlerIdtr.Base  = IdtBase;
   gSmiHandlerIdtr.Limit = (UINT16)(IdtSize - 1);
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm 
b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
index 0ea3c1e4498d..0023cb328d6a 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
@@ -44,7 +44,7 @@ extern ASM_PFX(CpuSmmDebugExit)
 
 global ASM_PFX(gcSmiHandlerTemplate)
 global ASM_PFX(gcSmiHandlerSize)
-global ASM_PFX(gSmiCr3)
+global ASM_PFX(gPatchSmiCr3)
 global ASM_PFX(gPatchSmiStack)
 global ASM_PFX(gPatchSmbase)
 global ASM_PFX(mXdSupported)
@@ -93,8 +93,8 @@ ASM_PFX(gPatchSmiStack):
 jmp ProtFlatMode
 
 ProtFlatMode:
-DB  0xb8; mov eax, imm32
-ASM_PFX(gSmiCr3): DD 0
+mov eax, strict dword 0   ; source operand will be patched
+ASM_PFX(gPatchSmiCr3):
 mov cr3, eax
 ;
 ; Need to test for CR4 specific bit support
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm 
b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
index 9cfa8e7fc8f4..9971ae6f064a 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
@@ -56,7 +56,7 @@ extern ASM_PFX(CpuSmmDebugExit)
 global ASM_PFX(gPatchSmbase)
 global ASM_PFX(mXdSupported)
 global ASM_PFX(gPatchSmiStack)
-global ASM_PFX(gSmiCr3)
+global ASM_PFX(gPatchSmiCr3)
 global ASM_PFX(gcSmiHandlerTemplate)
 global ASM_PFX(gcSmiHandlerSize)
 
@@ -102,8 +102,8 @@ ASM_PFX(gPatchSmiStack):
 
 BITS 64
 ProtFlatMode:
-DB  0xb8; mov eax, offset gSmiCr3
-ASM_PFX(gSmiCr3): DD 0
+mov eax, strict dword 0   ; source operand will be patched
+ASM_PFX(gPatchSmiCr3):
 mov cr3, rax
 mov eax, 0x668   ; as cr4.PGE is not set here, refresh 
cr3
 mov cr4, rax; in PreModifyMtrrs() to flush TLB.
-- 
2.14.1.3.gb7cf6e02401b


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[edk2] [PATCH 07/14] UefiCpuPkg/PiSmmCpuDxeSmm: patch "XdSupported" with PatchInstructionX86()

[Laszlo Ersek]

"mXdSupported" is a global BOOLEAN variable, initialized to TRUE. The
CheckFeatureSupported() function is executed on all processors (not
concurrently though), called from SmmInitHandler(). If XD support is found
to be missing on any CPU, then "mXdSupported" is set to FALSE, and further
processors omit the check. Afterwards, "mXdSupported" is read by several
assembly and C code locations.

The tricky part is *where* "mXdSupported" is allocated (defined):

- Before commit 717fb60443fb ("UefiCpuPkg/PiSmmCpuDxeSmm: Add paging
  protection.", 2016-11-17), it used to be a normal global variable,
  defined (allocated) in "SmmProfile.c".

- With said commit, we moved the definition (allocation) of "mXdSupported"
  into "SmiEntry.nasm". The variable was defined over the last byte of a
  "mov al, 1" instruction, so that setting it to FALSE in
  CheckFeatureSupported() would patch the instruction to "mov al, 0". The
  subsequent conditional jump would change behavior, plus all further read
  references to "mXdSupported" (in C and assembly code) would read back
  the source (imm8) operand of the patched MOV instruction as data.

  This trick required that the MOV instruction be encoded with DB.

In order to get rid of the DB, we have to split both roles: we need a
helper variable for the code patching, and "mXdSupported" has to be
defined (allocated) independently of the code patching. Of course, their
values must always remain in sync.

(1) Reinstate the "mXdSupported" definition and initialization in
"SmmProfile.c" from before commit 717fb60443fb. Change the assembly
language definition ("global") to a declaration ("extern").

(2) Define the "gPatchXdSupported" helper (type UINT8) in "SmiEntry.nasm",
and add the C-language declaration to "SmmProfileInternal.h". Replace
the DB with the MOV mnemonic (keeping the imm8 source operand with
value 1).

(3) In CheckFeatureSupported(), whenever "mXdSupported" is set to FALSE,
patch the assembly code in sync, with PatchInstructionX86().

Cc: Eric Dong 
Cc: Jiewen Yao 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ruiyu Ni 
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek 
---
 UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h | 1 +
 UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 7 +++
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm   | 7 ---
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm| 7 ---
 4 files changed, 16 insertions(+), 6 deletions(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h 
b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h
index a21689145bb4..1c8b899f9455 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h
@@ -100,6 +100,7 @@ typedef struct {
 extern SMM_S3_RESUME_STATE   *mSmmS3ResumeState;
 extern UINTN gSmiExceptionHandlers[];
 extern BOOLEAN   mXdSupported;
+extern UINT8 gPatchXdSupported;
 extern UINTN *mPFEntryCount;
 extern UINT64(*mLastPFEntryValue)[MAX_PF_ENTRY_COUNT];
 extern UINT64*(*mLastPFEntryPointer)[MAX_PF_ENTRY_COUNT];
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c 
b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
index 9588eaf02964..fb0d0b365e05 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
@@ -31,6 +31,11 @@ UINTN mSmmProfileSize;
 //
 UINTN mMsrDsAreaSize   = SMM_PROFILE_DTS_SIZE;
 
+//
+// The flag indicates if execute-disable is supported by processor.
+//
+BOOLEAN   mXdSupported = TRUE;
+
 //
 // The flag indicates if execute-disable is enabled on processor.
 //
@@ -1010,6 +1015,7 @@ CheckFeatureSupported (
   // Extended CPUID functions are not supported on this processor.
   //
   mXdSupported = FALSE;
+  PatchInstructionX86 (, mXdSupported, 1);
 }
 
 AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, );
@@ -1018,6 +1024,7 @@ CheckFeatureSupported (
   // Execute Disable Bit feature is not supported on this processor.
   //
   mXdSupported = FALSE;
+  PatchInstructionX86 (, mXdSupported, 1);
 }
   }
 
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm 
b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
index 0023cb328d6a..509e7a0a665f 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
@@ -47,7 +47,8 @@ global ASM_PFX(gcSmiHandlerSize)
 global ASM_PFX(gPatchSmiCr3)
 global ASM_PFX(gPatchSmiStack)
 global ASM_PFX(gPatchSmbase)
-global ASM_PFX(mXdSupported)
+extern ASM_PFX(mXdSupported)
+global ASM_PFX(gPatchXdSupported)
 extern ASM_PFX(gSmiHandlerIdtr)
 
 SECTION .text
@@ -133,8 

[edk2] [PATCH 11/14] UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmmCr0" with PatchInstructionX86()

[Laszlo Ersek]

Like "gSmmCr4" in the previous patch, "gSmmCr0" is not only used for
machine code patching, but also as a means to communicate the initial CR0
value from SmmRelocateBases() to InitSmmS3ResumeState(). In other words,
the last four bytes of the "mov eax, Cr0Value" instruction's binary
representation are utilized as normal data too.

In order to get rid of the DB for "mov eax, Cr0Value", we have to split
both roles, patching and data flow. Introduce the "mSmmCr0" global (SMRAM)
variable for the data flow purpose. Rename the "gSmmCr0" variable to
"gPatchSmmCr0" so that its association with PatchInstructionX86() is clear
from the declaration, change its type to UINT8, and patch it with
PatchInstructionX86(), to the value now contained in "mSmmCr0".

This lets us remove the binary (DB) encoding of "mov eax, Cr0Value" in
"SmmInit.nasm".

Cc: Eric Dong 
Cc: Jiewen Yao 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ruiyu Ni 
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek 
---
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h  | 3 ++-
 UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c   | 2 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c  | 4 +++-
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm | 6 +++---
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm  | 6 +++---
 5 files changed, 12 insertions(+), 9 deletions(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h 
b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
index adf341586f03..d4fca08aa695 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
@@ -308,7 +308,8 @@ extern IA32_FAR_ADDRESS gSmmJmpAddr;
 
 extern CONST UINT8  gcSmmInitTemplate[];
 extern CONST UINT16 gcSmmInitSize;
-extern UINT32   gSmmCr0;
+extern UINT8gPatchSmmCr0;
+extern UINT32   mSmmCr0;
 extern UINT8gPatchSmmCr3;
 extern UINT32   mSmmCr4;
 extern UINT8gPatchSmmCr4;
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c 
b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
index b4ed0a56a814..0b8ef7035903 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
@@ -744,7 +744,7 @@ InitSmmS3ResumeState (
   SmmS3ResumeState->SmmS3StackSize = 0;
 }
 
-SmmS3ResumeState->SmmS3Cr0 = gSmmCr0;
+SmmS3ResumeState->SmmS3Cr0 = mSmmCr0;
 SmmS3ResumeState->SmmS3Cr3 = Cr3;
 SmmS3ResumeState->SmmS3Cr4 = mSmmCr4;
 
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c 
b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
index be1d8e9978e0..797d3e63358d 100755
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
@@ -128,6 +128,7 @@ UINT8mPhysicalAddressBits;
 //
 // Control register contents saved for SMM S3 resume state initialization.
 //
+UINT32   mSmmCr0;
 UINT32   mSmmCr4;
 
 /**
@@ -410,7 +411,8 @@ SmmRelocateBases (
   //
   // Patch ASM code template with current CR0, CR3, and CR4 values
   //
-  gSmmCr0 = (UINT32)AsmReadCr0 ();
+  mSmmCr0 = (UINT32)AsmReadCr0 ();
+  PatchInstructionX86 (, mSmmCr0, 4);
   PatchInstructionX86 (, AsmReadCr3 (), 4);
   mSmmCr4 = (UINT32)AsmReadCr4 ();
   PatchInstructionX86 (, mSmmCr4, 4);
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm 
b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
index bd07a6e4f536..0f62fe448712 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
@@ -24,7 +24,7 @@ extern ASM_PFX(mSmmRelocationOriginalAddress)
 
 global ASM_PFX(gPatchSmmCr3)
 global ASM_PFX(gPatchSmmCr4)
-global ASM_PFX(gSmmCr0)
+global ASM_PFX(gPatchSmmCr0)
 global ASM_PFX(gSmmJmpAddr)
 global ASM_PFX(gSmmInitStack)
 global ASM_PFX(gcSmiInitGdtr)
@@ -60,8 +60,8 @@ ASM_PFX(gPatchSmmCr4):
 rdmsr
 or  eax, ebx; set NXE bit if NX is available
 wrmsr
-DB  0x66, 0xb8  ; mov eax, imm32
-ASM_PFX(gSmmCr0): DD 0
+mov eax, strict dword 0 ; source operand will be patched
+ASM_PFX(gPatchSmmCr0):
 mov di, PROTECT_MODE_DS
 mov cr0, eax
 DB  0x66, 0xea  ; jmp far [ptr48]
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm 
b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
index 971bd118132f..1a0667bd97ba 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
@@ -24,7 +24,7 @@ extern ASM_PFX(mSmmRelocationOriginalAddress)
 
 global ASM_PFX(gPatchSmmCr3)
 global ASM_PFX(gPatchSmmCr4)
-global ASM_PFX(gSmmCr0)
+global ASM_PFX(gPatchSmmCr0)
 global ASM_PFX(gSmmJmpAddr)
 global ASM_PFX(gSmmInitStack)
 global ASM_PFX(gcSmiInitGdtr)
@@ -63,8 

[edk2] [PATCH 01/14] MdePkg/BaseLib.h: state preprocessing conditions in comments after #endifs

[Laszlo Ersek]

"#endif" preprocessing directives near the top of "BaseLib.h" helpfully
repeat the preprocessing conditions from their matching "#if", "#ifdef",
and "#ifndef" directives. This practice has been less followed recently;
supplement the missing comments.

Cc: Ard Biesheuvel 
Cc: Eric Dong 
Cc: Jiewen Yao 
Cc: Leif Lindholm 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ruiyu Ni 
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek 
---
 MdePkg/Include/Library/BaseLib.h | 24 +---
 1 file changed, 11 insertions(+), 13 deletions(-)

diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index 39573db0c8da..e4455e71d5c3 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -1119,7 +1119,7 @@ StrnCpy (
   IN  CONST CHAR16  *Source,
   IN  UINTN Length
   );
-#endif
+#endif // !defined (DISABLE_NEW_DEPRECATED_INTERFACES)
 
 /**
   Returns the length of a Null-terminated Unicode string.
@@ -1338,7 +1338,7 @@ StrnCat (
   IN  CONST CHAR16  *Source,
   IN  UINTN Length
   );
-#endif
+#endif // !defined (DISABLE_NEW_DEPRECATED_INTERFACES)
 
 /**
   Returns the first occurrence of a Null-terminated Unicode sub-string
@@ -1811,7 +1811,7 @@ UnicodeStrToAsciiStr (
   OUT CHAR8 *Destination
   );
 
-#endif
+#endif // !defined (DISABLE_NEW_DEPRECATED_INTERFACES)
 
 /**
   Convert a Null-terminated Unicode string to a Null-terminated
@@ -1985,7 +1985,7 @@ AsciiStrnCpy (
   IN  CONST CHAR8   *Source,
   IN  UINTN Length
   );
-#endif
+#endif // !defined (DISABLE_NEW_DEPRECATED_INTERFACES)
 
 /**
   Returns the length of a Null-terminated ASCII string.
@@ -2229,7 +2229,7 @@ AsciiStrnCat (
   IN  CONST CHAR8   *Source,
   IN  UINTN Length
   );
-#endif
+#endif // !defined (DISABLE_NEW_DEPRECATED_INTERFACES)
 
 /**
   Returns the first occurrence of a Null-terminated ASCII sub-string
@@ -2670,7 +2670,7 @@ AsciiStrToUnicodeStr (
   OUT CHAR16*Destination
   );
 
-#endif
+#endif // !defined (DISABLE_NEW_DEPRECATED_INTERFACES)
 
 /**
   Convert one Null-terminated ASCII string to a Null-terminated
@@ -6495,7 +6495,7 @@ AsmPalCall (
   IN UINT64  Arg3,
   IN UINT64  Arg4
   );
-#endif
+#endif // defined (MDE_CPU_IPF)
 
 #if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)
 ///
@@ -6730,7 +6730,7 @@ typedef union {
 } IA32_TSS_DESCRIPTOR;
 #pragma pack ()
 
-#endif
+#endif // defined (MDE_CPU_IA32)
 
 #if defined (MDE_CPU_X64)
 ///
@@ -6792,7 +6792,7 @@ typedef union {
 } IA32_TSS_DESCRIPTOR;
 #pragma pack ()
 
-#endif
+#endif // defined (MDE_CPU_X64)
 
 ///
 /// Byte packed structure for an FP/SSE/SSE2 context.
@@ -9068,7 +9068,5 @@ AsmWriteTr (
   IN UINT16 Selector
   );
 
-#endif
-#endif
-
-
+#endif // defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)
+#endif // !defined (__BASE_LIB__)
-- 
2.14.1.3.gb7cf6e02401b


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[edk2] [PATCH 13/14] UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmmInitStack" with PatchInstructionX86()

[Laszlo Ersek]

Rename the variable to "gPatchSmmInitStack" so that its association with
PatchInstructionX86() is clear from the declaration, change its type to
UINT8, and patch it with PatchInstructionX86(). This lets us remove the
binary (DB) encoding of some instructions in "SmmInit.nasm".

The size of the patched source operand is (sizeof (UINTN)).

Cc: Eric Dong 
Cc: Jiewen Yao 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ruiyu Ni 
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek 
---
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h  | 2 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c  | 6 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm | 6 +++---
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm  | 6 +++---
 4 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h 
b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
index 5095c41af45e..d38d4782187f 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
@@ -302,7 +302,7 @@ extern UINT32   mSmmCr0;
 extern UINT8gPatchSmmCr3;
 extern UINT32   mSmmCr4;
 extern UINT8gPatchSmmCr4;
-extern UINTNgSmmInitStack;
+extern UINT8gPatchSmmInitStack;
 
 /**
   Semaphore operation for all processor relocate SMMBase.
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c 
b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
index 0609ed3738c7..501ebf0ed13f 100755
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
@@ -848,7 +848,11 @@ PiCpuSmmEntry (
   //
   // Set SMI stack for SMM base relocation
   //
-  gSmmInitStack = (UINTN) (Stacks + mSmmStackSize - sizeof (UINTN));
+  PatchInstructionX86 (
+,
+(UINTN) (Stacks + mSmmStackSize - sizeof (UINTN)),
+sizeof (UINTN)
+);
 
   //
   // Initialize IDT
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm 
b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
index f59413d9d4a3..5ff3cd2e731f 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
@@ -25,7 +25,7 @@ extern ASM_PFX(mSmmRelocationOriginalAddress)
 global ASM_PFX(gPatchSmmCr3)
 global ASM_PFX(gPatchSmmCr4)
 global ASM_PFX(gPatchSmmCr0)
-global ASM_PFX(gSmmInitStack)
+global ASM_PFX(gPatchSmmInitStack)
 global ASM_PFX(gcSmiInitGdtr)
 global ASM_PFX(gcSmmInitSize)
 global ASM_PFX(gcSmmInitTemplate)
@@ -72,8 +72,8 @@ BITS 32
 mov fs, edi
 mov gs, edi
 mov ss, edi
-DB  0xbc; mov esp, imm32
-ASM_PFX(gSmmInitStack): DD 0
+mov esp, strict dword 0 ; source operand will be patched
+ASM_PFX(gPatchSmmInitStack):
 callASM_PFX(SmmInitHandler)
 rsm
 
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm 
b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
index 2460e1eb2dee..eae14c0549f0 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
@@ -25,7 +25,7 @@ extern ASM_PFX(mSmmRelocationOriginalAddress)
 global ASM_PFX(gPatchSmmCr3)
 global ASM_PFX(gPatchSmmCr4)
 global ASM_PFX(gPatchSmmCr0)
-global ASM_PFX(gSmmInitStack)
+global ASM_PFX(gPatchSmmInitStack)
 global ASM_PFX(gcSmiInitGdtr)
 global ASM_PFX(gcSmmInitSize)
 global ASM_PFX(gcSmmInitTemplate)
@@ -72,8 +72,8 @@ ASM_PFX(gPatchSmmCr0):
 
 BITS 64
 @LongMode:  ; long-mode starts here
-DB  0x48, 0xbc   ; mov rsp, imm64
-ASM_PFX(gSmmInitStack): DQ 0
+mov rsp, strict qword 0 ; source operand will be patched
+ASM_PFX(gPatchSmmInitStack):
 and sp, 0xfff0  ; make sure RSP is 16-byte aligned
 ;
 ; Accoring to X64 calling convention, XMM0~5 are volatile, we need to save
-- 
2.14.1.3.gb7cf6e02401b


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[edk2] [PATCH 10/14] UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmmCr4" with PatchInstructionX86()

[Laszlo Ersek]

Unlike "gSmmCr3" in the previous patch, "gSmmCr4" is not only used for
machine code patching, but also as a means to communicate the initial CR4
value from SmmRelocateBases() to InitSmmS3ResumeState(). In other words,
the last four bytes of the "mov eax, Cr4Value" instruction's binary
representation are utilized as normal data too.

In order to get rid of the DB for "mov eax, Cr4Value", we have to split
both roles, patching and data flow. Introduce the "mSmmCr4" global (SMRAM)
variable for the data flow purpose. Rename the "gSmmCr4" variable to
"gPatchSmmCr4" so that its association with PatchInstructionX86() is clear
from the declaration, change its type to UINT8, and patch it with
PatchInstructionX86(), to the value now contained in "mSmmCr4".

This lets us remove the binary (DB) encoding of "mov eax, Cr4Value" in
"SmmInit.nasm".

Cc: Eric Dong 
Cc: Jiewen Yao 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ruiyu Ni 
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek 
---
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h  | 3 ++-
 UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c   | 2 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c  | 8 +++-
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm | 6 +++---
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm  | 6 +++---
 5 files changed, 16 insertions(+), 9 deletions(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h 
b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
index c862f48a2fea..adf341586f03 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
@@ -310,7 +310,8 @@ extern CONST UINT8  gcSmmInitTemplate[];
 extern CONST UINT16 gcSmmInitSize;
 extern UINT32   gSmmCr0;
 extern UINT8gPatchSmmCr3;
-extern UINT32   gSmmCr4;
+extern UINT32   mSmmCr4;
+extern UINT8gPatchSmmCr4;
 extern UINTNgSmmInitStack;
 
 /**
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c 
b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
index 554629536a5d..b4ed0a56a814 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
@@ -746,7 +746,7 @@ InitSmmS3ResumeState (
 
 SmmS3ResumeState->SmmS3Cr0 = gSmmCr0;
 SmmS3ResumeState->SmmS3Cr3 = Cr3;
-SmmS3ResumeState->SmmS3Cr4 = gSmmCr4;
+SmmS3ResumeState->SmmS3Cr4 = mSmmCr4;
 
 if (sizeof (UINTN) == sizeof (UINT64)) {
   SmmS3ResumeState->Signature = SMM_S3_RESUME_SMM_64;
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c 
b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
index 804727acc218..be1d8e9978e0 100755
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
@@ -125,6 +125,11 @@ UINTNmSmmCpuSmramRangeCount;
 
 UINT8mPhysicalAddressBits;
 
+//
+// Control register contents saved for SMM S3 resume state initialization.
+//
+UINT32   mSmmCr4;
+
 /**
   Initialize IDT to setup exception handlers for SMM.
 
@@ -407,7 +412,8 @@ SmmRelocateBases (
   //
   gSmmCr0 = (UINT32)AsmReadCr0 ();
   PatchInstructionX86 (, AsmReadCr3 (), 4);
-  gSmmCr4 = (UINT32)AsmReadCr4 ();
+  mSmmCr4 = (UINT32)AsmReadCr4 ();
+  PatchInstructionX86 (, mSmmCr4, 4);
 
   //
   // Patch GDTR for SMM base relocation
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm 
b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
index f7bb9b9a82e5..bd07a6e4f536 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
@@ -23,7 +23,7 @@ extern ASM_PFX(mRebasedFlag)
 extern ASM_PFX(mSmmRelocationOriginalAddress)
 
 global ASM_PFX(gPatchSmmCr3)
-global ASM_PFX(gSmmCr4)
+global ASM_PFX(gPatchSmmCr4)
 global ASM_PFX(gSmmCr0)
 global ASM_PFX(gSmmJmpAddr)
 global ASM_PFX(gSmmInitStack)
@@ -53,8 +53,8 @@ ASM_PFX(SmmStartup):
 ASM_PFX(gPatchSmmCr3):
 mov cr3, eax
 o32 lgdt[cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]
-DB  0x66, 0xb8  ; mov eax, imm32
-ASM_PFX(gSmmCr4): DD 0
+mov eax, strict dword 0 ; source operand will be patched
+ASM_PFX(gPatchSmmCr4):
 mov cr4, eax
 mov ecx, 0xc080 ; IA32_EFER MSR
 rdmsr
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm 
b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
index 2df22a1f6cd1..971bd118132f 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
@@ -23,7 +23,7 @@ extern ASM_PFX(mRebasedFlag)
 extern ASM_PFX(mSmmRelocationOriginalAddress)
 
 global ASM_PFX(gPatchSmmCr3)
-global ASM_PFX(gSmmCr4)
+global ASM_PFX(gPatchSmmCr4)
 global ASM_PFX(gSmmCr0)
 global ASM_PFX(gSmmJmpAddr)
 global ASM_PFX(gSmmInitStack)

[edk2] [PATCH 14/14] UefiCpuPkg/PiSmmCpuDxeSmm: remove DBs from SmmRelocationSemaphoreComplete32()

[Laszlo Ersek]

(1) SmmRelocationSemaphoreComplete32() runs in 32-bit mode, so wrap it in
a (BITS 32 ... BITS 64) bracket.

(2) SmmRelocationSemaphoreComplete32() currently compiles to:

> 02AE  C60501mov byte [dword 0x0],0x1
> 02B5  FF25  jmp dword [dword 0x0]

where the first instruction is patched with the contents of
"mRebasedFlag" (so that (*mRebasedFlag) is set to 1), and the second
instruction is patched with the address of
"mSmmRelocationOriginalAddress" (so that we jump to
"mSmmRelocationOriginalAddress").

In its current form the first instruction could not be patched with
PatchInstructionX86(), given that the operand to patch is not encoded
in the trailing bytes of the instruction. Therefore, adopt an
EAX-based version, inspired by both the IA32 and X64 variants of
SmmRelocationSemaphoreComplete():

> 02AE  50push eax
> 02AF  B8mov eax,0x0
> 02B4  C60001mov byte [eax],0x1
> 02B7  58pop eax
> 02B8  FF25  jmp dword [dword 0x0]

Here both instructions can be patched with PatchInstructionX86(), and
the DBs can be replaced with native NASM syntax.

(3) Turn the "mRebasedFlagAddr32" and "mSmmRelocationOriginalAddressPtr32"
variables into markers that suit PatchInstructionX86().

This removes the last instructions encoded with DBs from PiSmmCpuDxeSmm.

Cc: Eric Dong 
Cc: Jiewen Yao 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ruiyu Ni 
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek 
---
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c  | 16 +
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm | 24 +---
 2 files changed, 23 insertions(+), 17 deletions(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c 
b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c
index 6dbcb086aa4d..1586bbb626bb 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c
@@ -15,8 +15,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 
 #include "PiSmmCpuDxeSmm.h"
 
-extern  UINT32mSmmRelocationOriginalAddressPtr32;
-extern  UINT32mRebasedFlagAddr32;
+extern  UINT8 gPatchSmmRelocationOriginalAddressPtr32;
+extern  UINT8 gPatchRebasedFlagAddr32;
 
 UINTN mSmmRelocationOriginalAddress;
 volatile BOOLEAN  *mRebasedFlag;
@@ -49,7 +49,11 @@ SemaphoreHook (
   UINTN TempValue;
 
   mRebasedFlag   = RebasedFlag;
-  mRebasedFlagAddr32 = (UINT32)(UINTN)mRebasedFlag;
+  PatchInstructionX86 (
+,
+(UINT32)(UINTN)mRebasedFlag,
+4
+);
 
   CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + 
SMRAM_SAVE_STATE_MAP_OFFSET);
   mSmmRelocationOriginalAddress = HookReturnFromSmm (
@@ -63,5 +67,9 @@ SemaphoreHook (
   // Use temp value to fix ICC complier warning
   //
   TempValue = (UINTN)
-  mSmmRelocationOriginalAddressPtr32 = (UINT32)TempValue;
+  PatchInstructionX86 (
+,
+(UINT32)TempValue,
+4
+);
 }
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm 
b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
index eae14c0549f0..0b0c3f28e53f 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
@@ -29,8 +29,8 @@ global ASM_PFX(gPatchSmmInitStack)
 global ASM_PFX(gcSmiInitGdtr)
 global ASM_PFX(gcSmmInitSize)
 global ASM_PFX(gcSmmInitTemplate)
-global ASM_PFX(mRebasedFlagAddr32)
-global ASM_PFX(mSmmRelocationOriginalAddressPtr32)
+global ASM_PFX(gPatchRebasedFlagAddr32)
+global ASM_PFX(gPatchSmmRelocationOriginalAddressPtr32)
 
 %define LONG_MODE_CS 0x38
 
@@ -125,20 +125,18 @@ ASM_PFX(SmmRelocationSemaphoreComplete):
 ;
 ; Semaphore code running in 32-bit mode
 ;
+BITS 32
 global ASM_PFX(SmmRelocationSemaphoreComplete32)
 ASM_PFX(SmmRelocationSemaphoreComplete32):
-;
-; mov byte ptr [], 1
-;
-db  0xc6, 0x5
-ASM_PFX(mRebasedFlagAddr32): dd 0
-db  1
-;
-; jmp dword ptr []
-;
-db  0xff, 0x25
-ASM_PFX(mSmmRelocationOriginalAddressPtr32): dd 0
+pusheax
+mov eax, strict dword 0; source operand will be patched
+ASM_PFX(gPatchRebasedFlagAddr32):
+mov byte [eax], 1
+pop eax
+jmp dword [dword 0]; destination will be patched
+ASM_PFX(gPatchSmmRelocationOriginalAddressPtr32):
 
+BITS 64
 global ASM_PFX(PiSmmCpuSmmInitFixupAddress)
 ASM_PFX(PiSmmCpuSmmInitFixupAddress):
 learax, [@LongMode]
-- 
2.14.1.3.gb7cf6e02401b

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[edk2] [PATCH 12/14] UefiCpuPkg/PiSmmCpuDxeSmm: eliminate "gSmmJmpAddr" and related DBs

[Laszlo Ersek]

The IA32 version of "SmmInit.nasm" does not need "gSmmJmpAddr" at all (its
PiSmmCpuSmmInitFixupAddress() variant doesn't do anything either). We can
simply use the NASM syntax for the following Mixed-Size Jump:

> jmp PROTECT_MODE_CS : dword @32bit

The generated object code for the instruction is unchanged:

> 0182  66EA5A000800  jmp dword 0x8:0x5a

(The NASM manual explains that putting the DWORD prefix after the colon
":" reflects the intent better, since it is the offset that is a DWORD.
Thus, that's what I used. However, both syntaxes are interchangeable,
hence the ndisasm output.)

The X64 version of "SmmInit.nasm" appears to require "gSmmJmpAddr";
however that's accidental, not inherent:

- Bring LONG_MODE_CODE_SEGMENT from
  "UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h" to "SmmInit.nasm" as
  LONG_MODE_CS, same as PROTECT_MODE_CODE_SEGMENT was brought to the IA32
  version as PROTECT_MODE_CS earlier.

- Apply the NASM-native Mixed-Size Jump syntax again, but jump to the
  fixed zero offset in LONG_MODE_CS. This will produce no relocation
  record at all. Add a label after the instruction.

- Modify PiSmmCpuSmmInitFixupAddress() to patch the jump target backwards
  from the label. Because we modify the DWORD offset with a DWORD access,
  the segment selector is unharmed in the instruction, and we need not set
  it from PiCpuSmmEntry().

According to "objdump --reloc", the X64 version undergoes only the
following relocations, after this patch:

> RELOCATION RECORDS FOR [.text]:
> OFFSET   TYPE  VALUE
> 0095 R_X86_64_PC32 SmmInitHandler-0x0004
> 00e0 R_X86_64_PC32 mRebasedFlag-0x0004
> 00ea R_X86_64_PC32 
> mSmmRelocationOriginalAddress-0x0004

Therefore the patch does not regress
 ("Enable XCODE5 tool
chain for UefiCpuPkg with nasm source code").

Cc: Eric Dong 
Cc: Jiewen Yao 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ruiyu Ni 
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek 
---
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h  | 11 ---
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c  |  7 ---
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm |  6 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm  | 11 ++-
 4 files changed, 7 insertions(+), 28 deletions(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h 
b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
index d4fca08aa695..5095c41af45e 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
@@ -295,17 +295,6 @@ WriteSaveStateRegister (
   IN CONST VOID   *Buffer
   );
 
-//
-//
-//
-typedef struct {
-  UINT32Offset;
-  UINT16Segment;
-  UINT16Reserved;
-} IA32_FAR_ADDRESS;
-
-extern IA32_FAR_ADDRESS gSmmJmpAddr;
-
 extern CONST UINT8  gcSmmInitTemplate[];
 extern CONST UINT16 gcSmmInitSize;
 extern UINT8gPatchSmmCr0;
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c 
b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
index 797d3e63358d..0609ed3738c7 100755
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
@@ -569,13 +569,6 @@ PiCpuSmmEntry (
 EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_SMM_INIT
 );
 
-  //
-  // Fix segment address of the long-mode-switch jump
-  //
-  if (sizeof (UINTN) == sizeof (UINT64)) {
-gSmmJmpAddr.Segment = LONG_MODE_CODE_SEGMENT;
-  }
-
   //
   // Find out SMRR Base and SMRR Size
   //
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm 
b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
index 0f62fe448712..f59413d9d4a3 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
@@ -25,7 +25,6 @@ extern ASM_PFX(mSmmRelocationOriginalAddress)
 global ASM_PFX(gPatchSmmCr3)
 global ASM_PFX(gPatchSmmCr4)
 global ASM_PFX(gPatchSmmCr0)
-global ASM_PFX(gSmmJmpAddr)
 global ASM_PFX(gSmmInitStack)
 global ASM_PFX(gcSmiInitGdtr)
 global ASM_PFX(gcSmmInitSize)
@@ -64,10 +63,7 @@ ASM_PFX(gPatchSmmCr4):
 ASM_PFX(gPatchSmmCr0):
 mov di, PROTECT_MODE_DS
 mov cr0, eax
-DB  0x66, 0xea  ; jmp far [ptr48]
-ASM_PFX(gSmmJmpAddr):
-DD  @32bit
-DW  PROTECT_MODE_CS
+jmp PROTECT_MODE_CS : dword @32bit
 
 BITS 32
 @32bit:
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm 
b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
index 1a0667bd97ba..2460e1eb2dee 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
@@ -25,7 

Re: [edk2] [PATCH 04/10] MdeModulePkg/ResetSystemRuntimeDxe: Add platform filter and handler

[Laszlo Ersek]

On 02/02/18 07:45, Ruiyu Ni wrote:
> From: Michael D Kinney 
> 
> Add support for platform specific reset filters and platform
> specific reset handlers to ResetSystem().  A filter may modify
> the reset type and reset data and call ResetSystem() with the
> modified parameters.  A handler performs the reset action.
> 
> The support for platform specific filters and platform specific
> handlers is based on the Reset Notification feature added to the
> UEFI 2.7 Specification.
> 
> Platform specific reset filters are processed first so the final
> reset type and reset data can be determined.  In the DXE Phase
> The UEFI Reset Notifications are processed second so all UEFI
> Drivers that have registered for a Reset Notification can perform
> any required clean up actions.  The platform specific reset
> handlers are processed third.  If there are no registered
> platform specific reset handlers or none of them reset the
> platform, then the default reset action based on the
> ResetSystemLib is performed.
> 
> In the PEI Phase, filters are handlers are registered through
> the folloiwng 2 PPIs that are based on
> EFI_RESET_NOTIFICATION_PROTOCOL.
> * gEdkiiPlatformSpecificResetFilterPpiGuid
> * gEdkiiPlatformSpecificResetFilterPpiGuid

The second entry should be "gEdkiiPlatformSpecificResetHandlerPpiGuid".

> 
> In the DXE Phase, filters are handlers are registered through
> the folloiwng 2 Protocols that are based on
> EFI_RESET_NOTIFICATION_PROTOCOL.
> * gEdkiiPlatformSpecificResetFilterProtocolGuid
> * gEdkiiPlatformSpecificResetFilterProtocolGuid

The second entry should be "gEdkiiPlatformSpecificResetHandlerProtocolGuid".

[...]

Thanks
Laszlo
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Re: [edk2] MinPlatformPkg/PlatformInit: FV code

[Yao, Jiewen]

Excellent question.

Comment inline.

From: Marvin H?user [mailto:marvin.haeu...@outlook.com]
Sent: Wednesday, January 31, 2018 1:54 AM
To: edk2-devel@lists.01.org; Yao, Jiewen 
Subject: MinPlatformPkg/PlatformInit: FV code

Dear developers, dear Jiewen,

I have been investigating the devel-MinPlatform branch of edk2-platforms for 
educational purposes and got two questions regarding the Firmware Volume code 
in PlatformInitPreMem, if you do not mind. I assume the tree was tested, so 
most likely I misunderstood some things.


  1.  Why is a Firmware Volume HOB built to cover the entire flash range 
(https://github.com/tianocore/edk2-platforms/blob/devel-MinPlatform/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c#L379)?
 Am I correct that this implies a FV spanning through the entire flash MMIO 
range, which would then imply all other FVs are contained within it? This would 
make sense, however that's not what I saw in the KabylakeOpenBoardPkg Flash 
Map, which has the NV Storage first 
(https://github.com/tianocore/edk2-platforms/blob/devel-MinPlatform/Platform/Intel/KabylakeOpenBoardPkg/Include/Fdf/FlashMapInclude.fdf#L25).

[Jiewen] You are right. We should not use FD region for FV. Will fix it.



  1.  Why are FV Info PPIs installed for the UefiBoot and the OsBoot FVs 
(https://github.com/tianocore/edk2-platforms/blob/devel-MinPlatform/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c#L344)?
 If I checked correctly, installing this PPI type will trigger PeiCore to 
dispatch PEIMs in the FVs, however there are only DXE drivers in these. Why are 
no FV HOBs installed, which are gotten by DxeCore?

[Jiewen] In DxeIpl, PeiServicesFfsFindNextVolume() is used to search DxeCore.
In PeiCore, PeiFfsFindNextVolume() calls FindNextCoreFvHandle() for DxeCore one 
by one. If PcdFrameworkCompatibilitySupport is FALSE, it returns 
>Fv[Instance] directly.

And Fv[Instance] is added in FirmwareVolmeInfoPpiNotifyCallback(), when 
gEfiPeiFirmwareVolumeInfo2PpiGuid is installed.

So if PcdFrameworkCompatibilitySupport is FALSE, install PPI is the only way to 
let PEI core discover DxeCore.
Only if PcdFrameworkCompatibilitySupport is TRUE, install PPI is not required, 
but the FindNextCoreFvHandle() will install the PPI for the HobFv. The result 
is same.


Thank you
Yao Jiewen




Thanks in advance for your time!

Best regards,
Marvin.
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Re: [edk2] [PATCH] MdePkg/SafeString: Directly return when length of source string is 0

[Laszlo Ersek]

On 02/02/18 11:47, Ruiyu Ni wrote:
> Today's implementation of [Ascii]StrnCpyS/[Ascii]StrnCatS doesn't
> directly return the the length of source string is 0.
> 
> When length of source string is 0, it means the Source points to
> a memory that shouldn't be deferenced at all.
> So it's not proper to call StrnLenS() in such situation.
> In a pool guard enabled environment, when using shell to edit an
> existing file which contains empty line, the page fault is met.
> 
> The patch fixes the four library functions to align to the behavior
> of non-safe version: directly return when length of source string
> is 0.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ruiyu Ni 
> Cc: Jiewen Yao 
> Cc: Liming Gao 
> Cc: Jian J Wang 
> ---
>  MdePkg/Library/BaseLib/SafeString.c | 18 +-
>  1 file changed, 17 insertions(+), 1 deletion(-)
> 
> diff --git a/MdePkg/Library/BaseLib/SafeString.c 
> b/MdePkg/Library/BaseLib/SafeString.c
> index 68c33e9b7b..fed818ef33 100644
> --- a/MdePkg/Library/BaseLib/SafeString.c
> +++ b/MdePkg/Library/BaseLib/SafeString.c
> @@ -1,7 +1,7 @@
>  /** @file
>Safe String functions.
>  
> -  Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
> +  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
>This program and the accompanying materials
>are licensed and made available under the terms and conditions of the BSD 
> License
>which accompanies this distribution.  The full text of the license may be 
> found at
> @@ -317,6 +317,10 @@ StrnCpyS (
>  {
>UINTNSourceLen;
>  
> +  if (Length == 0) {
> +return RETURN_SUCCESS;
> +  }
> +
>ASSERT (((UINTN) Destination & BIT0) == 0);
>ASSERT (((UINTN) Source & BIT0) == 0);
>  
> @@ -515,6 +519,10 @@ StrnCatS (
>UINTN   CopyLen;
>UINTN   SourceLen;
>  
> +  if (Length == 0) {
> +return RETURN_SUCCESS;
> +  }
> +
>ASSERT (((UINTN) Destination & BIT0) == 0);
>ASSERT (((UINTN) Source & BIT0) == 0);
>  
> @@ -1894,6 +1902,10 @@ AsciiStrnCpyS (
>  {
>UINTNSourceLen;
>  
> +  if (Length == 0) {
> +return RETURN_SUCCESS;
> +  }
> +
>//
>// 1. Neither Destination nor Source shall be a null pointer.
>//
> @@ -2082,6 +2094,10 @@ AsciiStrnCatS (
>UINTN   CopyLen;
>UINTN   SourceLen;
>  
> +  if (Length == 0) {
> +return RETURN_SUCCESS;
> +  }
> +
>//
>// Let CopyLen denote the value DestMax - AsciiStrnLenS(Destination, 
> DestMax) upon entry to AsciiStrnCatS.
>//
> 

Reviewed-by: Laszlo Ersek 
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Re: [edk2] [PATCH 1/3] UefiCpuPkg/PiSmmCpuDxeSmm: update comments in IA32 SmmStartup()

[Leif Lindholm]

On Fri, Feb 02, 2018 at 10:06:07AM +, Ard Biesheuvel wrote:
> On 31 January 2018 at 10:40, Laszlo Ersek  wrote:
> > On 01/30/18 23:25, Kinney, Michael D wrote:
> >> Laszlo,
> >>
> >> I agree that the function is better than a macro.
> >>
> >> I thought of the alignment issues as well.  CopyMem()
> >> is a good solution.  We could also consider
> >> WriteUnalignedxx() functions in BaseLib.
> >
> > IMO, the WriteUnalignedxx functions are a bit pointless in the exact
> > form they are declared (this was discussed earlier esp. with regard to
> > aarch64). The functions take pointers to objects that already have the
> > target type, such as
> >
> > UINT32
> > EFIAPI
> > WriteUnaligned32 (
> >   OUT UINT32*Buffer,
> >   IN  UINT32Value
> >   )
> >
> > Here the type of Buffer should be (VOID *), not (UINT32 *). Otherwise,
> > the undefined behavior (due to mis-alignment) surfaces as soon as the
> > function is called with an unaligned pointer (i.e. before the target
> > area is actually written).
> >
> >> I was originally thinking this functionality would go
> >> into BaseLib.  But with the use of CopyMem(), we can't
> >> do that.
> >
> > Can we put it in BaseMemoryLib instead (which is where CopyMem() is
> > from)? That library class is still low-level enough. And, while I count
> > 9 library instances, PatchAssembly() is not a large function, we could
> > tolerate adding it to all 9 instances, identically.
> >
> > Let me also ask the opposite question: should we perhaps make the
> > PatchAssembly() API *less* abstract? (Also suggested by your naming of
> > the macro, PATCH_X86_ASM.) If the instruction encoding on e.g. AARCH64
> > doesn't lend itself to such patching (= expressed through the address
> > right after the instruction), then even BaseMemoryLib may be too generic
> > for the API.
> >
> >> Maybe we should use WriteUnalignedxx() and
> >> add some ASSERT() checks.
> >>
> >> VOID
> >> PatchAssembly (
> >>   VOID*BufferEnd,
> >>   UINT64  PatchValue,
> >>   UINTN   ValueSize
> >>   )
> >> {
> >>   ASSERT ((UINTN)BufferEnd > ValueSize);
> >>   switch (ValueSize) {
> >>   case 1:
> >> ASSERT (PatchValue <= MAX_UINT8);
> >> *((UINT8 *)BufferEnd - 1) = (UINT8)PatchValue;
> >>   case 2:
> >> ASSERT (PatchValue <= MAX_UINT16);
> >> WriteUnaligned16 ((UINT16 *)(BufferEnd) - 1, (UINT16)PatchValue));
> >> break;
> >>   case 4:
> >> ASSERT (PatchValue <= MAX_UINT32);
> >> WriteUnaligned32 ((UINT32 *)(BufferEnd) - 1, (UINT32)PatchValue));
> >> break;
> >>   case 8:
> >> WriteUnaligned64 ((UINT64 *)(BufferEnd) - 1, PatchValue));
> >> break;
> >>   default:
> >> ASSERT (FALSE);
> >>   }
> >> }
> >
> > In my opinion:
> >
> > - If Ard and Leif say that PatchAssembly() API makes sense for AARCH64,
> >   then I think we can go with the above generic implementation (for
> >   BaseLib).
> >
> 
> Code patching on ARM/AARCH64 has some hoops to jump through, i.e.,
> clean the D-cache to the point of unification, invalidate the I-cache,
> probably some barriers in case the patching function happened to end
> up in the same cache line as the patchee

Not just the same cache line. Prefetching can happen whenever, for
whatever reason.

> (which may not be a concern
> for this specific use case, but it does need to be taken into account
> if this is turned into a patch-any-assembly-anywhere function)
> 
> So if the PatchAssembly() prototype does end up in a generic library
> class, we'd have to provide ARM and AARCH64 specific implementations
> anyway, and given that I don't see any use for this on ARM/AARCH64 in
> the first place, I think this should belong in an IA32/X64 specific
> package.

I also don't see a specific use for this on ARM* at the moment. But if
this is going to become more widespread, it would be useful to
introduce a higher-level layer with more portable semantics (I don't
know RISC-V, but could imagine they require similar).
However, at that point, we would probably want something
buffer-oriented rather than instruction-oriented, since we'd like to
keep the overhead down if writing more than one register's worth.

/
Leif
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[edk2] [PATCH edk2-platforms v3 02/15] Hisilicon/D05: Add PPTT support

[Heyi Guo]

Add Processor Properties Topology Table, PPTT include
Processor hierarchy node, Cache Type Structure and ID structure.

PPTT is needed for lscpu command to show socket information correctly.
https://bugs.linaro.org/show_bug.cgi?id=3206

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang 
Signed-off-by: Heyi Guo 
Reviewed-by: Ard Biesheuvel 
Reviewed-by: Graeme Gregory 
Reveiwed-by: Jeremy Linton 
---
 Platform/Hisilicon/D05/D05.dsc |   1 +
 Platform/Hisilicon/D05/D05.fdf |   1 +
 Silicon/Hisilicon/Hi1616/Pptt/Pptt.c   | 529 
 Silicon/Hisilicon/Hi1616/Pptt/Pptt.h   |  67 +++
 Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf |  48 ++
 5 files changed, 646 insertions(+)

diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
index 77a89fd..710339c 100644
--- a/Platform/Hisilicon/D05/D05.dsc
+++ b/Platform/Hisilicon/D05/D05.dsc
@@ -506,6 +506,7 @@
   MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
 
   Silicon/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
+  Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
   Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
 
   #
diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf
index 78ab0c8..97de4d2 100644
--- a/Platform/Hisilicon/D05/D05.fdf
+++ b/Platform/Hisilicon/D05/D05.fdf
@@ -241,6 +241,7 @@ READ_LOCK_STATUS   = TRUE
   INF Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
 
   INF RuleOverride=ACPITABLE 
Silicon/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
+  INF Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
   INF Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
 
   #
diff --git a/Silicon/Hisilicon/Hi1616/Pptt/Pptt.c 
b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.c
new file mode 100644
index 000..9ce2b32
--- /dev/null
+++ b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.c
@@ -0,0 +1,529 @@
+/** @file
+*
+*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2018, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD 
License
+*  which accompanies this distribution.  The full text of the license may be 
found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+*
+*  Based on the files under Platform/ARM/JunoPkg/AcpiTables/
+*
+**/
+
+#include "Pptt.h"
+
+EFI_ACPI_TABLE_PROTOCOL   *mAcpiTableProtocol = NULL;
+EFI_ACPI_SDT_PROTOCOL *mAcpiSdtProtocol   = NULL;
+
+EFI_ACPI_DESCRIPTION_HEADER mPpttHeader =
+  ARM_ACPI_HEADER (
+EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+EFI_ACPI_DESCRIPTION_HEADER,
+EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+  );
+
+EFI_ACPI_6_2_PPTT_STRUCTURE_ID mPpttSocketType2[PPTT_SOCKET_COMPONENT_NO] =
+{
+  {2, sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID), {0, 0}, PPTT_VENDOR_ID, 0, 0, 
0, 0, 0}
+};
+
+EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE mPpttCacheType1[PPTT_CACHE_NO];
+
+
+STATIC
+VOID
+InitCacheInfo (
+  VOID
+  )
+{
+  UINT8Index;
+  EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES Type1Attributes;
+  CSSELR_DATA  CsselrData;
+  CCSIDR_DATA  CcsidrData;
+
+  for (Index = 0; Index < PPTT_CACHE_NO; Index++) {
+CsselrData.Data = 0;
+CcsidrData.Data = 0;
+SetMem (
+  ,
+  sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES),
+  0
+  );
+
+if (Index == 0) { //L1I
+  CsselrData.Bits.InD = 1;
+  CsselrData.Bits.Level = 0;
+  Type1Attributes.CacheType  = 1;
+} else if (Index == 1) {
+  Type1Attributes.CacheType  = 0;
+  CsselrData.Bits.Level = Index - 1;
+} else {
+  Type1Attributes.CacheType  = 2;
+  CsselrData.Bits.Level = Index - 1;
+}
+
+CcsidrData.Data = ReadCCSIDR (CsselrData.Data);
+
+if (CcsidrData.Bits.Wa == 1) {
+  Type1Attributes.AllocationType = 
EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_WRITE;
+  if (CcsidrData.Bits.Ra == 1) {
+Type1Attributes.AllocationType = 
EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE;
+  }
+}
+
+if (CcsidrData.Bits.Wt == 1) {
+  Type1Attributes.WritePolicy = 1;
+}
+DEBUG ((DEBUG_INFO,
+"[Acpi PPTT] Level = %x!CcsidrData = %x!\n",
+CsselrData.Bits.Level,
+CcsidrData.Data));
+
+mPpttCacheType1[Index].Type = EFI_ACPI_6_2_PPTT_TYPE_CACHE;
+mPpttCacheType1[Index].Length = sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE);
+mPpttCacheType1[Index].Reserved[0] = 0;
+mPpttCacheType1[Index].Reserved[1] = 0;
+

[edk2] [PATCH edk2-platforms v3 03/15] Hisilicon/D0x/BDS: Switch to Generic BDS driver

[Heyi Guo]

Hisilicon-specific PlatformBootManagerLib added. It is convenient
to add specific feature, like BMC control boot option.
Remove Intel BDS from dsc file because it is out of use.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang 
Signed-off-by: Heyi Guo 
Signed-off-by: Jason Zhang 
Reviewed-by: Leif Lindholm 
Reviewed-by: Ard Biesheuvel 
---
 Platform/Hisilicon/D03/D03.dsc  |  
17 +-
 Platform/Hisilicon/D03/D03.fdf  |  
 3 +-
 Platform/Hisilicon/D05/D05.dsc  |  
17 +-
 Platform/Hisilicon/D05/D05.fdf  |  
 3 +-
 Silicon/Hisilicon/HisiPkg.dec   |  
 2 +
 Silicon/Hisilicon/Hisilicon.dsc.inc |  
 1 +
 Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c   | 
636 
 Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.h   |  
31 +
 Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf |  
73 +++
 9 files changed, 777 insertions(+), 6 deletions(-)

diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc
index b434f68..5fbe1f9 100644
--- a/Platform/Hisilicon/D03/D03.dsc
+++ b/Platform/Hisilicon/D03/D03.dsc
@@ -68,6 +68,13 @@
   CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
   GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
   
PlatformBdsLib|Silicon/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf
+  
UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+  BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
+  SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+  
ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+  
PlatformBootManagerLib|Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+  FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
   
CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
 
   # USB Requirements
@@ -187,7 +194,7 @@
 
 
   gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
-  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 
0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
+  gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 
0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 
}|VOID*|0x0001006b
 
   gHisiTokenSpaceGuid.PcdSysControlBaseAddress|0x4001
   gHisiTokenSpaceGuid.PcdMailBoxAddress|0xFFF8
@@ -405,6 +412,12 @@
   MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
   MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
 
+  MdeModulePkg/Application/UiApp/UiApp.inf {
+
+  NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
+  NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
+  
NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
+  }
   MdeModulePkg/Application/HelloWorld/HelloWorld.inf
   #
   # Bds
@@ -457,7 +470,7 @@
 
   MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
   MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
-  IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
+  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
 
   #
   # UEFI application (Shell Embedded Boot Loader)
diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf
index 0b38eb4..474f37f 100644
--- a/Platform/Hisilicon/D03/D03.fdf
+++ b/Platform/Hisilicon/D03/D03.fdf
@@ -283,6 +283,7 @@ READ_LOCK_STATUS   = TRUE
   INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
 !endif #$(INCLUDE_TFTP_COMMAND)
 
+  INF MdeModulePkg/Application/UiApp/UiApp.inf
   #
   # Bds
   #
@@ -291,7 +292,7 @@ READ_LOCK_STATUS   = TRUE
   INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
   INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
   INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
-  INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
+  INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
 
 [FV.FVMAIN_COMPACT]
 FvAlignment= 16
diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
index 710339c..4d630da 100644
--- a/Platform/Hisilicon/D05/D05.dsc
+++ b/Platform/Hisilicon/D05/D05.dsc
@@ -84,6 +84,12 @@
   CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
   

[edk2] [PATCH edk2-platforms v3 05/15] Hisilicon D03/D05: Add capsule upgrade support

[Heyi Guo]

This module support updating the boot CPU firmware only.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jason Zhang 
Signed-off-by: Ming Huang 
Signed-off-by: Heyi Guo 
Reviewed-by: Ard Biesheuvel 
---
 
Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
 |  45 +++
 Platform/Hisilicon/D03/D03.dsc 
  |  17 ++-
 Platform/Hisilicon/D03/D03.fdf 
  |  70 +++
 
Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
|  81 +
 
Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
 |  50 
 
Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c
|  70 +++
 
Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
 |  45 +++
 Platform/Hisilicon/D05/D05.dsc 
  |  19 ++-
 Platform/Hisilicon/D05/D05.fdf 
  |  70 +++
 
Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
|  81 +
 
Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
 |  50 
 
Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c
|  70 +++
 Silicon/Hisilicon/Hisilicon.dsc.inc
  |  11 +-
 Silicon/Hisilicon/Hisilicon.fdf.inc
  |   9 ++
 Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c   
  | 123 
 Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf 
  |  51 
 16 files changed, 859 insertions(+), 3 deletions(-)

diff --git 
a/Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
 
b/Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
new file mode 100644
index 000..fc834d9
--- /dev/null
+++ 
b/Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
@@ -0,0 +1,45 @@
+#
+#  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+#  Copyright (c) 2018, Linaro Limited. All rights reserved.
+#  Copyright (c) 2016, Intel Corporation. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD 
License
+#  which accompanies this distribution.  The full text of the license may be 
found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+#
+##
+
+[Head]
+NumOfUpdate = 3
+NumOfRecovery = 0
+Update0 = SysFvMain
+Update1 = SysCustom
+Update2 = SysNvRam
+
+[SysFvMain]
+FirmwareType  = 0 # 0 - SystemFirmware, 1 - NvRam
+AddressType   = 0 # 0 - relative address, 1 - absolute address.
+BaseAddress   = 0x# Base address offset on flash
+Length= 0x002D# Length
+ImageOffset   = 0x# Image offset of this SystemFirmware image
+FileGuid  = 642e4fcf-2df7-4415-8b70-a03909c57b55  # 
PcdEdkiiSystemFirmwareFileGuid
+
+[SysCustom]
+FirmwareType  = 0 # 0 - SystemFirmware, 1 - NvRam
+AddressType   = 0 # 0 - relative address, 1 - absolute address.
+BaseAddress   = 0x002F# Base address offset on flash
+Length= 0x0001# Length
+ImageOffset   = 0x002F# Image offset of this SystemFirmware image
+FileGuid  = 642e4fcf-2df7-4415-8b70-a03909c57b55  # 
PcdEdkiiSystemFirmwareFileGuid
+
+[SysNvRam]
+FirmwareType  = 1 # 0 - SystemFirmware, 1 - NvRam
+AddressType   = 0 # 0 - relative address, 1 - absolute address.
+BaseAddress   = 0x002D# Base address offset on flash
+Length= 0x0002# Length
+ImageOffset   = 0x002D# Image offset of this SystemFirmware image
+FileGuid  = 642e4fcf-2df7-4415-8b70-a03909c57b55  # 
PcdEdkiiSystemFirmwareFileGuid
diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc
index e1e3b14..82c8bb4 100644
--- a/Platform/Hisilicon/D03/D03.dsc
+++ b/Platform/Hisilicon/D03/D03.dsc
@@ -65,7 +65,6 @@
   
OemAddressMapLib|Platform/Hisilicon/D03/Library/OemAddressMap2P/OemAddressMap2PHi1610.inf
   
PlatformSysCtrlLib|Silicon/Hisilicon/Hi1610/Library/PlatformSysCtrlLibHi1610/PlatformSysCtrlLibHi1610.inf
 
-  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
   

[edk2] [PATCH edk2-platforms v3 15/15] Hisilicon D03/D05: Update firmware version to 18.02

[Heyi Guo]

Replace the old string with short one. The old one is
too long that can not be show integrallty in Setup nemu.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang 
Signed-off-by: Heyi Guo 
Reviewed-by: Leif Lindholm 
Reviewed-by: Ard Biesheuvel 
Reviewed-by: Graeme Gregory 
---
 Platform/Hisilicon/D03/D03.dsc | 2 +-
 Platform/Hisilicon/D05/D05.dsc | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc
index 37bec9e..c496306 100644
--- a/Platform/Hisilicon/D03/D03.dsc
+++ b/Platform/Hisilicon/D03/D03.dsc
@@ -168,7 +168,7 @@
   !ifdef $(FIRMWARE_VER)
 gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)"
   !else
-gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Development 
build base on Hisilicon D03 UEFI 17.10 Release"
+gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Development 
build 18.02 for Hisilicon D03"
   !endif
 
   gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18"
diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
index b2ccd0e..0792b08 100644
--- a/Platform/Hisilicon/D05/D05.dsc
+++ b/Platform/Hisilicon/D05/D05.dsc
@@ -187,7 +187,7 @@
   !ifdef $(FIRMWARE_VER)
 gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)"
   !else
-gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Development 
build base on Hisilicon D05 UEFI 17.10 Release"
+gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Development 
build 18.02 for Hisilicon D05"
   !endif
 
   gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18"
-- 
1.9.1

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[edk2] [PATCH edk2-platforms v3 13/15] Hisilicon/D05/ACPI: Add ITS PXM

[Heyi Guo]

Add ITS affinity structure in SRAT.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang 
Signed-off-by: Heyi Guo 
Reviewed-by: Ard Biesheuvel 
Reviewed-by: Graeme Gregory 
---
 Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc | 10 ++
 Silicon/Hisilicon/Include/Library/AcpiNextLib.h | 10 +-
 2 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc 
b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc
index b448a29..8ea0c4b 100644
--- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc
+++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc
@@ -121,6 +121,16 @@ EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE Srat = {
 
EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x0003,0x003E,0x0001,0x),
   //GICC Affinity Processor 62
 
EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x0003,0x003F,0x0001,0x)
//GICC Affinity Processor 63
   },
+  {
+EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x, 0x),
+EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x0001, 0x0001),
+EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x, 0x0002),
+EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x0001, 0x0003),
+EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x0002, 0x0004),
+EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x0003, 0x0005),
+EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x0002, 0x0006),
+EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x0003, 0x0007)
+  },
 };
 
 //
diff --git a/Silicon/Hisilicon/Include/Library/AcpiNextLib.h 
b/Silicon/Hisilicon/Include/Library/AcpiNextLib.h
index 60f9925..fd05a3b 100644
--- a/Silicon/Hisilicon/Include/Library/AcpiNextLib.h
+++ b/Silicon/Hisilicon/Include/Library/AcpiNextLib.h
@@ -39,6 +39,13 @@
  ACPIProcessorUID,  Flags,  ClockDomain
 \
   }
 
+#define EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(  
 \
+ProximityDomain, ItsId)
 \
+  {
 \
+4, sizeof (EFI_ACPI_6_2_GIC_ITS_AFFINITY_STRUCTURE), ProximityDomain,  
 \
+{EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, ItsId
   \
+  }
+
 #define EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(   
   \
 ProximityDomain, AddressBaseLow, AddressBaseHigh, LengthLow, LengthHigh, 
Flags)   \
   {
   \
@@ -70,12 +77,13 @@
 //
 #define EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT  64
 #define EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT10
-
+#define EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT   8
 
 typedef struct {
   EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER  Header;
   EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE  
Memory[EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT];
   EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE
Gicc[EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT];
+  EFI_ACPI_6_2_GIC_ITS_AFFINITY_STRUCTURE 
Its[EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT];
 } EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE;
 
 #pragma pack()
-- 
1.9.1

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[edk2] [PATCH edk2-platforms v3 11/15] Hisilicon/D05: Replace SP805Watchdog by WatchdogTimer driver.

[Heyi Guo]

In SCT test,we find SP805 watchdog driver can't reset when timeout
so we use another driver in MdeModulePkg.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang 
Signed-off-by: Heyi Guo 
Signed-off-by: GongChengYa 
Reviewed-by: Leif Lindholm 
Reviewed-by: Ard Biesheuvel 
---
 Platform/Hisilicon/D05/D05.dsc | 2 +-
 Platform/Hisilicon/D05/D05.fdf | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
index dfe19b0..b2ccd0e 100644
--- a/Platform/Hisilicon/D05/D05.dsc
+++ b/Platform/Hisilicon/D05/D05.dsc
@@ -511,7 +511,7 @@
 
   ArmPkg/Drivers/TimerDxe/TimerDxe.inf
 
-  ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
+  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
   
IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf
   #
   #ACPI
diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf
index e829494..22609bb 100644
--- a/Platform/Hisilicon/D05/D05.fdf
+++ b/Platform/Hisilicon/D05/D05.fdf
@@ -193,7 +193,7 @@ READ_LOCK_STATUS   = TRUE
   INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
   INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
 
-  INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
+  INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
 
   #
   # FAT filesystem + GPT/MBR partitioning
-- 
1.9.1

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[edk2] [PATCH edk2-platforms v3 04/15] Hisilicon/D0x: Break BMC SetBoot option out into separate library

[Heyi Guo]

Modify the feature of BMC set boot option as switching generic
BDS. Break BMC SetBoot option out into BmcConfigBootLib.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang 
Signed-off-by: Heyi Guo 
Reviewed-by: Leif Lindholm 
Reviewed-by: Ard Biesheuvel 
---
 Platform/Hisilicon/D03/D03.dsc  |  
 1 +
 Platform/Hisilicon/D05/D05.dsc  |  
 1 +
 Silicon/Hisilicon/HisiPkg.dec   |  
 1 +
 Silicon/Hisilicon/Include/Library/BmcConfigBootLib.h|  
31 ++
 Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.c   | 
466 
 Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf |  
51 +++
 Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c   |  
 7 +
 Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf |  
 1 +
 8 files changed, 559 insertions(+)

diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc
index 5fbe1f9..e1e3b14 100644
--- a/Platform/Hisilicon/D03/D03.dsc
+++ b/Platform/Hisilicon/D03/D03.dsc
@@ -68,6 +68,7 @@
   CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
   GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
   
PlatformBdsLib|Silicon/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf
+  
BmcConfigBootLib|Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf
   
UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
   BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
   SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
index 4d630da..ac7da04 100644
--- a/Platform/Hisilicon/D05/D05.dsc
+++ b/Platform/Hisilicon/D05/D05.dsc
@@ -84,6 +84,7 @@
   CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
   GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
   
PlatformBdsLib|Silicon/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf
+  
BmcConfigBootLib|Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf
   
UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
   SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
   
ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
diff --git a/Silicon/Hisilicon/HisiPkg.dec b/Silicon/Hisilicon/HisiPkg.dec
index 398d0a7..889a181 100644
--- a/Silicon/Hisilicon/HisiPkg.dec
+++ b/Silicon/Hisilicon/HisiPkg.dec
@@ -43,6 +43,7 @@
 
   gHisiEfiMemoryMapGuid  = {0xf8870015, 0x6994, 0x4b98, {0x95, 0xa2, 0xbd, 
0x56, 0xda, 0x91, 0xc0, 0x7f}}
   gVersionInfoHobGuid = {0xe13a14c, 0x859c, 0x4f22, {0x82, 0xbd, 0x18, 0xe, 
0xe1, 0x42, 0x12, 0xbf}}
+  gOemBootVariableGuid = {0xb7784577, 0x5aaf, 0x4557, {0xa1, 0x99, 0xd4, 0xa4, 
0x2f, 0x45, 0x06, 0xf8}}
 
 [LibraryClasses]
   PlatformSysCtrlLib|Include/Library/PlatformSysCtrlLib.h
diff --git a/Silicon/Hisilicon/Include/Library/BmcConfigBootLib.h 
b/Silicon/Hisilicon/Include/Library/BmcConfigBootLib.h
new file mode 100644
index 000..d937234
--- /dev/null
+++ b/Silicon/Hisilicon/Include/Library/BmcConfigBootLib.h
@@ -0,0 +1,31 @@
+/** @file
+*
+*  Copyright (c) 2017, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2017, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD 
License
+*  which accompanies this distribution.  The full text of the license may be 
found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+*
+**/
+
+#ifndef _BMC_CONFIG_BOOT_LIB_H_
+#define _BMC_CONFIG_BOOT_LIB_H_
+
+VOID
+EFIAPI
+RestoreBootOrder (
+  VOID
+  );
+
+VOID
+EFIAPI
+HandleBmcBootType (
+  VOID
+  );
+
+#endif
diff --git a/Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.c 
b/Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.c
new file mode 100644
index 000..08a9c9c
--- /dev/null
+++ b/Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.c
@@ -0,0 +1,466 @@
+/** @file
+*
+*  Copyright (c) 2017, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2017, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD 
License
+*  which accompanies this distribution.  The full text of the license may be 
found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER 

[edk2] [PATCH edk2-platforms v3 09/15] Hisilicon/Smbios: Indicate use of ProcessorFamily2 in type 4 table

[Heyi Guo]

modify processorFamily of type 4 to ProcessorFamilyIndicatorFamily2,
indicator to obtain the processor family from the Processor Family 2 field.
ProcessorFamily2 is already specified as ProcessorFamilyARM in the existing
table.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang 
Signed-off-by: Heyi Guo 
Reviewed-by: Leif Lindholm 
Reviewed-by: Ard Biesheuvel 
---
 Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c | 4 
++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git 
a/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c 
b/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c
index 61473e8..c9903ba 100644
--- a/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c
+++ b/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c
@@ -125,7 +125,7 @@ SMBIOS_TABLE_TYPE4   mSmbiosProcessorTable[] = {
 },
 1,  //Socket
 CentralProcessor,   //ProcessorType
-ProcessorFamilyOther,   //ProcessorFamily
+ProcessorFamilyIndicatorFamily2,//ProcessorFamily
 2,  //ProcessorManufacture
 {   //ProcessorId
 {   //Signature
@@ -172,7 +172,7 @@ SMBIOS_TABLE_TYPE4   mSmbiosProcessorTable[] = {
 },
 1,  //Socket
 CentralProcessor,   //ProcessorType
-ProcessorFamilyOther,   //ProcessorFamily
+ProcessorFamilyIndicatorFamily2,//ProcessorFamily
 2,  //ProcessorManufacture
 {   //ProcessorId
 {   //Signature
-- 
1.9.1

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[edk2] [PATCH edk2-platforms v3 10/15] Hisilicon/PCIe: Disable PCIe ASPM

[Heyi Guo]

In order to replace command line parameter pcie_aspm=off, BIOS needs to
disable Pcie Aspm support during Pcie initilization.
D03 and D05 do not support PCIe ASPM, so we disable it in BIOS.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang 
Signed-off-by: Heyi Guo 
Signed-off-by: Yan Zhang 
Reviewed-by: Leif Lindholm 
Reviewed-by: Ard Biesheuvel 
---
 Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 103 

 Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h |   2 +
 Silicon/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h|   2 +
 3 files changed, 107 insertions(+)

diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c 
b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
index f420c91..c1c3fbb 100644
--- a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
+++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
@@ -1033,6 +1033,106 @@ DisableRcOptionRom (
   return;
 }
 
+STATIC
+VOID
+PcieDbiCs2Enable (
+  IN UINT32 HostBridgeNum,
+  IN UINT32 Port,
+  IN BOOLEAN Val
+  )
+{
+  UINT32 RegVal;
+
+  RegRead (
+PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 
PCIE_SUBCTRL_SC_PCIE_SYS_CTRL21,
+RegVal
+);
+  if (Val) {
+RegVal = RegVal | BIT2;
+/* BIT2: DBI Chip Select indicator. 0 indicates CS, 1 indicates CS2.*/
+  } else {
+RegVal = RegVal & (~BIT2);
+  }
+  RegWrite (
+PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 
PCIE_SUBCTRL_SC_PCIE_SYS_CTRL21,
+RegVal
+);
+}
+
+STATIC
+BOOLEAN
+PcieDBIReadOnlyWriteEnable (
+  IN UINT32 HostBridgeNum,
+  IN UINT32 Port
+  )
+{
+  UINT32  Val;
+
+  RegRead (
+PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 
PCIE_DBI_READ_ONLY_WRITE_ENABLE,
+Val
+);
+  if (Val == 0x1) {
+return TRUE;
+  } else {
+RegWrite (
+  PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 
PCIE_DBI_READ_ONLY_WRITE_ENABLE,
+  0x1
+  );
+/* Delay 10us to make sure the PCIE device have enouph time to response. */
+MicroSecondDelay(10);
+RegRead (
+  PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 
PCIE_DBI_READ_ONLY_WRITE_ENABLE,
+  Val
+  );
+if (Val == 0x1) {
+  return TRUE;
+}
+  }
+  DEBUG ((DEBUG_ERROR,"PcieDBIReadOnlyWriteEnable Fail!!!\n"));
+  return FALSE;
+}
+
+STATIC
+VOID
+SwitchPcieASPMSupport (
+  IN UINT32 HostBridgeNum,
+  IN UINT32 Port,
+  IN UINT8 Val
+  )
+{
+  PCIE_EP_PCIE_CAP3_U PcieCap3;
+
+  if (Port >= PCIE_MAX_ROOTBRIDGE) {
+DEBUG ((DEBUG_ERROR, "Port is not valid\n"));
+return;
+  }
+  if (!PcieDBIReadOnlyWriteEnable (HostBridgeNum, Port)) {
+DEBUG ((DEBUG_INFO, "PcieDBI ReadOnly Reg do not Enable!!!\n"));
+return;
+  }
+  PcieDbiCs2Enable (HostBridgeNum, Port, FALSE);
+
+  RegRead (
+PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_EP_PCIE_CAP3_REG,
+PcieCap3.UInt32
+);
+  PcieCap3.Bits.active_state_power_management = Val;
+  RegWrite (
+PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_EP_PCIE_CAP3_REG,
+PcieCap3.UInt32
+);
+  RegRead (
+PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_EP_PCIE_CAP3_REG,
+PcieCap3.UInt32
+);
+  DEBUG ((DEBUG_INFO,
+  "ASPI active state power management: %d\n",
+  PcieCap3.Bits.active_state_power_management));
+
+  PcieDbiCs2Enable (HostBridgeNum, Port, TRUE);
+}
+
 EFI_STATUS
 EFIAPI
 PciePortInit (
@@ -1090,6 +1190,9 @@ PciePortInit (
  /* disable link up interrupt */
  (VOID)PcieMaskLinkUpInit(soctype, HostBridgeNum, PortIndex);
 
+ /* disable ASPM */
+ SwitchPcieASPMSupport (HostBridgeNum, PortIndex, PCIE_ASPM_DISABLE);
+
  /* Pcie Equalization*/
  (VOID)PcieEqualization(soctype ,HostBridgeNum, PortIndex);
 
diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h 
b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h
index 9a0f636..e96c53c 100644
--- a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h
+++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h
@@ -77,6 +77,8 @@
 #define RegWrite(addr,data)MmioWrite32((addr), (data))
 #define RegRead(addr,data) ((data) = MmioRead32 (addr))
 
+#define PCIE_ASPM_DISABLE 0x0
+#define PCIE_ASPM_ENABLE 0x1
 
 typedef struct tagPcieDebugInfo
 {
diff --git a/Silicon/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h 
b/Silicon/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h
index bf57652..c8b9781 100644
--- a/Silicon/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h
+++ b/Silicon/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h
@@ -135,6 +135,7 @@
 #define PCIE_EEP_PORTLOGIC53_REG  (0x888)
 #define PCIE_EEP_GEN3_CONTRL_REG  (0x890)
 #define PCIE_EEP_PIPE_LOOPBACK_REG(0x8B8)
+#define PCIE_DBI_READ_ONLY_WRITE_ENABLE   (0x8BC)
 #define 

[edk2] [PATCH edk2-platforms v3 07/15] Hisilicon D03/D05: Open SnpPlatform source code

[Heyi Guo]

1. This driver install a protocol for SnpPV600Dxe driver.
   The protocol indicate which ethernet port to use and port sequence.
2. Fixed bug:Confusing Ethernet port sequence.
   Move the most right Ethernet port (when looking from the front
   of the chassis) to the first one in BootManage for PXE boot.
   https://bugs.linaro.org/show_bug.cgi?id=2657

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jason Zhang 
Signed-off-by: Ming Huang 
Signed-off-by: Heyi Guo 
Reviewed-by: Leif Lindholm 
Reviewed-by: Ard Biesheuvel 
---
 Platform/Hisilicon/D03/D03.dsc   |   2 +
 Platform/Hisilicon/D03/D03.fdf   |   2 +-
 Platform/Hisilicon/D05/D05.dsc   |   2 +
 Platform/Hisilicon/D05/D05.fdf   |   2 +-
 Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.c  | 115 

 Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf|  46 
 Silicon/Hisilicon/HisiPkg.dec|   1 +
 Silicon/Hisilicon/Include/Protocol/SnpPlatformProtocol.h |  32 ++
 8 files changed, 200 insertions(+), 2 deletions(-)

diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc
index 07da597..947a8a5 100644
--- a/Platform/Hisilicon/D03/D03.dsc
+++ b/Platform/Hisilicon/D03/D03.dsc
@@ -399,6 +399,8 @@
 
   Platform/Hisilicon/D03/Drivers/Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.inf
 
+  Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf
+
   MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
   MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
   MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf
index 919f9d7..1c55761 100644
--- a/Platform/Hisilicon/D03/D03.fdf
+++ b/Platform/Hisilicon/D03/D03.fdf
@@ -242,7 +242,7 @@ READ_LOCK_STATUS   = TRUE
   #Network
   #
 
-  INF Platform/Hisilicon/D03/Drivers/Net/SnpPlatform/SnpPlatform.inf
+  INF Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf
   INF Platform/Hisilicon/D03/Drivers/Net/SnpPV600Dxe/SnpPV600Dxe.inf
 
   INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
index b279c9e..6e44041 100644
--- a/Platform/Hisilicon/D05/D05.dsc
+++ b/Platform/Hisilicon/D05/D05.dsc
@@ -537,6 +537,8 @@
 
   Platform/Hisilicon/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf
 
+  Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf
+
   MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
   MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
   MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf
index b105ee2..e829494 100644
--- a/Platform/Hisilicon/D05/D05.fdf
+++ b/Platform/Hisilicon/D05/D05.fdf
@@ -248,7 +248,7 @@ READ_LOCK_STATUS   = TRUE
   #Network
   #
 
-  INF Platform/Hisilicon/D05/Drivers/Net/SnpPlatform/SnpPlatform.inf
+  INF Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf
   INF Platform/Hisilicon/D05/Drivers/Net/SnpPV600Dxe/SnpPV600Dxe.inf
 
   INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
diff --git a/Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.c 
b/Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.c
new file mode 100644
index 000..0d6e86e
--- /dev/null
+++ b/Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.c
@@ -0,0 +1,115 @@
+/** @file
+*
+*  Copyright (c) 2017, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2017, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD 
License
+*  which accompanies this distribution.  The full text of the license may be 
found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+*
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+typedef struct {
+  UINTN  Signature;
+  EFI_HANDLE Handle;
+  HISI_PLATFORM_SNP_PROTOCOL SnpPlatformProtocol;
+} SNP_PLATFORM_INSTANCE;
+
+STATIC HISI_PLATFORM_SNP_PROTOCOL mSnpPlatformProtocol[] = {
+  {
+4,
+1
+  },
+  {
+5,
+1
+  },
+  {
+2,
+0
+  },
+  {
+3,
+0
+  },
+  {
+0,
+1
+  },
+ {
+1,
+1
+  },
+  {
+6,
+0
+  },
+  {
+7,
+0
+  }
+};
+
+
+EFI_STATUS
+EFIAPI
+SnpPlatformInitialize (
+  IN EFI_HANDLE ImageHandle,
+  IN EFI_SYSTEM_TABLE   *SystemTable
+  )
+{
+  UINTNLoop;
+  SNP_PLATFORM_INSTANCE*PrivateData;
+  EFI_STATUS   Status;
+
+  for (Loop = 0; Loop < 

[edk2] [PATCH edk2-platforms v3 06/15] Hisilicon D03/D05: Open SasPlatform source code

[Heyi Guo]

This module install a protocol for SasDriverDxe. the protocol
include main information of sas controller, like controller ID,
enable or disable,base address of registers.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jason Zhang 
Signed-off-by: Ming Huang 
Signed-off-by: Heyi Guo 
Reviewed-by: Leif Lindholm 
Reviewed-by: Ard Biesheuvel 
---
 Platform/Hisilicon/D03/D03.dsc   |   1 +
 Platform/Hisilicon/D03/D03.fdf   |   2 +-
 Platform/Hisilicon/D05/D05.dsc   |   1 +
 Platform/Hisilicon/D05/D05.fdf   |   2 +-
 Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.c  | 106 

 Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf|  45 +
 Silicon/Hisilicon/HisiPkg.dec|   2 +
 Silicon/Hisilicon/Include/Library/OemDevicePath.h|  52 ++
 Silicon/Hisilicon/Include/Protocol/HisiPlatformSasProtocol.h |  30 ++
 9 files changed, 239 insertions(+), 2 deletions(-)

diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc
index 82c8bb4..07da597 100644
--- a/Platform/Hisilicon/D03/D03.dsc
+++ b/Platform/Hisilicon/D03/D03.dsc
@@ -468,6 +468,7 @@
   Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf
   Platform/Hisilicon/D03/Drivers/Sm750Dxe/UefiSmi.inf
 
+  Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf
   Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf
 
 
diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf
index 6462a53..919f9d7 100644
--- a/Platform/Hisilicon/D03/D03.fdf
+++ b/Platform/Hisilicon/D03/D03.fdf
@@ -272,7 +272,7 @@ READ_LOCK_STATUS   = TRUE
   #
   INF Platform/Hisilicon/D03/Drivers/Sm750Dxe/UefiSmi.inf
 
-  INF Platform/Hisilicon/D03/Drivers/SasPlatform/SasPlatform.inf
+  INF Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf
   INF Platform/Hisilicon/D03/Drivers/Sas/SasDxeDriver.inf
 
   INF 
SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf
diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
index e39acb1..b279c9e 100644
--- a/Platform/Hisilicon/D05/D05.dsc
+++ b/Platform/Hisilicon/D05/D05.dsc
@@ -621,6 +621,7 @@
   
Platform/Hisilicon/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf
   Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf
   Platform/Hisilicon/D05/Drivers/Sm750Dxe/UefiSmi.inf
+  Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf
   MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
   Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf
 
diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf
index b0296e1..b105ee2 100644
--- a/Platform/Hisilicon/D05/D05.fdf
+++ b/Platform/Hisilicon/D05/D05.fdf
@@ -294,7 +294,7 @@ READ_LOCK_STATUS   = TRUE
   #
   INF Platform/Hisilicon/D05/Drivers/Sm750Dxe/UefiSmi.inf
   INF  MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
-  INF Platform/Hisilicon/D05/Drivers/SasPlatform/SasPlatform.inf
+  INF Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf
   INF Platform/Hisilicon/D05/Drivers/Sas/SasDxeDriver.inf
 
   INF 
SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf
diff --git a/Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.c 
b/Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.c
new file mode 100644
index 000..7ae1f5d
--- /dev/null
+++ b/Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.c
@@ -0,0 +1,106 @@
+/** @file
+*
+*  Copyright (c) 2017, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2017, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD 
License
+*  which accompanies this distribution.  The full text of the license may be 
found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+*
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#define SAS0BusAddr 0xc300
+#define SAS1BusAddr 0xa200
+#define SAS2BusAddr 0xa300
+
+#define SAS0ResetAddr 0xc000
+#define SAS1ResetAddr 0xa000
+#define SAS2ResetAddr 0xa000
+
+typedef struct {
+  UINTN   Signature;
+  EFI_HANDLE  Handle;
+  HISI_PLATFORM_SAS_PROTOCOL  SasPlatformProtocol;
+} SAS_PLATFORM_INSTANCE;
+
+
+STATIC HISI_PLATFORM_SAS_PROTOCOL mSasPlatformProtocol[] = {
+  {
+0,
+FALSE,
+SAS0BusAddr,
+SAS0ResetAddr
+  },
+  {
+1,
+TRUE,
+SAS1BusAddr,
+

[edk2] [PATCH edk2-platforms v3 12/15] Hisilicon/D03: Replace SP805Watchdog by WatchdogTimer driver.

[Heyi Guo]

In SCT test,we find SP805 watchdog driver can't reset when timeout
so we use another driver in MdeModulePkg.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang 
Signed-off-by: Heyi Guo 
Signed-off-by: GongChengYa 
Reviewed-by: Leif Lindholm 
Reviewed-by: Ard Biesheuvel 
---
 Platform/Hisilicon/D03/D03.dsc | 2 +-
 Platform/Hisilicon/D03/D03.fdf | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc
index 947a8a5..37bec9e 100644
--- a/Platform/Hisilicon/D03/D03.dsc
+++ b/Platform/Hisilicon/D03/D03.dsc
@@ -374,7 +374,7 @@
 
   ArmPkg/Drivers/TimerDxe/TimerDxe.inf
 
-  ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
+  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
   
IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf
   #
   #ACPI
diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf
index 1c55761..e6a4820 100644
--- a/Platform/Hisilicon/D03/D03.fdf
+++ b/Platform/Hisilicon/D03/D03.fdf
@@ -189,7 +189,7 @@ READ_LOCK_STATUS   = TRUE
   INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
   INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
 
-  INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
+  INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
 
   #
   # FAT filesystem + GPT/MBR partitioning
-- 
1.9.1

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[edk2] [PATCH edk2-platforms v3 08/15] Hilisicon: Change DmaLib to CoherentDmaLib

[Heyi Guo]

Unify all D0x(include D06 in further) to cache coherent DmaLib.
This can improve boot speed.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wang Yue 
Signed-off-by: Ming Huang 
Signed-off-by: Heyi Guo 
Reviewed-by: Leif Lindholm 
Reviewed-by: Ard Biesheuvel 
---
 Platform/Hisilicon/D05/D05.dsc| 2 +-
 Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.c | 2 +-
 Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.c| 3 +--
 3 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
index 6e44041..dfe19b0 100644
--- a/Platform/Hisilicon/D05/D05.dsc
+++ b/Platform/Hisilicon/D05/D05.dsc
@@ -614,7 +614,7 @@
   Platform/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf
   Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf {
 
-  DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf
+  DmaLib|EmbeddedPkg/Library/CoherentDmaLib/CoherentDmaLib.inf
   NULL|Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf
   }
 
diff --git a/Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.c 
b/Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.c
index 706eb12..63de50b 100644
--- a/Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.c
+++ b/Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.c
@@ -26,7 +26,7 @@ EhciVirtualPciIoInitialize (
 {
   return RegisterNonDiscoverableMmioDevice (
NonDiscoverableDeviceTypeEhci,
-   NonDiscoverableDeviceDmaTypeNonCoherent,
+   NonDiscoverableDeviceDmaTypeCoherent,
NULL,
NULL,
1,
diff --git a/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.c 
b/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.c
index 2310ee4..3e272f8 100644
--- a/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.c
+++ b/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.c
@@ -27,7 +27,6 @@ ExitBootServicesEventSmmu (
   IN VOID   *Context
   )
 {
-  SmmuConfigForOS ();
   DEBUG((EFI_D_INFO,"SMMU ExitBootServicesEvent\n"));
 }
 
@@ -43,7 +42,7 @@ IoInitDxeEntry (
 
   (VOID) EfiSerdesInitWrap ();
 
-  SmmuConfigForBios ();
+  SmmuConfigForOS ();
 
   Status = gBS->CreateEvent (
   EVT_SIGNAL_EXIT_BOOT_SERVICES,
-- 
1.9.1

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[edk2] [PATCH edk2-platforms v3 14/15] Hisilicon/D05/ACPI: Add Pcie, HNS and SAS PXM

[Heyi Guo]

Add PXM method for Pcie device, HNS device and SAS device.
Add STA method for HNS.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: hensonwang 
Signed-off-by: Ming Huang 
Signed-off-by: Heyi Guo 
Reviewed-by: Ard Biesheuvel 
Reviewed-by: Graeme Gregory 
---
 Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl |  9 ++
 Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 34 
++--
 Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl | 19 +--
 3 files changed, 57 insertions(+), 5 deletions(-)

diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl 
b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl
index 11c28ba..7aa04af 100644
--- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl
+++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl
@@ -233,6 +233,15 @@ Scope(_SB)
   }
 })
 
+Method (_PXM, 0, NotSerialized)
+{
+  Return(0x00)
+}
+Method (_STA, 0, NotSerialized)
+{
+  Return(0x0F)
+}
+
 //reset XGE port
 //Arg0 : XGE port index in dsaf
 //Arg1 : 0 reset, 1 cancle reset
diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl 
b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl
index 55c7f50..122e4f0 100644
--- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl
+++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl
@@ -141,7 +141,10 @@ Scope(_SB)
 {
   Return (0xf)
 }
-
+Method (_PXM, 0, NotSerialized)
+{
+  Return(0x00)
+}
   } // Device(PCI2)
 
   Device (RES2)
@@ -240,7 +243,10 @@ Scope(_SB)
 {
   Return (RBYV())
 }
-
+Method (_PXM, 0, NotSerialized)
+{
+  Return(0x01)
+}
   } // Device(PCI4)
   Device (RES4)
   {
@@ -338,6 +344,10 @@ Scope(_SB)
 {
   Return (RBYV())
 }
+Method (_PXM, 0, NotSerialized)
+{
+  Return(0x01)
+}
   } // Device(PCI5)
   Device (RES5)
   {
@@ -435,6 +445,10 @@ Scope(_SB)
 {
   Return (RBYV())
 }
+Method (_PXM, 0, NotSerialized)
+{
+  Return(0x01)
+}
   } // Device(PCI6)
   Device (RES6)
   {
@@ -531,6 +545,10 @@ Scope(_SB)
 {
   Return (RBYV())
 }
+Method (_PXM, 0, NotSerialized)
+{
+  Return(0x01)
+}
   } // Device(PCI7)
   Device (RES7)
   {
@@ -690,6 +708,10 @@ Scope(_SB)
 {
   Return (0xf)
 }
+Method (_PXM, 0, NotSerialized)
+{
+  Return(0x02)
+}
   } // Device(PCIa)
   Device (RESa)
   {
@@ -810,6 +832,10 @@ Scope(_SB)
 {
   Return (RBYV())
 }
+Method (_PXM, 0, NotSerialized)
+{
+  Return(0x03)
+}
   } // Device(PCIc)
 
   Device (RESc)
@@ -907,6 +933,10 @@ Scope(_SB)
 {
   Return (RBYV())
 }
+Method (_PXM, 0, NotSerialized)
+{
+  Return(0x03)
+}
   } // Device(PCId)
   Device (RESd)
   {
diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl 
b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl
index 6455130..d5b7e2f 100644
--- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl
+++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl
@@ -88,7 +88,10 @@ Scope(_SB)
   Store(0x7, CLK)
   Sleep(1)
 }
-
+Method (_PXM, 0, NotSerialized)
+{
+  Return(0x00)
+}
Method (_STA, 0, NotSerialized)
{
  Return (0x0)
@@ -169,8 +172,15 @@ Scope(_SB)
   Store(0x7, CLK)
   Sleep(1)
 }
+Method (_PXM, 0, NotSerialized)
+{
+  Return(0x00)
+}
+Method (_STA, 0, NotSerialized)
+{
+  Return(0x0F)
+}
   }
-
   Device(SAS2) {
 Name(_HID, "HISI0162")
 Name(_CCA, 1)
@@ -244,7 +254,10 @@ Scope(_SB)
   Store(0x7, CLK)
   Sleep(1)
 }
-
+Method (_PXM, 0, NotSerialized)
+{
+  Return(0x00)
+}
Method (_STA, 0, NotSerialized)
{
  Return (0x0)
-- 
1.9.1

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Re: [edk2] [PATCH] BaseTools: Update Expression.py for VOID* support L'a' and 'a'

[Feng, YunhuaX]

sorry
L'' and '' is single quote and not include any character, so we will report 
error message

Any question, please let me know. Thanks.

Best Regards
Feng, Yunhua


-Original Message-
From: Yao, Jiewen 
Sent: Friday, February 2, 2018 9:45 PM
To: Feng, YunhuaX ; edk2-devel@lists.01.org
Cc: Gao, Liming 
Subject: RE: [PATCH] BaseTools: Update Expression.py for VOID* support L'a' and 
'a'

Good.

I am just confused on the commit message --- when the value is L'' or '', will 
report error.

Would you please clarify what does that mean?

Thank you
Yao Jiewen


> -Original Message-
> From: Feng, YunhuaX
> Sent: Friday, February 2, 2018 9:42 PM
> To: Yao, Jiewen ; edk2-devel@lists.01.org
> Cc: Gao, Liming 
> Subject: RE: [PATCH] BaseTools: Update Expression.py for VOID* support 
> L'a' and 'a'
> 
> Yes, you are right.
> 
> L"String" and "String" still support,  and we add L'String' and 'String'
> L"ab"  ==> {0x61, 0x00, 0x62, 0x00, 0x00, 0x00}
> L'ab'   ==> {0x61, 0x00, 0x62, 0x00}
> 
> Any question, please let me know. Thanks.
> 
> Best Regards
> Feng, Yunhua
> 
> -Original Message-
> From: Yao, Jiewen
> Sent: Friday, February 2, 2018 8:17 PM
> To: Feng, YunhuaX ; edk2-devel@lists.01.org
> Cc: Gao, Liming ; Yao, Jiewen 
> 
> Subject: RE: [PATCH] BaseTools: Update Expression.py for VOID* support 
> L'a' and 'a'
> 
> Hello
> May I know why we do not support L"String" ?
> 
> My understanding is that L'String' is a string without NULL 
> terminator, L"String" is a string with NULL terminator, right?
> 
> Thank you
> Yao Jiewen
> 
> > -Original Message-
> > From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf 
> > Of Feng, YunhuaX
> > Sent: Friday, February 2, 2018 5:02 PM
> > To: edk2-devel@lists.01.org
> > Cc: Gao, Liming 
> > Subject: [edk2] [PATCH] BaseTools: Update Expression.py for VOID* 
> > support
> L'a'
> > and 'a'
> >
> > Type VOID* support L'a' and 'a', the value transfer to c style value.
> > L'a' --> {0x61, 0x00}
> > L'ab' --> {0x61, 0x00, 0x62, 0x00}
> > 'a'  --> {0x61}
> > 'ab' --> {0x61, 0x62}
> >
> > when the value is L'' or '', will report error
> >
> > Cc: Liming Gao 
> > Cc: Yonghong Zhu 
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Yunhua Feng 
> > ---
> >  BaseTools/Source/Python/Common/Expression.py | 19
> ---
> >  BaseTools/Source/Python/Common/Misc.py   |  4 
> >  2 files changed, 20 insertions(+), 3 deletions(-)
> >
> > diff --git a/BaseTools/Source/Python/Common/Expression.py
> > b/BaseTools/Source/Python/Common/Expression.py
> > index b8c48460ff..6a1103df2c 100644
> > --- a/BaseTools/Source/Python/Common/Expression.py
> > +++ b/BaseTools/Source/Python/Common/Expression.py
> > @@ -740,7 +740,12 @@ class ValueExpressionEx(ValueExpression):
> >  try:
> >  PcdValue = ValueExpression.__call__(self, RealValue, Depth)
> >  if self.PcdType == 'VOID*' and 
> > (PcdValue.startswith("'") or
> > PcdValue.startswith("L'")):
> > -raise BadExpression
> > +PcdValue, Size = ParseFieldValue(PcdValue)
> > +PcdValueList = []
> > +for I in range(Size):
> > +PcdValueList.append('0x%02X'%(PcdValue & 0xff))
> > +PcdValue = PcdValue >> 8
> > +PcdValue = '{' + ','.join(PcdValueList) + '}'
> >  elif self.PcdType in ['UINT8', 'UINT16', 'UINT32', 
> > 'UINT64', 'BOOLEAN'] and (PcdValue.startswith("'") or \
> >PcdValue.startswith('"') or
> > PcdValue.startswith("L'") or PcdValue.startswith('L"') or
> PcdValue.startswith('{')):
> >  raise BadExpression @@ -755,6 +760,8 @@ class 
> > ValueExpressionEx(ValueExpression):
> >  TmpValue = 0
> >  Size = 0
> >  for Item in PcdValue:
> > +if Item.startswith('UINT8'):
> > +ItemSize = 1
> >  if Item.startswith('UINT16'):
> >  ItemSize = 2
> >  elif Item.startswith('UINT32'):
> > @@ -776,7 +783,10 @@ class ValueExpressionEx(ValueExpression):
> >  TmpValue = (ItemValue << (Size * 8)) | TmpValue
> >  Size = Size + ItemSize
> >  else:
> > -TmpValue, Size = ParseFieldValue(PcdValue)
> > +try:
> > +TmpValue, Size = ParseFieldValue(PcdValue)
> > +except BadExpression:
> > +raise BadExpression("Type: %s, Value: %s, 
> > + format
> > or value error" % (self.PcdType, PcdValue))
> >   

[edk2] [PATCH edk2-non-osi v3 5/7] Hisilicon D03/D05: Update NativeOhci binary

[Heyi Guo]

Update NativeOhci bianry for changing DmaLib to CoherentDmaLib.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang 
Signed-off-by: Heyi Guo 
Reviewed-by: Leif Lindholm 
---
 Platform/Hisilicon/D03/Drivers/OhciDxe/NativeOhci.efi | Bin 21664 -> 22336 
bytes
 Platform/Hisilicon/D05/Drivers/OhciDxe/NativeOhci.efi | Bin 23328 -> 22624 
bytes
 2 files changed, 0 insertions(+), 0 deletions(-)

diff --git a/Platform/Hisilicon/D03/Drivers/OhciDxe/NativeOhci.efi 
b/Platform/Hisilicon/D03/Drivers/OhciDxe/NativeOhci.efi
index e1970fd..5472254 100644
Binary files a/Platform/Hisilicon/D03/Drivers/OhciDxe/NativeOhci.efi and 
b/Platform/Hisilicon/D03/Drivers/OhciDxe/NativeOhci.efi differ
diff --git a/Platform/Hisilicon/D05/Drivers/OhciDxe/NativeOhci.efi 
b/Platform/Hisilicon/D05/Drivers/OhciDxe/NativeOhci.efi
index 9e7dd0e..7f0ac10 100644
Binary files a/Platform/Hisilicon/D05/Drivers/OhciDxe/NativeOhci.efi and 
b/Platform/Hisilicon/D05/Drivers/OhciDxe/NativeOhci.efi differ
-- 
1.9.1

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[edk2] [PATCH edk2-non-osi v3 6/7] Hisilicon/D03: Update binary of trusted-firmware

[Heyi Guo]

1 Workarounds for CVE-2017-5715 on Cortex A57/A72/A73 and A75 #1214.
2 Upgrade trusted firmware to 1.4

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang 
Signed-off-by: Heyi Guo 
Reviewed-by: Leif Lindholm 
Reviewed-by: Ard Biesheuvel 
---
 Platform/Hisilicon/D03/bl1.bin | Bin 14336 -> 12416 bytes
 Platform/Hisilicon/D03/fip.bin | Bin 62513 -> 66758 bytes
 2 files changed, 0 insertions(+), 0 deletions(-)

diff --git a/Platform/Hisilicon/D03/bl1.bin b/Platform/Hisilicon/D03/bl1.bin
index cdaa743..19ceb9b 100644
Binary files a/Platform/Hisilicon/D03/bl1.bin and 
b/Platform/Hisilicon/D03/bl1.bin differ
diff --git a/Platform/Hisilicon/D03/fip.bin b/Platform/Hisilicon/D03/fip.bin
index ae4ed1a..e91b0da 100644
Binary files a/Platform/Hisilicon/D03/fip.bin and 
b/Platform/Hisilicon/D03/fip.bin differ
-- 
1.9.1

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[edk2] [PATCH edk2-non-osi v3 7/7] Hisilicon/D05: Update binary of trusted-firmware

[Heyi Guo]

1 Workarounds for CVE-2017-5715 on Cortex A57/A72/A73 and A75 #1214.
2 Upgrade trusted firmware to 1.4

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang 
Signed-off-by: Heyi Guo 
Reviewed-by: Leif Lindholm 
Reviewed-by: Ard Biesheuvel 
---
 Platform/Hisilicon/D05/bl1.bin | Bin 14344 -> 12424 bytes
 Platform/Hisilicon/D05/fip.bin | Bin 41493 -> 37546 bytes
 2 files changed, 0 insertions(+), 0 deletions(-)

diff --git a/Platform/Hisilicon/D05/bl1.bin b/Platform/Hisilicon/D05/bl1.bin
index 7341476..b95257c 100644
Binary files a/Platform/Hisilicon/D05/bl1.bin and 
b/Platform/Hisilicon/D05/bl1.bin differ
diff --git a/Platform/Hisilicon/D05/fip.bin b/Platform/Hisilicon/D05/fip.bin
index 496a9b8..5958293 100644
Binary files a/Platform/Hisilicon/D05/fip.bin and 
b/Platform/Hisilicon/D05/fip.bin differ
-- 
1.9.1

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[edk2] [PATCH 00/14] rid PiSmmCpuDxeSmm of DB-encoded instructions

[Laszlo Ersek]

Repo:   https://github.com/lersek/edk2.git
Branch: patch_insn_x86

Patch 01 is a comment cleanup patch for "BaseLib.h".

Patch 02 introduces PatchInstructionX86() to BaseLib, based on the
recent discussion.

Patch 03 removes *.S and *.asm files from PiSmmCpuDxeSmm, so that the
rest of the series only needs to concern itself with *.nasm files. (The
subject of removing *.S and *.asm files for x86 was broached by Liming
on the list earlier; it's handy for this series.)

Patches 04 through 14 replace the DB encodings of instructions in
PiSmmCpuDxeSmm NASM source code. Most of the time the new
PatchInstructionX86() function is utilized, but in some cases, not even
PatchInstructionX86() is needed.

Tested the following OSes with this series (all cases used -D
SMM_REQUIRE, 2-4 VCPUs, both normal boot and S3, on KVM):

- IA32
  - Fedora 26

- IA32X64
  - Fedora 26
  - Windows 7
  - Windows 8.1
  - Windows 10
  - Windows Server 2008 R2
  - Windows Server 2012 R2
  - Windows Server 2016 (normal boot only -- S3 is untestable at this
time due to QXL GPU driver signing issues)

Cc: Ard Biesheuvel 
Cc: Eric Dong 
Cc: Jiewen Yao 
Cc: Leif Lindholm 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ruiyu Ni 

Thanks,
Laszlo

Laszlo Ersek (14):
  MdePkg/BaseLib.h: state preprocessing conditions in comments after
#endifs
  MdePkg/BaseLib: add PatchInstructionX86()
  UefiCpuPkg/PiSmmCpuDxeSmm: remove *.S and *.asm assembly files
  UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmbase" with PatchInstructionX86()
  UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmiStack" with
PatchInstructionX86()
  UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmiCr3" with PatchInstructionX86()
  UefiCpuPkg/PiSmmCpuDxeSmm: patch "XdSupported" with
PatchInstructionX86()
  UefiCpuPkg/PiSmmCpuDxeSmm: remove unneeded DBs from X64 SmmStartup()
  UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmmCr3" with PatchInstructionX86()
  UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmmCr4" with PatchInstructionX86()
  UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmmCr0" with PatchInstructionX86()
  UefiCpuPkg/PiSmmCpuDxeSmm: eliminate "gSmmJmpAddr" and related DBs
  UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmmInitStack" with
PatchInstructionX86()
  UefiCpuPkg/PiSmmCpuDxeSmm: remove DBs from
SmmRelocationSemaphoreComplete32()

 MdePkg/Include/Library/BaseLib.h|  62 +-
 MdePkg/Library/BaseLib/BaseLib.inf  |   2 +
 MdePkg/Library/BaseLib/X86PatchInstruction.c|  89 +++
 UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c   |   4 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/MpFuncs.S| 165 -
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/MpFuncs.asm  | 168 -
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S   | 215 --
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm | 223 --
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm|  25 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.S   | 696 ---
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.asm | 713 
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.S|  84 ---
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.asm  |  94 ---
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm |  30 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c  |  27 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h  |  21 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf|  20 -
 UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c  |   7 +
 UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h  |   1 +
 UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c  |  16 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/MpFuncs.S | 204 --
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/MpFuncs.asm   | 206 --
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c   |  16 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S| 243 ---
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm  | 242 ---
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm |  25 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.S| 365 --
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.asm  | 383 ---
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.S | 141 
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.asm   | 132 
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm  |  76 +--
 31 files changed, 271 insertions(+), 4424 deletions(-)
 create mode 100644 MdePkg/Library/BaseLib/X86PatchInstruction.c
 delete mode 100644 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/MpFuncs.S
 delete mode 100644 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/MpFuncs.asm
 delete mode 100644 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
 delete mode 100644 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
 delete mode 100644 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.S
 delete mode 100644 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.asm
 delete mode 100644 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.S
 delete mode 100644 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.asm
 delete mode 100644 

[edk2] [PATCH 04/14] UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmbase" with PatchInstructionX86()

[Laszlo Ersek]

Rename the variable to "gPatchSmbase" so that its association with
PatchInstructionX86() is clear from the declaration, change its type to
UINT8, and patch it with PatchInstructionX86(). This lets us remove the
binary (DB) encoding of some instructions in "SmiEntry.nasm".

Cc: Eric Dong 
Cc: Jiewen Yao 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Ruiyu Ni 
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek 
---
 UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c   | 4 ++--
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 6 +++---
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm  | 6 +++---
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c 
b/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
index 3188d438181c..c13692127fcf 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
@@ -105,7 +105,7 @@ typedef struct {
 ///
 /// Variables from SMI Handler
 ///
-extern UINT32   gSmbase;
+extern UINT8gPatchSmbase;
 extern volatile UINT32  gSmiStack;
 extern UINT32   gSmiCr3;
 extern volatile UINT8   gcSmiHandlerTemplate[];
@@ -718,7 +718,7 @@ InstallSmiHandler (
   //
   gSmiStack = (UINT32)((UINTN)SmiStack + StackSize - sizeof 
(UINTN));
   gSmiCr3   = Cr3;
-  gSmbase   = SmBase;
+  PatchInstructionX86 (, SmBase, 4);
   gSmiHandlerIdtr.Base  = IdtBase;
   gSmiHandlerIdtr.Limit = (UINT16)(IdtSize - 1);
 
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm 
b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
index a8324a7f4a84..e6e29128e64e 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
@@ -46,7 +46,7 @@ global ASM_PFX(gcSmiHandlerTemplate)
 global ASM_PFX(gcSmiHandlerSize)
 global ASM_PFX(gSmiCr3)
 global ASM_PFX(gSmiStack)
-global ASM_PFX(gSmbase)
+global ASM_PFX(gPatchSmbase)
 global ASM_PFX(mXdSupported)
 extern ASM_PFX(gSmiHandlerIdtr)
 
@@ -65,8 +65,8 @@ _SmiEntryPoint:
 o32 lgdt[cs:bx]   ; lgdt fword ptr cs:[bx]
 mov ax, PROTECT_MODE_CS
 mov [cs:bx-0x2],ax
-DB  0x66, 0xbf   ; mov edi, SMBASE
-ASM_PFX(gSmbase): DD 0
+mov edi, strict dword 0   ; source operand will be patched
+ASM_PFX(gPatchSmbase):
 lea eax, [edi + (@32bit - _SmiEntryPoint) + 0x8000]
 mov [cs:bx-0x6],eax
 mov ebx, cr0
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm 
b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
index 697fd2bec7c6..0e314279a541 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
@@ -53,7 +53,7 @@ extern ASM_PFX(gSmiHandlerIdtr)
 extern ASM_PFX(CpuSmmDebugEntry)
 extern ASM_PFX(CpuSmmDebugExit)
 
-global ASM_PFX(gSmbase)
+global ASM_PFX(gPatchSmbase)
 global ASM_PFX(mXdSupported)
 global ASM_PFX(gSmiStack)
 global ASM_PFX(gSmiCr3)
@@ -75,8 +75,8 @@ _SmiEntryPoint:
 o32 lgdt[cs:bx]   ; lgdt fword ptr cs:[bx]
 mov ax, PROTECT_MODE_CS
 mov [cs:bx-0x2],ax
-DB  0x66, 0xbf   ; mov edi, SMBASE
-ASM_PFX(gSmbase): DD 0
+mov edi, strict dword 0   ; source operand will be patched
+ASM_PFX(gPatchSmbase):
 lea eax, [edi + (@ProtectedMode - _SmiEntryPoint) + 0x8000]
 mov [cs:bx-0x6],eax
 mov ebx, cr0
-- 
2.14.1.3.gb7cf6e02401b


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[edk2] [PATCH edk2-platforms v3 00/15] Improve D0x platforms and bug fix

[Heyi Guo]

The major features of this patchset include
adding PPTT support, 
switching to Generic BDS driver,
adding capsule upgrade support,
open-source version for SnpPlatform and SasPlatform
changing DmaLib to CoherentDmaLib.

Note: The patch PPTT is related to the edk2 patch "MdePkg ACPI: Add some macros 
for PPTT".

Code can also be found in github: 
https://github.com/hisilicon/OpenPlatformPkg.git
branch: rp-1802-platforms-v3


Heyi Guo (15):
  Hisilicon/D05: Move Madt definition to head file
  Hisilicon/D05: Add PPTT support
  Hisilicon/D0x/BDS: Switch to Generic BDS driver
  Hisilicon/D0x: Break BMC SetBoot option out into separate library
  Hisilicon D03/D05: Add capsule upgrade support
  Hisilicon D03/D05: Open SasPlatform source code
  Hisilicon D03/D05: Open SnpPlatform source code
  Hilisicon: Change DmaLib to CoherentDmaLib
  Hisilicon/Smbios: Indicate use of ProcessorFamily2 in type 4 table
  Hisilicon/PCIe: Disable PCIe ASPM
  Hisilicon/D05: Replace SP805Watchdog by WatchdogTimer driver.
  Hisilicon/D03: Replace SP805Watchdog by WatchdogTimer driver.
  Hisilicon/D05/ACPI: Add ITS PXM
  Hisilicon/D05/ACPI: Add Pcie, HNS and SAS PXM
  Hisilicon D03/D05: Update firmware version to 18.02

 
Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
 |  45 ++
 Platform/Hisilicon/D03/D03.dsc 
  |  42 +-
 Platform/Hisilicon/D03/D03.fdf 
  |  79 ++-
 
Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
|  81 +++
 
Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
 |  50 ++
 
Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c
|  70 +++
 
Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
 |  45 ++
 Platform/Hisilicon/D05/D05.dsc 
  |  47 +-
 Platform/Hisilicon/D05/D05.fdf 
  |  80 ++-
 
Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
|  81 +++
 
Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
 |  50 ++
 
Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c
|  70 +++
 Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.c
  | 106 
 Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf  
  |  45 ++
 Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c  
  |   4 +-
 Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.c
  | 115 
 Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf  
  |  46 ++
 Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.c  
  |   2 +-
 Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.c 
  |   3 +-
 Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
  | 103 
 Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h
  |   2 +
 Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc
  |  10 +
 Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl 
  |   9 +
 Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl 
  |  34 +-
 Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl 
  |  19 +-
 Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h
  |  30 +-
 Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc 
  |  23 +-
 Silicon/Hisilicon/Hi1616/Pptt/Pptt.c   
  | 529 
 Silicon/Hisilicon/Hi1616/Pptt/Pptt.h   
  |  67 ++
 Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf 
  |  48 ++
 Silicon/Hisilicon/HisiPkg.dec  
  |   6 +
 Silicon/Hisilicon/Hisilicon.dsc.inc
  |  12 +-
 Silicon/Hisilicon/Hisilicon.fdf.inc
  |   9 +
 Silicon/Hisilicon/Include/Library/AcpiNextLib.h
  |  10 +-
 Silicon/Hisilicon/Include/Library/BmcConfigBootLib.h   
  |  31 +
 Silicon/Hisilicon/Include/Library/OemDevicePath.h  
  |  52 ++
 Silicon/Hisilicon/Include/Protocol/HisiPlatformSasProtocol.h   
  |  30 +
 Silicon/Hisilicon/Include/Protocol/SnpPlatformProtocol.h  

[edk2] [PATCH edk2-platforms v3 01/15] Hisilicon/D05: Move Madt definition to head file

[Heyi Guo]

Move definition of Madt struct to head file, so PPTT driver
can include it.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang 
Signed-off-by: Heyi Guo 
Reviewed-by: Ard Biesheuvel 
Reviewed-by: Graeme Gregory 
Reveiwed-by: Jeremy Linton 
---
 Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h | 30 
+++-
 Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc  | 23 +--
 2 files changed, 30 insertions(+), 23 deletions(-)

diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h 
b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h
index 808219a..ad73aa2 100644
--- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h
+++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h
@@ -1,7 +1,7 @@
 /** @file
 *
 *  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
-*  Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015-2018, Hisilicon Limited. All rights reserved.
 *  Copyright (c) 2015-2016, Linaro Limited. All rights reserved.
 *
 *  This program and the accompanying materials
@@ -20,6 +20,8 @@
 #ifndef _HI1610_PLATFORM_H_
 #define _HI1610_PLATFORM_H_
 
+#include 
+
 //
 // ACPI table information used to initialize tables.
 //
@@ -44,5 +46,31 @@
   }
 
 #define HI1616_WATCHDOG_COUNT  2
+#define HI1616_GIC_STRUCTURE_COUNT  64
+
+#define HI1616_MPID_TA_BASE  0x1
+#define HI1616_MPID_TB_BASE  0x3
+#define HI1616_MPID_TA_2_BASE  0x5
+#define HI1616_MPID_TB_2_BASE  0x7
+
+// Differs from Juno, we have another affinity level beyond cluster and core
+#define PLATFORM_GET_MPID_TA(ClusterId, CoreId)   (HI1616_MPID_TA_BASE | 
((ClusterId) << 8) | (CoreId))
+#define PLATFORM_GET_MPID_TB(ClusterId, CoreId)   (HI1616_MPID_TB_BASE | 
((ClusterId) << 8) | (CoreId))
+#define PLATFORM_GET_MPID_TA_2(ClusterId, CoreId)   (HI1616_MPID_TA_2_BASE | 
((ClusterId) << 8) | (CoreId))
+#define PLATFORM_GET_MPID_TB_2(ClusterId, CoreId)   (HI1616_MPID_TB_2_BASE | 
((ClusterId) << 8) | (CoreId))
+
+//
+// Multiple APIC Description Table
+//
+#pragma pack (1)
+
+typedef struct {
+  EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER   Header;
+  EFI_ACPI_6_1_GIC_STRUCTURE
GicInterfaces[HI1616_GIC_STRUCTURE_COUNT];
+  EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
+  EFI_ACPI_6_1_GIC_ITS_STRUCTUREGicITS[8];
+} EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE;
+
+#pragma pack ()
 
 #endif
diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc 
b/Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc
index 169ee72..54605a6 100644
--- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc
+++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc
@@ -2,7 +2,7 @@
 *  Multiple APIC Description Table (MADT)
 *
 *  Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
-*  Copyright (c) 2015 - 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015 - 2018, Hisilicon Limited. All rights reserved.
 *  Copyright (c) 2015 - 2016, Linaro Limited. All rights reserved.
 *
 *  This program and the accompanying materials
@@ -27,27 +27,6 @@
 #include 
 #include "Hi1616Platform.h"
 
-// Differs from Juno, we have another affinity level beyond cluster and core
-// 0x2 is only for socket 0
-#define PLATFORM_GET_MPID_TA(ClusterId, CoreId)   (0x1 | ((ClusterId) << 
8) | (CoreId))
-#define PLATFORM_GET_MPID_TB(ClusterId, CoreId)   (0x3 | ((ClusterId) << 
8) | (CoreId))
-#define PLATFORM_GET_MPID_TA_2(ClusterId, CoreId)   (0x5 | ((ClusterId) << 
8) | (CoreId))
-#define PLATFORM_GET_MPID_TB_2(ClusterId, CoreId)   (0x7 | ((ClusterId) << 
8) | (CoreId))
-
-//
-// Multiple APIC Description Table
-//
-#pragma pack (1)
-
-typedef struct {
-  EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER   Header;
-  EFI_ACPI_6_1_GIC_STRUCTUREGicInterfaces[64];
-  EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
-  EFI_ACPI_6_1_GIC_ITS_STRUCTURE  GicITS[8];
-} EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE;
-
-#pragma pack ()
-
 EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
   {
 ARM_ACPI_HEADER (
-- 
1.9.1

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Re: [edk2] [PATCH] BaseTools: Update Expression.py for VOID* support L'a' and 'a'

[Yao, Jiewen]

Hello
May I know why we do not support L"String" ?

My understanding is that L'String' is a string without NULL terminator, 
L"String" is a string with NULL terminator, right?

Thank you
Yao Jiewen

> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Feng,
> YunhuaX
> Sent: Friday, February 2, 2018 5:02 PM
> To: edk2-devel@lists.01.org
> Cc: Gao, Liming 
> Subject: [edk2] [PATCH] BaseTools: Update Expression.py for VOID* support L'a'
> and 'a'
> 
> Type VOID* support L'a' and 'a', the value transfer to c style value.
> L'a' --> {0x61, 0x00}
> L'ab' --> {0x61, 0x00, 0x62, 0x00}
> 'a'  --> {0x61}
> 'ab' --> {0x61, 0x62}
> 
> when the value is L'' or '', will report error
> 
> Cc: Liming Gao 
> Cc: Yonghong Zhu 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Yunhua Feng 
> ---
>  BaseTools/Source/Python/Common/Expression.py | 19 ---
>  BaseTools/Source/Python/Common/Misc.py   |  4 
>  2 files changed, 20 insertions(+), 3 deletions(-)
> 
> diff --git a/BaseTools/Source/Python/Common/Expression.py
> b/BaseTools/Source/Python/Common/Expression.py
> index b8c48460ff..6a1103df2c 100644
> --- a/BaseTools/Source/Python/Common/Expression.py
> +++ b/BaseTools/Source/Python/Common/Expression.py
> @@ -740,7 +740,12 @@ class ValueExpressionEx(ValueExpression):
>  try:
>  PcdValue = ValueExpression.__call__(self, RealValue, Depth)
>  if self.PcdType == 'VOID*' and (PcdValue.startswith("'") or
> PcdValue.startswith("L'")):
> -raise BadExpression
> +PcdValue, Size = ParseFieldValue(PcdValue)
> +PcdValueList = []
> +for I in range(Size):
> +PcdValueList.append('0x%02X'%(PcdValue & 0xff))
> +PcdValue = PcdValue >> 8
> +PcdValue = '{' + ','.join(PcdValueList) + '}'
>  elif self.PcdType in ['UINT8', 'UINT16', 'UINT32', 'UINT64',
> 'BOOLEAN'] and (PcdValue.startswith("'") or \
>PcdValue.startswith('"') or PcdValue.startswith("L'")
> or PcdValue.startswith('L"') or PcdValue.startswith('{')):
>  raise BadExpression
> @@ -755,6 +760,8 @@ class ValueExpressionEx(ValueExpression):
>  TmpValue = 0
>  Size = 0
>  for Item in PcdValue:
> +if Item.startswith('UINT8'):
> +ItemSize = 1
>  if Item.startswith('UINT16'):
>  ItemSize = 2
>  elif Item.startswith('UINT32'):
> @@ -776,7 +783,10 @@ class ValueExpressionEx(ValueExpression):
>  TmpValue = (ItemValue << (Size * 8)) | TmpValue
>  Size = Size + ItemSize
>  else:
> -TmpValue, Size = ParseFieldValue(PcdValue)
> +try:
> +TmpValue, Size = ParseFieldValue(PcdValue)
> +except BadExpression:
> +raise BadExpression("Type: %s, Value: %s, format
> or value error" % (self.PcdType, PcdValue))
>  if type(TmpValue) == type(''):
>  TmpValue = int(TmpValue)
>  else:
> @@ -858,7 +868,7 @@ class ValueExpressionEx(ValueExpression):
>  else:
>  raise BadExpression('%s not
> defined before use' % Offset)
>  ValueType = ""
> -if Item.startswith('UINT16'):
> +if Item.startswith('UINT8'):
>  ItemSize = 1
>  ValueType = "UINT8"
>  elif Item.startswith('UINT16'):
> @@ -887,6 +897,9 @@ class ValueExpressionEx(ValueExpression):
> 
>  if Size > 0:
>  PcdValue = '{' + ValueStr[:-2] + '}'
> +else:
> +raise  BadExpression("Type: %s, Value: %s, format
> or value error"%(self.PcdType, PcdValue))
> +
>  if PcdValue == 'True':
>  PcdValue = '1'
>  if PcdValue == 'False':
> diff --git a/BaseTools/Source/Python/Common/Misc.py
> b/BaseTools/Source/Python/Common/Misc.py
> index b34cb4c3be..d80f645d2e 100644
> --- a/BaseTools/Source/Python/Common/Misc.py
> +++ b/BaseTools/Source/Python/Common/Misc.py
> @@ -1572,6 +1572,8 @@ def ParseFieldValue (Value):
>  if Value.startswith("L'") and Value.endswith("'"):
>  # Unicode Character Constant
>  List = list(Value[2:-1])
> +if len(List) == 0:
> +raise BadExpression('Length %s is %s' % (Value, len(List)))
>  List.reverse()
>  Value = 

Re: [edk2] [PATCH edk2-platforms v2 02/15] Hisilicon/D05: Add PPTT support

[Jeremy Linton]

Hi,

On 02/01/2018 09:42 PM, Huangming (Mark) wrote:



On 2018/2/1 9:11, Jeremy Linton wrote:

Hi,


On 01/26/2018 02:00 AM, Ming Huang wrote:

Add Processor Properties Topology Table, PPTT include


(trimming)


+STATIC
+VOID
+InitCacheInfo (
+  VOID
+  )
+{
+  UINT8Index;
+  EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES Type1Attributes;
+  CSSELR_DATA  CsselrData;
+  CCSIDR_DATA  CcsidrData;
+
+  for (Index = 0; Index < PPTT_CACHE_NO; Index++) {
+CsselrData.Data = 0;
+CcsidrData.Data = 0;
+SetMem (
+  ,
+  sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES),
+  0
+  );
+
+if (Index == 0) { //L1I
+  CsselrData.Bits.InD = 1;
+  CsselrData.Bits.Level = 0;
+  Type1Attributes.CacheType  = 1;
+} else if (Index == 1) {
+  Type1Attributes.CacheType  = 0;
+  CsselrData.Bits.Level = Index - 1;
+} else {
+  Type1Attributes.CacheType  = 2;
+  CsselrData.Bits.Level = Index - 1;
+}
+
+CcsidrData.Data = ReadCCSIDR (CsselrData.Data);
+
+if (CcsidrData.Bits.Wa == 1) {
+  Type1Attributes.AllocationType  = PPTT_TYPE1_ALLOCATION_WRITE;
+  if (CcsidrData.Bits.Ra == 1) {
+Type1Attributes.AllocationType  = PPTT_TYPE1_ALLOCATION_READ_WRITE;
+  }
+}
+
+if (CcsidrData.Bits.Wt == 1) {
+  Type1Attributes.WritePolicy = 1;


Note a few cases where you have mixed PPTT #define definitions for some 
of the fields (AllocateType, WritePolicy, CacheType) with numeric values.




+}
+DEBUG ((DEBUG_INFO,
+"[Acpi PPTT] Level = %x!CcsidrData = %x!\n",
+CsselrData.Bits.Level,
+CcsidrData.Data));
+
+mPpttCacheType1[Index].Type = EFI_ACPI_6_2_PPTT_TYPE_CACHE;
+mPpttCacheType1[Index].Length = sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE);
+mPpttCacheType1[Index].Reserved[0] = 0;
+mPpttCacheType1[Index].Reserved[1] = 0;
+mPpttCacheType1[Index].Flags.SizePropertyValid = 1;
+mPpttCacheType1[Index].Flags.NumberOfSetsValid = 1;
+mPpttCacheType1[Index].Flags.AssociativityValid = 1;
+mPpttCacheType1[Index].Flags.AllocationTypeValid = 1;
+mPpttCacheType1[Index].Flags.CacheTypeValid = 1;
+mPpttCacheType1[Index].Flags.WritePolicyValid = 1;
+mPpttCacheType1[Index].Flags.LineSizeValid = 1;
+mPpttCacheType1[Index].Flags.Reserved = 0;
+mPpttCacheType1[Index].NextLevelOfCache = 0;
+
+if (Index != PPTT_CACHE_NO - 1) {
+  mPpttCacheType1[Index].NumberOfSets = (UINT16)CcsidrData.Bits.NumSets + 
1;
+  mPpttCacheType1[Index].Associativity = 
(UINT16)CcsidrData.Bits.Associativity + 1;
+  mPpttCacheType1[Index].LineSize = (UINT16)( 1 << 
(CcsidrData.Bits.LineSize + 4));
+  mPpttCacheType1[Index].Size = mPpttCacheType1[Index].LineSize *  \
+mPpttCacheType1[Index].Associativity * \
+mPpttCacheType1[Index].NumberOfSets;
+  CopyMem (
+[Index].Attributes,
+,
+sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES)
+);
+} else {
+  // L3 cache
+  mPpttCacheType1[Index].Size = 0x100;   // 16m
+  mPpttCacheType1[Index].NumberOfSets = 0x2000;
+  mPpttCacheType1[Index].Associativity = 0x10;   // CacheAssociativity16Way
+  SetMem (
+[Index].Attributes,
+sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES),
+0x0A
+);
+  mPpttCacheType1[Index].LineSize = 0x80;// 128byte
+}
+  }


(trimming)


+#define PPTT_TYPE0_SOCKET_FLAG PPTT_TYPE0_PHYSICAL_PKG
+#define PPTT_TYPE0_SCCL_FLAG   0
+#define PPTT_TYPE0_CLUSTER_FLAG0
+#define PPTT_TYPE0_CORE_FLAG   PPTT_TYPE0_PROCESSORID_VALID
+
+#define PPTT_TYPE1_ALLOCATION_WRITE   0x1
+#define PPTT_TYPE1_ALLOCATION_READ_WRITE  0x2


Its more clear for these two, they should be in the acpi header file. While 
your at it the write policy and cache type should also probably be defined and 
used in your init routing.




I plan to move these two macro to Acpi62.h.

"While your at it the write policy and cache type should also probably be defined 
and used in your init routing"
I don't really understand the mean above.


I was simply suggesting that you define/use new #defines to describe 
acpi standardized values you place in the policy and type (and any more 
you think might be helpful) fields. For example, I found it a bit odd 
that you defined PPTT_TYPE1_ALLOCATION_* but not 'PPTT_TYPE1_WRITE_POLICY_*'



Thanks,
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Re: [edk2] MinPlatformPkg/PlatformInit: FV code

[Marvin H?user]

Good point with the DxeCore, I didn't consider that. Though OsBoot would be 
irrelevant to the PEI phase, wouldn't it be?

Thanks,
Marvin

From: Yao, Jiewen [mailto:jiewen@intel.com]
Sent: Friday, February 2, 2018 1:40 PM
To: Marvin H?user ; edk2-devel@lists.01.org
Subject: RE: MinPlatformPkg/PlatformInit: FV code

Excellent question.

Comment inline.

From: Marvin H?user [mailto:marvin.haeu...@outlook.com]
Sent: Wednesday, January 31, 2018 1:54 AM
To: edk2-devel@lists.01.org; Yao, Jiewen 
>
Subject: MinPlatformPkg/PlatformInit: FV code

Dear developers, dear Jiewen,

I have been investigating the devel-MinPlatform branch of edk2-platforms for 
educational purposes and got two questions regarding the Firmware Volume code 
in PlatformInitPreMem, if you do not mind. I assume the tree was tested, so 
most likely I misunderstood some things.


  1.  Why is a Firmware Volume HOB built to cover the entire flash range 
(https://github.com/tianocore/edk2-platforms/blob/devel-MinPlatform/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c#L379)?
 Am I correct that this implies a FV spanning through the entire flash MMIO 
range, which would then imply all other FVs are contained within it? This would 
make sense, however that's not what I saw in the KabylakeOpenBoardPkg Flash 
Map, which has the NV Storage first 
(https://github.com/tianocore/edk2-platforms/blob/devel-MinPlatform/Platform/Intel/KabylakeOpenBoardPkg/Include/Fdf/FlashMapInclude.fdf#L25).

[Jiewen] You are right. We should not use FD region for FV. Will fix it.



  1.  Why are FV Info PPIs installed for the UefiBoot and the OsBoot FVs 
(https://github.com/tianocore/edk2-platforms/blob/devel-MinPlatform/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c#L344)?
 If I checked correctly, installing this PPI type will trigger PeiCore to 
dispatch PEIMs in the FVs, however there are only DXE drivers in these. Why are 
no FV HOBs installed, which are gotten by DxeCore?

[Jiewen] In DxeIpl, PeiServicesFfsFindNextVolume() is used to search DxeCore.
In PeiCore, PeiFfsFindNextVolume() calls FindNextCoreFvHandle() for DxeCore one 
by one. If PcdFrameworkCompatibilitySupport is FALSE, it returns 
>Fv[Instance] directly.

And Fv[Instance] is added in FirmwareVolmeInfoPpiNotifyCallback(), when 
gEfiPeiFirmwareVolumeInfo2PpiGuid is installed.

So if PcdFrameworkCompatibilitySupport is FALSE, install PPI is the only way to 
let PEI core discover DxeCore.
Only if PcdFrameworkCompatibilitySupport is TRUE, install PPI is not required, 
but the FindNextCoreFvHandle() will install the PPI for the HobFv. The result 
is same.


Thank you
Yao Jiewen




Thanks in advance for your time!

Best regards,
Marvin.
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Re: [edk2] [RFC] MdeModulePkg/PciHostBridgeDxe: Add support for address translation

[Ni, Ruiyu]

> -Original Message-
> From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org]
> Sent: Friday, February 2, 2018 4:22 PM
> To: Ni, Ruiyu 
> Cc: Guo Heyi ,Dong Wei ; Dong,
> Eric ; edk2-devel@lists.01.org; linaro-uefi  u...@lists.linaro.org>; Kinney, Michael D ; Zeng,
> Star 
> Subject: Re: [edk2] [RFC] MdeModulePkg/PciHostBridgeDxe: Add support for
> address translation
> 
> On 2 February 2018 at 00:34, Ni, Ruiyu  wrote:
> >
> >
> >> -Original Message-
> >> From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org]
> >> Sent: Friday, February 2, 2018 1:23 AM
> >> To: Ni, Ruiyu 
> >> Cc: Guo Heyi ,Dong Wei ;
> Dong,
> >> Eric ; edk2-devel@lists.01.org; linaro-uefi
> >> ; Kinney, Michael D
> >> ; Zeng, Star 
> >> Subject: Re: [edk2] [RFC] MdeModulePkg/PciHostBridgeDxe: Add support
> >> for address translation
> >>
> >> On 1 February 2018 at 05:03, Ni, Ruiyu  wrote:
> >> > On 1/29/2018 4:50 PM, Guo Heyi wrote:
> >> >>
> >> >> Sorry for the late; I caught cold and didn't work for several days
> >> >> last week :( Please see my comments below:
> >> >>
> >> >>
> >> >> On Mon, Jan 22, 2018 at 11:36:14AM +0800, Ni, Ruiyu wrote:
> >> >>>
> >> >>> On 1/18/2018 9:26 AM, Guo Heyi wrote:
> >> 
> >>  On Wed, Jan 17, 2018 at 02:08:06PM +, Ard Biesheuvel wrote:
> >> >
> >> > On 15 January 2018 at 14:46, Heyi Guo  wrote:
> >> >>
> >> >> This is the draft patch for the discussion posted in
> >> >> edk2-devel mailing list:
> >> >> https://lists.01.org/pipermail/edk2-devel/2017-December/019289
> >> >> .ht
> >> >> ml
> >> >>
> >> >> As discussed in the mailing list, we'd like to add support for
> >> >> PCI address translation which is necessary for some non-x86
> >> >> platforms. I also want to minimize the changes to the generic
> >> >> host bridge driver and platform PciHostBridgeLib
> >> >> implemetations, so additional two interfaces are added to
> >> >> expose translation information of the platform. To be generic,
> >> >> I add translation for each type of IO or memory resources.
> >> >>
> >> >> The patch is still a RFC, so I only passed the build for
> >> >> qemu64 and the function has not been tested yet.
> >> >>
> >> >> Please let me know your comments about it.
> >> >>
> >> >> Thanks.
> >> >>
> >> >> Contributed-under: TianoCore Contribution Agreement 1.1
> >> >> Signed-off-by: Heyi Guo 
> >> >> Cc: Ruiyu Ni 
> >> >> Cc: Ard Biesheuvel 
> >> >> Cc: Star Zeng 
> >> >> Cc: Eric Dong 
> >> >> ---
> >> >>   .../FdtPciHostBridgeLib/FdtPciHostBridgeLib.c  |  19 
> >> >>   .../Bus/Pci/PciHostBridgeDxe/PciHostBridge.c   |  53 
> >> >> ---
> >> >>   .../Bus/Pci/PciHostBridgeDxe/PciRootBridge.h   |   8 +-
> >> >>   .../Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 101
> >> >> ++---
> >> >>   MdeModulePkg/Include/Library/PciHostBridgeLib.h|  36
> 
> >> >>   5 files changed, 192 insertions(+), 25 deletions(-)
> >> >>
> >> >> diff --git
> >> >> a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c
> >> >> b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c
> >> >> index 5b9c887..0c8371a 100644
> >> >> ---
> >> >> a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c
> >> >> +++ b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.
> >> >> +++ c
> >> >> @@ -360,6 +360,16 @@ PciHostBridgeGetRootBridges (
> >> >> return 
> >> >>   }
> >> >>
> >> >> +PCI_ROOT_BRIDGE_TRANSLATION * EFIAPI
> >> >> +PciHostBridgeGetTranslations (
> >> >> +  UINTN *Count
> >> >> +  )
> >> >> +{
> >> >> +  *Count = 0;
> >> >> +  return NULL;
> >> >> +}
> >> >> +
> >> >>   /**
> >> >> Free the root bridge instances array returned from
> >> >> PciHostBridgeGetRootBridges().
> >> >> @@ -377,6 +387,15 @@ PciHostBridgeFreeRootBridges (
> >> >> ASSERT (Count == 1);
> >> >>   }
> >> >>
> >> >> +VOID
> >> >> +EFIAPI
> >> >> +PciHostBridgeFreeTranslations (
> >> >> +  PCI_ROOT_BRIDGE_TRANSLATION *Translations,
> >> >> +  UINTN   Count
> >> >> +  )
> >> >> +{
> >> >> +}
> >> >> +
> >> >>   /**
> >> >> Inform the platform that the resource conflict happens.
> >> >>
> >> >> diff --git
> >> >> asame/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c
> >> >> 

Re: [edk2] [PATCH edk2-platforms v2 00/15] Improve D0x platforms and bug fix

[Huangming (Mark)]

On 2018/1/30 1:33, Leif Lindholm wrote:
> So, I'm mostly happy with this set, but:
> 
> Sender (and hence Author for all patches that do not have a second
> From: statement after Subject: ) for all patches here is
> Ming Huang 
> 
> Can you please address this, either by actually sending from Ming Huang, or
> by adding a From:.
> 

I had modify the auther to heyi Guo which is equal to the sender in V3, but
the emails do not have "From: " also, I am puzzle about that.
Maybe a Linaro email account for myself is the best solution.

Thanks,
Ming

> You can add my
> Reviewed-by: Leif Lindholm 
> to 3-4, 6-12 and 15.
> 
> I have a few comments on 5/15, and then I need some input from others
> on the ACPI bits - especially from Jeremy, who should ideally have
> been cc:d on at least the PPTT patch given his comments on v1.
> 
> /
> Leif
> 
> On Fri, Jan 26, 2018 at 04:00:35PM +0800, Ming Huang wrote:
>> The major features of this patchset include
>> adding PPTT support, 
>> switching to Generic BDS driver,
>> adding capsule upgrade support,
>> open-source version for SnpPlatform and SasPlatform
>> changing DmaLib to CoherentDmaLib(this one is omissive in v1).
>>
>> Code can also be found in github: 
>> https://github.com/hisilicon/OpenPlatformPkg.git
>> branch: rp-1802-platforms-v2
>>
>>
>> Jason Zhang (3):
>>   Hisilicon D03/D05: Add capsule upgrade support
>>   Hisilicon D03/D05: Open SasPlatform source code
>>   Hisilicon D03/D05: Open SnpPlatform source code
>>
>> Ming Huang (11):
>>   Hisilicon/D05: Move Madt definition to head file
>>   Hisilicon/D05: Add PPTT support
>>   Hisilicon/D0x/BDS: Switch to Generic BDS driver
>>   Hisilicon/D0x: Break BMC SetBoot option out into separate library
>>   Hilisicon: Change DmaLib to CoherentDmaLib
>>   Hisilicon/Smbios: Indicate use of ProcessorFamily2 in type 4 table
>>   Hisilicon/D05: Replace SP805Watchdog by WatchdogTimer driver.
>>   Hisilicon/D03: Replace SP805Watchdog by WatchdogTimer driver.
>>   Hisilicon/D05/ACPI: Add ITS PXM
>>   Hisilicon/D05/ACPI: Add Pcie, HNS and SAS PXM
>>   Hisilicon D03/D05: Update firmware version to 18.02
>>
>> Yan Zhang (1):
>>   Hisilicon/PCIe: Disable PCIe ASPM
>>
>>  
>> Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
>>  |  45 ++
>>  Platform/Hisilicon/D03/D03.dsc  
>>  |  42 +-
>>  Platform/Hisilicon/D03/D03.fdf  
>>  |  79 ++-
>>  
>> Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
>> |  81 +++
>>  
>> Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
>>  |  50 ++
>>  
>> Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c
>> |  70 +++
>>  
>> Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
>>  |  45 ++
>>  Platform/Hisilicon/D05/D05.dsc  
>>  |  47 +-
>>  Platform/Hisilicon/D05/D05.fdf  
>>  |  80 ++-
>>  
>> Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
>> |  81 +++
>>  
>> Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
>>  |  50 ++
>>  
>> Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c
>> |  70 +++
>>  Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.c 
>>  | 106 
>>  Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf   
>>  |  45 ++
>>  Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c   
>>  |   4 +-
>>  Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.c 
>>  | 115 
>>  Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf   
>>  |  46 ++
>>  Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.c   
>>  |   2 +-
>>  Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.c  
>>  |   3 +-
>>  Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c 
>>  | 103 
>>  Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h 
>>  |   2 +
>>  Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc 
>>  |  10 +
>>  Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl  
>>  |   9 +
>>  Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl  
>>  |  34 +-
>>  Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl  
>>  |  19 +-
>>  Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h

[edk2] [PATCH] SecurityPkg: Add UNI string for 2 PCDs

[Zhang, Chao B]

Add prompt & help string for PcdTpm2CurrentIrqNum, PcdTpm2PossibleIrqNumBuf

Cc: Dandan Bi 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chao Zhang 
---
 SecurityPkg/SecurityPkg.uni | 11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/SecurityPkg/SecurityPkg.uni b/SecurityPkg/SecurityPkg.uni
index 1263516..aaf7726 100644
--- a/SecurityPkg/SecurityPkg.uni
+++ b/SecurityPkg/SecurityPkg.uni
@@ -5,7 +5,7 @@
 // It also provides the definitions(including PPIs/PROTOCOLs/GUIDs and library 
classes)
 // and libraries instances, which are used for those features.
 //
-// Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
+// Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
 //
 // This program and the accompanying materials are licensed and made available 
under
 // the terms and conditions of the BSD License which accompanies this 
distribution.
@@ -238,3 +238,12 @@

 "To support configuring from setup page, this PCD can be DynamicHii type 
and map to a setup option.\n"

 "For example, map to TCG2_VERSION.Tpm2AcpiTableRev to be configured by 
Tcg2ConfigDxe driver.\n"

 
"gEfiSecurityPkgTokenSpaceGuid.PcdTpm2AcpiTableRev|L\"TCG2_VERSION\"|gTcg2ConfigFormSetGuid|0x8|3|NV,BS"
+
+#string STR_gEfiSecurityPkgTokenSpaceGuid_PcdTpm2CurrentIrqNum_PROMPT  
#language en-US "Current TPM2 device interrupt number"
+
+#string STR_gEfiSecurityPkgTokenSpaceGuid_PcdTpm2CurrentIrqNum_HELP  #language 
en-US "This PCD defines current TPM2 device interrupt number reported by _CRS. 
If set to 0, interrupt is disabled."
+
+#string STR_gEfiSecurityPkgTokenSpaceGuid_PcdTpm2PossibleIrqNumBuf_PROMPT  
#language en-US "Possible TPM2 device interrupt number buffer"
+
+#string STR_gEfiSecurityPkgTokenSpaceGuid_PcdTpm2PossibleIrqNumBuf_HELP  
#language en-US "This PCD defines possible TPM2 interrupt number in a platform 
reported by _PRS control method.\n"
+   
  "If PcdTpm2CurrentIrqNum set to 0, _PRS will not report any possible 
TPM2 interrupt numbers."
\ No newline at end of file
-- 
1.9.5.msysgit.1

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Re: [edk2] MinPlatformPkg/PlatformInit: FV code

[Yao, Jiewen]

Marvin
I have filed 2 bugzilla to record this.

https://bugzilla.tianocore.org/show_bug.cgi?id=872
https://bugzilla.tianocore.org/show_bug.cgi?id=871

Thank you
Yao Jiewen


> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Yao,
> Jiewen
> Sent: Saturday, February 3, 2018 9:54 AM
> To: Marvin H?user ; edk2-devel@lists.01.org
> Subject: Re: [edk2] MinPlatformPkg/PlatformInit: FV code
> 
> Ah, good catch.
> 
> That is correct - it is irrelevant to PEI. To put to FV Hob is enough, I 
> believe.
> 
> Appreciate your careful review, which helps us clean up the code. :-)
> 
> Thank you
> Yao Jiewen
> 
> 
> > -Original Message-
> > From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
> > Marvin H?user
> > Sent: Saturday, February 3, 2018 2:30 AM
> > To: edk2-devel@lists.01.org; Yao, Jiewen 
> > Subject: Re: [edk2] MinPlatformPkg/PlatformInit: FV code
> >
> > Good point with the DxeCore, I didn't consider that. Though OsBoot would be
> > irrelevant to the PEI phase, wouldn't it be?
> >
> > Thanks,
> > Marvin
> >
> > From: Yao, Jiewen [mailto:jiewen@intel.com]
> > Sent: Friday, February 2, 2018 1:40 PM
> > To: Marvin H?user ; edk2-devel@lists.01.org
> > Subject: RE: MinPlatformPkg/PlatformInit: FV code
> >
> > Excellent question.
> >
> > Comment inline.
> >
> > From: Marvin H?user [mailto:marvin.haeu...@outlook.com]
> > Sent: Wednesday, January 31, 2018 1:54 AM
> > To: edk2-devel@lists.01.org; Yao, Jiewen
> > >
> > Subject: MinPlatformPkg/PlatformInit: FV code
> >
> > Dear developers, dear Jiewen,
> >
> > I have been investigating the devel-MinPlatform branch of edk2-platforms for
> > educational purposes and got two questions regarding the Firmware Volume
> > code in PlatformInitPreMem, if you do not mind. I assume the tree was 
> > tested,
> so
> > most likely I misunderstood some things.
> >
> >
> >   1.  Why is a Firmware Volume HOB built to cover the entire flash range
> >
> (https://github.com/tianocore/edk2-platforms/blob/devel-MinPlatform/Platfor
> >
> m/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c#L3
> > 79)? Am I correct that this implies a FV spanning through the entire flash
> MMIO
> > range, which would then imply all other FVs are contained within it? This 
> > would
> > make sense, however that's not what I saw in the KabylakeOpenBoardPkg
> Flash
> > Map, which has the NV Storage first
> >
> (https://github.com/tianocore/edk2-platforms/blob/devel-MinPlatform/Platfor
> > m/Intel/KabylakeOpenBoardPkg/Include/Fdf/FlashMapInclude.fdf#L25).
> >
> > [Jiewen] You are right. We should not use FD region for FV. Will fix it.
> >
> >
> >
> >   1.  Why are FV Info PPIs installed for the UefiBoot and the OsBoot FVs
> >
> (https://github.com/tianocore/edk2-platforms/blob/devel-MinPlatform/Platfor
> >
> m/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c#L3
> > 44)? If I checked correctly, installing this PPI type will trigger PeiCore 
> > to
> dispatch
> > PEIMs in the FVs, however there are only DXE drivers in these. Why are no FV
> > HOBs installed, which are gotten by DxeCore?
> >
> > [Jiewen] In DxeIpl, PeiServicesFfsFindNextVolume() is used to search 
> > DxeCore.
> > In PeiCore, PeiFfsFindNextVolume() calls FindNextCoreFvHandle() for DxeCore
> > one by one. If PcdFrameworkCompatibilitySupport is FALSE, it returns
> > >Fv[Instance] directly.
> >
> > And Fv[Instance] is added in FirmwareVolmeInfoPpiNotifyCallback(), when
> > gEfiPeiFirmwareVolumeInfo2PpiGuid is installed.
> >
> > So if PcdFrameworkCompatibilitySupport is FALSE, install PPI is the only 
> > way to
> > let PEI core discover DxeCore.
> > Only if PcdFrameworkCompatibilitySupport is TRUE, install PPI is not 
> > required,
> > but the FindNextCoreFvHandle() will install the PPI for the HobFv. The 
> > result is
> > same.
> >
> >
> > Thank you
> > Yao Jiewen
> >
> >
> >
> >
> > Thanks in advance for your time!
> >
> > Best regards,
> > Marvin.
> > ___
> > edk2-devel mailing list
> > edk2-devel@lists.01.org
> > https://lists.01.org/mailman/listinfo/edk2-devel
> ___
> edk2-devel mailing list
> edk2-devel@lists.01.org
> https://lists.01.org/mailman/listinfo/edk2-devel
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[edk2] [staging/edk2-test Patch V2] MdePkgUnitTest: Add UefiLib unit tests

[Kinney, Michael D]

Add UefiLib unit tests for the new API
EfiLocateProtocolBuffer().

Cc: Sean Brogan 
Cc: Liming Gao 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Michael D Kinney 
---
 MdePkgUnitTest/MdePkgUnitTest.dsc   |  17 +-
 MdePkgUnitTest/UefiLib/UefiLibUnitTests.c   | 266 
 MdePkgUnitTest/UefiLib/UefiLibUnitTests.inf |  46 +
 3 files changed, 328 insertions(+), 1 deletion(-)
 create mode 100644 MdePkgUnitTest/UefiLib/UefiLibUnitTests.c
 create mode 100644 MdePkgUnitTest/UefiLib/UefiLibUnitTests.inf

diff --git a/MdePkgUnitTest/MdePkgUnitTest.dsc 
b/MdePkgUnitTest/MdePkgUnitTest.dsc
index d98483020b..522464b545 100644
--- a/MdePkgUnitTest/MdePkgUnitTest.dsc
+++ b/MdePkgUnitTest/MdePkgUnitTest.dsc
@@ -1,7 +1,7 @@
 ## @file
 # This Package provides unit tests for the MdePkg
 #
-# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
 #
 # This program and the accompanying materials are licensed and made available 
under
 # the terms and conditions of the BSD License which accompanies this 
distribution.
@@ -33,6 +33,7 @@
   BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
   BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
   PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+
   DebugLib|MdePkg/Library/UefiDebugLibStdErr/UefiDebugLibStdErr.inf
   
DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
   PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
@@ -50,8 +51,22 @@
   
UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
   SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
 
+[PcdsFixedAtBuild]
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8047
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x1f
+
 [Components]
   MdePkgUnitTest/SafeIntLib/SafeIntLibUnitTests.inf {
 
   SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf
   }
+  MdePkgUnitTest/UefiLib/UefiLibUnitTests.inf {
+
+  UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+  }
+  MdePkgUnitTest/UefiLib/UefiLibUnitTests.inf {
+
+  FILE_GUID = 98286492-B21F-42CD-87BF-4DA8BF617CEB
+
+  UefiLib|IntelFrameworkPkg/Library/FrameworkUefiLib/FrameworkUefiLib.inf
+  }
diff --git a/MdePkgUnitTest/UefiLib/UefiLibUnitTests.c 
b/MdePkgUnitTest/UefiLib/UefiLibUnitTests.c
new file mode 100644
index 00..244715c2ca
--- /dev/null
+++ b/MdePkgUnitTest/UefiLib/UefiLibUnitTests.c
@@ -0,0 +1,266 @@
+/** @file
+  Uefi Shell based Application that Unit Tests the UefiLib
+
+  Copyright (c) 2018, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+
+#define UNIT_TEST_APP_NAMEL"Uefi Lib Unit Test Application"
+#define UNIT_TEST_APP_VERSION L"0.1"
+
+EFI_GUID  mUnitTestProtocolGuid = { 0xe5f282af, 0x895c, 0x4ece, { 0xae, 0xf0, 
0x19, 0xbf, 0x6f, 0xdd, 0x41, 0x2 } };
+
+//
+// Conversion function tests:
+//
+UNIT_TEST_STATUS
+EFIAPI
+TestEfiLocateProtocolBuffer (
+  IN UNIT_TEST_FRAMEWORK_HANDLE  Framework,
+  IN UNIT_TEST_CONTEXT   Context
+  )
+{
+  EFI_STATUS  Status;
+  UINTN   NoProtocols;
+  VOID**Buffer;
+  EFI_HANDLE  Handle1;
+  EFI_HANDLE  Handle2;
+  EFI_HANDLE  Handle3;
+  UINT32  Instance2;
+  UINT32  Instance3;
+
+  //
+  // NULL Protocol should result in EFI_INVALID_PARAMETER
+  //
+  Status = EfiLocateProtocolBuffer (NULL, , );
+  UT_ASSERT_EQUAL (EFI_INVALID_PARAMETER, Status);
+
+  //
+  // NULL NoProtocols should result in EFI_INVALID_PARAMETER
+  //
+  Status = EfiLocateProtocolBuffer (, NULL, );
+  UT_ASSERT_EQUAL (EFI_INVALID_PARAMETER, Status);
+
+  //
+  // NULL Buffer should result in EFI_INVALID_PARAMETER
+  //
+  Status = EfiLocateProtocolBuffer (, , NULL);
+  UT_ASSERT_EQUAL (EFI_INVALID_PARAMETER, Status);
+
+  //
+  // All NULL should result in EFI_INVALID_PARAMETER
+  //
+  Status = EfiLocateProtocolBuffer (NULL, NULL, NULL);
+  UT_ASSERT_EQUAL (EFI_INVALID_PARAMETER, Status);
+
+  //
+  // Request for unknown protocol should result in EFI_NOT_FOUND
+  //
+  NoProtocols = 0;
+  Buffer = NULL;
+  Status = EfiLocateProtocolBuffer (, , 
);
+  UT_ASSERT_EQUAL (EFI_NOT_FOUND, Status);
+
+  //
+  // Request for Loaded Image Protocol should result in EFI_SUCCESS
+  //
+  NoProtocols = 0;
+  Buffer = NULL;
+  Status = 

Re: [edk2] [PATCH 00/14] rid PiSmmCpuDxeSmm of DB-encoded instructions

[Kinney, Michael D]

Laszlo,

Thanks for all the work on this series and the very
detailed commit messages.

Liming's email on removing the .S and .asm files is an
RFC.  We need to see this RFC approved before we can
commit changes to remove .S and .asm files.  This should
be a separate activity.

One odd thing I see in this series is that the instruction
patch label in the .nasm file is just a label and does not
have any storage associated with it.  But in the C code
the type UINT8 is used with the label which implies some
storage.  Can we make the globals in C code be a pointer
(maybe VOID *) instead of UINT8?

Thanks,

Mike

> -Original Message-
> From: Laszlo Ersek [mailto:ler...@redhat.com]
> Sent: Friday, February 2, 2018 6:40 AM
> To: edk2-devel-01 
> Cc: Ard Biesheuvel ; Dong,
> Eric ; Yao, Jiewen
> ; Leif Lindholm
> ; Gao, Liming
> ; Kinney, Michael D
> ; Ni, Ruiyu
> 
> Subject: [PATCH 00/14] rid PiSmmCpuDxeSmm of DB-encoded
> instructions
> 
> Repo:   https://github.com/lersek/edk2.git
> Branch: patch_insn_x86
> 
> Patch 01 is a comment cleanup patch for "BaseLib.h".
> 
> Patch 02 introduces PatchInstructionX86() to BaseLib,
> based on the
> recent discussion.
> 
> Patch 03 removes *.S and *.asm files from PiSmmCpuDxeSmm,
> so that the
> rest of the series only needs to concern itself with
> *.nasm files. (The
> subject of removing *.S and *.asm files for x86 was
> broached by Liming
> on the list earlier; it's handy for this series.)
> 
> Patches 04 through 14 replace the DB encodings of
> instructions in
> PiSmmCpuDxeSmm NASM source code. Most of the time the new
> PatchInstructionX86() function is utilized, but in some
> cases, not even
> PatchInstructionX86() is needed.
> 
> Tested the following OSes with this series (all cases
> used -D
> SMM_REQUIRE, 2-4 VCPUs, both normal boot and S3, on KVM):
> 
> - IA32
>   - Fedora 26
> 
> - IA32X64
>   - Fedora 26
>   - Windows 7
>   - Windows 8.1
>   - Windows 10
>   - Windows Server 2008 R2
>   - Windows Server 2012 R2
>   - Windows Server 2016 (normal boot only -- S3 is
> untestable at this
> time due to QXL GPU driver signing issues)
> 
> Cc: Ard Biesheuvel 
> Cc: Eric Dong 
> Cc: Jiewen Yao 
> Cc: Leif Lindholm 
> Cc: Liming Gao 
> Cc: Michael D Kinney 
> Cc: Ruiyu Ni 
> 
> Thanks,
> Laszlo
> 
> Laszlo Ersek (14):
>   MdePkg/BaseLib.h: state preprocessing conditions in
> comments after
> #endifs
>   MdePkg/BaseLib: add PatchInstructionX86()
>   UefiCpuPkg/PiSmmCpuDxeSmm: remove *.S and *.asm
> assembly files
>   UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmbase" with
> PatchInstructionX86()
>   UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmiStack" with
> PatchInstructionX86()
>   UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmiCr3" with
> PatchInstructionX86()
>   UefiCpuPkg/PiSmmCpuDxeSmm: patch "XdSupported" with
> PatchInstructionX86()
>   UefiCpuPkg/PiSmmCpuDxeSmm: remove unneeded DBs from X64
> SmmStartup()
>   UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmmCr3" with
> PatchInstructionX86()
>   UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmmCr4" with
> PatchInstructionX86()
>   UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmmCr0" with
> PatchInstructionX86()
>   UefiCpuPkg/PiSmmCpuDxeSmm: eliminate "gSmmJmpAddr" and
> related DBs
>   UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmmInitStack" with
> PatchInstructionX86()
>   UefiCpuPkg/PiSmmCpuDxeSmm: remove DBs from
> SmmRelocationSemaphoreComplete32()
> 
>  MdePkg/Include/Library/BaseLib.h|  62 +-
>  MdePkg/Library/BaseLib/BaseLib.inf  |   2 +
>  MdePkg/Library/BaseLib/X86PatchInstruction.c|  89
> +++
>  UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c   |   4 +-
>  UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/MpFuncs.S| 165 --
> ---
>  UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/MpFuncs.asm  | 168 --
> ---
>  UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S   | 215 --
> 
>  UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm | 223 --
> 
>  UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm|  25 +-
>  UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.S   | 696 --
> -
>  UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.asm | 713 --
> --
>  UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.S|  84 --
> -
>  UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.asm  |  94 --
> -
>  UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm |  30 +-
>  UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c  |  27 +-
>  UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h  |  21 +-
>  UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf|  20 -
>  UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c  |   7 +
>  UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h  |   1 +
>  UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c 

[edk2] [Patch V2 2/3] IntelFrameworkPkg/FrameworkUefiLib: Add EfiLocateProtocolBuffer()

[Kinney, Michael D]

https://bugzilla.tianocore.org/show_bug.cgi?id=838

Add new API to the UefiLib that locates and returns
an array of protocols instances that match a given
protocol.

Cc: Sean Brogan 
Cc: Jiewen Yao 
Cc: Liming Gao 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Michael D Kinney 
---
 .../Library/FrameworkUefiLib/UefiLib.c | 112 -
 1 file changed, 111 insertions(+), 1 deletion(-)

diff --git a/IntelFrameworkPkg/Library/FrameworkUefiLib/UefiLib.c 
b/IntelFrameworkPkg/Library/FrameworkUefiLib/UefiLib.c
index 30b6dc9218..845f6ea173 100644
--- a/IntelFrameworkPkg/Library/FrameworkUefiLib/UefiLib.c
+++ b/IntelFrameworkPkg/Library/FrameworkUefiLib/UefiLib.c
@@ -5,7 +5,7 @@
   EFI Driver Model related protocols, manage Unicode string tables for UEFI 
Drivers, 
   and print messages on the console output and standard error devices.
 
-  Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -1475,3 +1475,113 @@ GetBestLanguage (
   //
   return NULL;
 }
+
+/**
+  Returns an array of protocol instance that matches the given protocol.
+
+  @param[in]  Protocol  Provides the protocol to search for.
+  @param[out] NoProtocols   The number of protocols returned in Buffer.
+  @param[out] BufferA pointer to the buffer to return the requested
+array of protocol instances that match Protocol.
+The returned buffer is allocated using
+EFI_BOOT_SERVICES.AllocatePool().  The caller is
+responsible for freeing this buffer with
+EFI_BOOT_SERVICES.FreePool().
+
+  @retval EFI_SUCCESSThe array of protocols was returned in Buffer,
+ and the number of protocols in Buffer was
+ returned in NoProtocols.
+  @retval EFI_NOT_FOUND  No protocols found.
+  @retval EFI_OUT_OF_RESOURCES   There is not enough pool memory to store the
+ matching results.
+  @retval EFI_INVALID_PARAMETER  Protocol is NULL.
+  @retval EFI_INVALID_PARAMETER  NoProtocols is NULL.
+  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiLocateProtocolBuffer (
+  IN  EFI_GUID  *Protocol,
+  OUT UINTN *NoProtocols,
+  OUT VOID  ***Buffer
+  )
+{
+  EFI_STATUS  Status;
+  UINTN   NoHandles;
+  EFI_HANDLE  *HandleBuffer;
+  UINTN   Index;
+
+  //
+  // Check input parameters
+  //
+  if (Protocol == NULL || NoProtocols == NULL || Buffer == NULL) {
+return EFI_INVALID_PARAMETER;
+  }
+
+  //
+  // Initialze output parameters
+  //
+  *NoProtocols = 0;
+  *Buffer = NULL;
+
+  //
+  // Retrieve the array of handles that support Protocol
+  //
+  Status = gBS->LocateHandleBuffer (
+  ByProtocol,
+  Protocol,
+  NULL,
+  ,
+  
+  );
+  if (EFI_ERROR (Status)) {
+return Status;
+  }
+
+  //
+  // Allocate array of protocol instances
+  //
+  Status = gBS->AllocatePool (
+  EfiBootServicesData,
+  NoHandles * sizeof (VOID *),
+  (VOID **)Buffer
+  );
+  if (EFI_ERROR (Status)) {
+return EFI_OUT_OF_RESOURCES;
+  }
+  ZeroMem (*Buffer, NoHandles * sizeof (VOID *));
+
+  //
+  // Lookup Protocol on each handle in HandleBuffer to fill in the array of
+  // protocol instances.  Handle case where protocol instance was present when
+  // LocateHandleBuffer() was called, but is not present when HandleProtocol()
+  // is called.
+  //
+  for (Index = 0, *NoProtocols = 0; Index < NoHandles; Index++) {
+Status = gBS->HandleProtocol (
+HandleBuffer[Index],
+Protocol,
+&((*Buffer)[*NoProtocols])
+);
+if (!EFI_ERROR (Status)) {
+  (*NoProtocols)++;
+}
+  }
+
+  //
+  // Free the handle buffer
+  //
+  gBS->FreePool (HandleBuffer);
+
+  //
+  // Make sure at least one protocol instance was found
+  //
+  if (*NoProtocols == 0) {
+gBS->FreePool (*Buffer);
+*Buffer = NULL;
+return EFI_NOT_FOUND;
+  }
+
+  return EFI_SUCCESS;
+}
-- 
2.14.2.windows.3

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[edk2] [Patch V2 1/3] MdePkg/UefiLib: Add EfiLocateProtocolBuffer()

[Kinney, Michael D]

From: Michael D Kinney 

https://bugzilla.tianocore.org/show_bug.cgi?id=838

Add new API to the UefiLib that locates and returns
an array of protocols instances that match a given
protocol.

Cc: Sean Brogan 
Cc: Jiewen Yao 
Cc: Liming Gao 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Michael D Kinney 
---
 MdePkg/Include/Library/UefiLib.h |  32 ++-
 MdePkg/Library/UefiLib/UefiLib.c | 112 ++-
 2 files changed, 142 insertions(+), 2 deletions(-)

diff --git a/MdePkg/Include/Library/UefiLib.h b/MdePkg/Include/Library/UefiLib.h
index 0b14792a0a..54bc2cc5a3 100644
--- a/MdePkg/Include/Library/UefiLib.h
+++ b/MdePkg/Include/Library/UefiLib.h
@@ -12,7 +12,7 @@
   of size reduction when compiler optimization is disabled. If MDEPKG_NDEBUG is
   defined, then debug and assert related macros wrapped by it are the NULL 
implementations.
 
-Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
 This program and the accompanying materials are licensed and made available 
under 
 the terms and conditions of the BSD License that accompanies this 
distribution.  
 The full text of the license may be found at
@@ -1490,4 +1490,34 @@ CatSPrint (
   ...
   );
 
+/**
+  Returns an array of protocol instance that matches the given protocol.
+
+  @param[in]  Protocol  Provides the protocol to search for.
+  @param[out] NoProtocols   The number of protocols returned in Buffer.
+  @param[out] BufferA pointer to the buffer to return the requested
+array of protocol instances that match Protocol.
+The returned buffer is allocated using
+EFI_BOOT_SERVICES.AllocatePool().  The caller is
+responsible for freeing this buffer with
+EFI_BOOT_SERVICES.FreePool().
+
+  @retval EFI_SUCCESSThe array of protocols was returned in Buffer,
+ and the number of protocols in Buffer was
+ returned in NoProtocols.
+  @retval EFI_NOT_FOUND  No protocols found.
+  @retval EFI_OUT_OF_RESOURCES   There is not enough pool memory to store the
+ matching results.
+  @retval EFI_INVALID_PARAMETER  Protocol is NULL.
+  @retval EFI_INVALID_PARAMETER  NoProtocols is NULL.
+  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiLocateProtocolBuffer (
+  IN  EFI_GUID  *Protocol,
+  OUT UINTN *NoProtocols,
+  OUT VOID  ***Buffer
+  );
 #endif
diff --git a/MdePkg/Library/UefiLib/UefiLib.c b/MdePkg/Library/UefiLib/UefiLib.c
index a7eee01240..f1a3f1c7af 100644
--- a/MdePkg/Library/UefiLib/UefiLib.c
+++ b/MdePkg/Library/UefiLib/UefiLib.c
@@ -5,7 +5,7 @@
   EFI Driver Model related protocols, manage Unicode string tables for UEFI 
Drivers, 
   and print messages on the console output and standard error devices.
 
-  Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -1605,3 +1605,113 @@ GetBestLanguage (
   //
   return NULL;
 }
+
+/**
+  Returns an array of protocol instance that matches the given protocol.
+
+  @param[in]  Protocol  Provides the protocol to search for.
+  @param[out] NoProtocols   The number of protocols returned in Buffer.
+  @param[out] BufferA pointer to the buffer to return the requested
+array of protocol instances that match Protocol.
+The returned buffer is allocated using
+EFI_BOOT_SERVICES.AllocatePool().  The caller is
+responsible for freeing this buffer with
+EFI_BOOT_SERVICES.FreePool().
+
+  @retval EFI_SUCCESSThe array of protocols was returned in Buffer,
+ and the number of protocols in Buffer was
+ returned in NoProtocols.
+  @retval EFI_NOT_FOUND  No protocols found.
+  @retval EFI_OUT_OF_RESOURCES   There is not enough pool memory to store the
+ matching results.
+  @retval EFI_INVALID_PARAMETER  Protocol is NULL.
+  @retval EFI_INVALID_PARAMETER  NoProtocols is NULL.
+  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiLocateProtocolBuffer (
+  IN  EFI_GUID  *Protocol,
+  OUT UINTN *NoProtocols,
+  OUT VOID  ***Buffer
+  )
+{
+  EFI_STATUS  Status;
+  UINTN   

[edk2] [Patch V2 3/3] IntelFrameworkPkg/FrameworkUefiLib: Sync with MdePkg/UefiLib

[Kinney, Michael D]

Add functions that have been added to MdePkg/UefiLib.

* GetVariable2()
* GetEfiGlobalVariable2

Cc: Sean Brogan 
Cc: Jiewen Yao 
Cc: Liming Gao 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Michael D Kinney 
---
 .../Library/FrameworkUefiLib/UefiLib.c | 102 +
 1 file changed, 102 insertions(+)

diff --git a/IntelFrameworkPkg/Library/FrameworkUefiLib/UefiLib.c 
b/IntelFrameworkPkg/Library/FrameworkUefiLib/UefiLib.c
index 845f6ea173..895ff39fc1 100644
--- a/IntelFrameworkPkg/Library/FrameworkUefiLib/UefiLib.c
+++ b/IntelFrameworkPkg/Library/FrameworkUefiLib/UefiLib.c
@@ -1338,6 +1338,108 @@ GetEfiGlobalVariable (
   return GetVariable (Name, );
 }
 
+/**
+  Returns the status whether get the variable success. The function retrieves
+  variable  through the UEFI Runtime Service GetVariable().  The
+  returned buffer is allocated using AllocatePool().  The caller is responsible
+  for freeing this buffer with FreePool().
+
+  If Name  is NULL, then ASSERT().
+  If Guid  is NULL, then ASSERT().
+  If Value is NULL, then ASSERT().
+
+  @param[in]  Name  The pointer to a Null-terminated Unicode string.
+  @param[in]  Guid  The pointer to an EFI_GUID structure
+  @param[out] Value The buffer point saved the variable info.
+  @param[out] Size  The buffer size of the variable.
+
+  @return EFI_OUT_OF_RESOURCES  Allocate buffer failed.
+  @return EFI_SUCCESS   Find the specified variable.
+  @return Others Errors Return errors from call to 
gRT->GetVariable.
+
+**/
+EFI_STATUS
+EFIAPI
+GetVariable2 (
+  IN CONST CHAR16*Name,
+  IN CONST EFI_GUID  *Guid,
+  OUT VOID   **Value,
+  OUT UINTN  *Size OPTIONAL
+  )
+{
+  EFI_STATUS  Status;
+  UINTN   BufferSize;
+
+  ASSERT (Name != NULL && Guid != NULL && Value != NULL);
+
+  //
+  // Try to get the variable size.
+  //
+  BufferSize = 0;
+  *Value = NULL;
+  if (Size != NULL) {
+*Size  = 0;
+  }
+
+  Status = gRT->GetVariable ((CHAR16 *) Name, (EFI_GUID *) Guid, NULL, 
, *Value);
+  if (Status != EFI_BUFFER_TOO_SMALL) {
+return Status;
+  }
+
+  //
+  // Allocate buffer to get the variable.
+  //
+  *Value = AllocatePool (BufferSize);
+  ASSERT (*Value != NULL);
+  if (*Value == NULL) {
+return EFI_OUT_OF_RESOURCES;
+  }
+
+  //
+  // Get the variable data.
+  //
+  Status = gRT->GetVariable ((CHAR16 *) Name, (EFI_GUID *) Guid, NULL, 
, *Value);
+  if (EFI_ERROR (Status)) {
+FreePool(*Value);
+*Value = NULL;
+  }
+
+  if (Size != NULL) {
+*Size = BufferSize;
+  }
+
+  return Status;
+}
+
+/**
+  Returns a pointer to an allocated buffer that contains the contents of a
+  variable retrieved through the UEFI Runtime Service GetVariable().  This
+  function always uses the EFI_GLOBAL_VARIABLE GUID to retrieve variables.
+  The returned buffer is allocated using AllocatePool().  The caller is
+  responsible for freeing this buffer with FreePool().
+
+  If Name is NULL, then ASSERT().
+  If Value is NULL, then ASSERT().
+
+  @param[in]  Name  The pointer to a Null-terminated Unicode string.
+  @param[out] Value The buffer point saved the variable info.
+  @param[out] Size  The buffer size of the variable.
+
+  @return EFI_OUT_OF_RESOURCES  Allocate buffer failed.
+  @return EFI_SUCCESS   Find the specified variable.
+  @return Others Errors Return errors from call to 
gRT->GetVariable.
+
+**/
+EFI_STATUS
+EFIAPI
+GetEfiGlobalVariable2 (
+  IN CONST CHAR16*Name,
+  OUT VOID   **Value,
+  OUT UINTN  *Size OPTIONAL
+  )
+{
+  return GetVariable2 (Name, , Value, Size);
+}
 
 /**
   Returns a pointer to an allocated buffer that contains the best matching 
language 
-- 
2.14.2.windows.3

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[edk2] [Patch V2 0/3] MdePkg/UefiLib: Add EfiLocateProtocolBuffer()

[Kinney, Michael D]

V2:
* Use gBS->AllocatePool() instead of AllocatePool()
* Use gBS->FreePool() instead of FreePool()
* Add EfiLocateProtocolBuffer() to IntelFrameworkPkg/FrameworkUefiLib
* Add GetVariable2() to IntelFrameworkPkg/FrameworkUefiLib
* Add GetEfiGlobalVariable2 to IntelFrameworkPkg/FrameworkUefiLib

https://bugzilla.tianocore.org/show_bug.cgi?id=838

Add new API to the UefiLib that locates and returns
an array of protocols instances that match a given
protocol.

Branch for review:

https://github.com/mdkinney/edk2/tree/Bug_838_EfiLocateProtocolBuffer_V4

Cc: Sean Brogan 
Cc: Jiewen Yao 
Cc: Liming Gao 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Michael D Kinney 

Kinney, Michael D (2):
  IntelFrameworkPkg/FrameworkUefiLib: Add EfiLocateProtocolBuffer()
  IntelFrameworkPkg/FrameworkUefiLib: Sync with MdePkg/UefiLib

Michael D Kinney (1):
  MdePkg/UefiLib: Add EfiLocateProtocolBuffer()

 .../Library/FrameworkUefiLib/UefiLib.c | 214 -
 MdePkg/Include/Library/UefiLib.h   |  32 ++-
 MdePkg/Library/UefiLib/UefiLib.c   | 112 ++-
 3 files changed, 355 insertions(+), 3 deletions(-)

-- 
2.14.2.windows.3

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Re: [edk2] MinPlatformPkg/PlatformInit: FV code

[Yao, Jiewen]

Ah, good catch.

That is correct - it is irrelevant to PEI. To put to FV Hob is enough, I 
believe.

Appreciate your careful review, which helps us clean up the code. :-)

Thank you
Yao Jiewen


> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
> Marvin H?user
> Sent: Saturday, February 3, 2018 2:30 AM
> To: edk2-devel@lists.01.org; Yao, Jiewen 
> Subject: Re: [edk2] MinPlatformPkg/PlatformInit: FV code
> 
> Good point with the DxeCore, I didn't consider that. Though OsBoot would be
> irrelevant to the PEI phase, wouldn't it be?
> 
> Thanks,
> Marvin
> 
> From: Yao, Jiewen [mailto:jiewen@intel.com]
> Sent: Friday, February 2, 2018 1:40 PM
> To: Marvin H?user ; edk2-devel@lists.01.org
> Subject: RE: MinPlatformPkg/PlatformInit: FV code
> 
> Excellent question.
> 
> Comment inline.
> 
> From: Marvin H?user [mailto:marvin.haeu...@outlook.com]
> Sent: Wednesday, January 31, 2018 1:54 AM
> To: edk2-devel@lists.01.org; Yao, Jiewen
> >
> Subject: MinPlatformPkg/PlatformInit: FV code
> 
> Dear developers, dear Jiewen,
> 
> I have been investigating the devel-MinPlatform branch of edk2-platforms for
> educational purposes and got two questions regarding the Firmware Volume
> code in PlatformInitPreMem, if you do not mind. I assume the tree was tested, 
> so
> most likely I misunderstood some things.
> 
> 
>   1.  Why is a Firmware Volume HOB built to cover the entire flash range
> (https://github.com/tianocore/edk2-platforms/blob/devel-MinPlatform/Platfor
> m/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c#L3
> 79)? Am I correct that this implies a FV spanning through the entire flash 
> MMIO
> range, which would then imply all other FVs are contained within it? This 
> would
> make sense, however that's not what I saw in the KabylakeOpenBoardPkg Flash
> Map, which has the NV Storage first
> (https://github.com/tianocore/edk2-platforms/blob/devel-MinPlatform/Platfor
> m/Intel/KabylakeOpenBoardPkg/Include/Fdf/FlashMapInclude.fdf#L25).
> 
> [Jiewen] You are right. We should not use FD region for FV. Will fix it.
> 
> 
> 
>   1.  Why are FV Info PPIs installed for the UefiBoot and the OsBoot FVs
> (https://github.com/tianocore/edk2-platforms/blob/devel-MinPlatform/Platfor
> m/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c#L3
> 44)? If I checked correctly, installing this PPI type will trigger PeiCore to 
> dispatch
> PEIMs in the FVs, however there are only DXE drivers in these. Why are no FV
> HOBs installed, which are gotten by DxeCore?
> 
> [Jiewen] In DxeIpl, PeiServicesFfsFindNextVolume() is used to search DxeCore.
> In PeiCore, PeiFfsFindNextVolume() calls FindNextCoreFvHandle() for DxeCore
> one by one. If PcdFrameworkCompatibilitySupport is FALSE, it returns
> >Fv[Instance] directly.
> 
> And Fv[Instance] is added in FirmwareVolmeInfoPpiNotifyCallback(), when
> gEfiPeiFirmwareVolumeInfo2PpiGuid is installed.
> 
> So if PcdFrameworkCompatibilitySupport is FALSE, install PPI is the only way 
> to
> let PEI core discover DxeCore.
> Only if PcdFrameworkCompatibilitySupport is TRUE, install PPI is not required,
> but the FindNextCoreFvHandle() will install the PPI for the HobFv. The result 
> is
> same.
> 
> 
> Thank you
> Yao Jiewen
> 
> 
> 
> 
> Thanks in advance for your time!
> 
> Best regards,
> Marvin.
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[edk2] [EDK2] How to use compiler intrinsic function, such as :mmintrin.h

[Tiger Liu(BJ-RD)]

Hi, experts:
I have a question about using compiler's intrinsic function.
It seems EDKII's compiler option doesn't support using intrinsic function.

Such as:
mmintrin.h  MMX
xmmintrin.hSSE
emmintrin.h   SSE2
pmmintrin.h   SSE3
tmmintrin.hSSSE3
intrin.h SSE4A
smmintrin.h   SSE4.1
nmmintrin.h   SSE4.2
mm3dnow.h  3DNOW

Thanks

Best wishes,


?
?
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[edk2] [Patch] BaseTools: enhance error check for DatumType format

[Yonghong Zhu]

Add a check for DatumType format, eg: VOID *, original Tool will crash
but no detail error message which cause confusion to user.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Yonghong Zhu 
---
 BaseTools/Source/Python/Workspace/DecBuildData.py | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/BaseTools/Source/Python/Workspace/DecBuildData.py 
b/BaseTools/Source/Python/Workspace/DecBuildData.py
index 2fd3820..2266b0b 100644
--- a/BaseTools/Source/Python/Workspace/DecBuildData.py
+++ b/BaseTools/Source/Python/Workspace/DecBuildData.py
@@ -1,9 +1,9 @@
 ## @file
 # This file is used to create a database used by build tool
 #
-# Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.
 # (C) Copyright 2016 Hewlett Packard Enterprise Development LP
 # This program and the accompanying materials
 # are licensed and made available under the terms and conditions of the BSD 
License
 # which accompanies this distribution.  The full text of the license may be 
found at
 # http://opensource.org/licenses/bsd-license.php
@@ -421,10 +421,15 @@ class DecBuildData(PackageBuildClassObject):
 Setting,LineNo = PcdDict[self._Arch, PcdCName, TokenSpaceGuid]
 if Setting == None:
 continue
 
 DefaultValue, DatumType, TokenNumber = AnalyzePcdData(Setting)
+if DatumType not in [TAB_UINT8, TAB_UINT16, TAB_UINT32, 
TAB_UINT64, TAB_VOID, "BOOLEAN"]:
+StructPattern = re.compile(r'[_a-zA-Z][0-9A-Za-z_]*$')
+if StructPattern.match(DatumType) == None:
+EdkLogger.error('build', FORMAT_INVALID, "DatumType only 
support BOOLEAN, UINT8, UINT16, UINT32, UINT64, VOID* or a valid struct name.", 
File=self.MetaFile, Line=LineNo)
+
 validateranges, validlists, expressions = 
self._RawData.GetValidExpression(TokenSpaceGuid, PcdCName)
 PcdObj = PcdClassObject(
 PcdCName,
 TokenSpaceGuid,
 self._PCD_TYPE_STRING_[Type],
-- 
2.6.1.windows.1

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[edk2] [PATCH v3 1/8] MdeModulePkg:Add definitions for new Performance infrastructure

[Dandan Bi]

From: "Gao, Liming" 

V3:
Add "FPDT_" prefix for related definitions.

Cc: Liming Gao 
Cc: Star Zeng 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao 
Signed-off-by: Dandan Bi 
---
 .../Include/Guid/ExtendedFirmwarePerformance.h | 291 +
 MdeModulePkg/Include/Guid/FirmwarePerformance.h|  13 +-
 MdeModulePkg/MdeModulePkg.dec  |  11 +-
 MdeModulePkg/MdeModulePkg.uni  |   8 +-
 4 files changed, 320 insertions(+), 3 deletions(-)
 create mode 100644 MdeModulePkg/Include/Guid/ExtendedFirmwarePerformance.h

diff --git a/MdeModulePkg/Include/Guid/ExtendedFirmwarePerformance.h 
b/MdeModulePkg/Include/Guid/ExtendedFirmwarePerformance.h
new file mode 100644
index 000..f2db02d
--- /dev/null
+++ b/MdeModulePkg/Include/Guid/ExtendedFirmwarePerformance.h
@@ -0,0 +1,291 @@
+/** @file
+  This file defines edk2 extended firmware performance records.
+  These records will be added into ACPI FPDT Firmware Basic Boot Performance 
Table.
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available 
under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __EXTENDED_FIRMWARE_PERFORMANCE_H__
+#define __EXTENDED_FIRMWARE_PERFORMANCE_H__
+
+#include 
+
+//
+// Known performance tokens
+//
+#define SEC_TOK "SEC" ///< SEC Phase
+#define DXE_TOK "DXE" ///< DXE Phase
+#define PEI_TOK "PEI" ///< PEI Phase
+#define BDS_TOK "BDS" ///< BDS Phase
+#define DRIVERBINDING_START_TOK "DB:Start:"   ///< Driver Binding 
Start() function call
+#define DRIVERBINDING_SUPPORT_TOK   "DB:Support:" ///< Driver Binding 
Support() function call
+#define DRIVERBINDING_STOP_TOK  "DB:Stop:"///< Driver Binding 
Stop() function call
+#define LOAD_IMAGE_TOK  "LoadImage:"  ///< Load a 
dispatched module
+#define START_IMAGE_TOK "StartImage:" ///< Dispatched 
Modules Entry Point execution
+#define PEIM_TOK"PEIM"///< PEIM Modules 
Entry Point execution
+
+//
+// Public Progress Identifiers for Event Records to map the above known token
+//
+#define MODULE_START_ID 0x01
+#define MODULE_END_ID   0x02
+#define MODULE_LOADIMAGE_START_ID   0x03
+#define MODULE_LOADIMAGE_END_ID 0x04
+#define MODULE_DB_START_ID  0x05
+#define MODULE_DB_END_ID0x06
+#define MODULE_DB_SUPPORT_START_ID  0x07
+#define MODULE_DB_SUPPORT_END_ID0x08
+#define MODULE_DB_STOP_START_ID 0x09
+#define MODULE_DB_STOP_END_ID   0x0A
+
+#define PERF_EVENTSIGNAL_START_ID   0x10
+#define PERF_EVENTSIGNAL_END_ID 0x11
+#define PERF_CALLBACK_START_ID  0x20
+#define PERF_CALLBACK_END_ID0x21
+#define PERF_FUNCTION_START_ID  0x30
+#define PERF_FUNCTION_END_ID0x31
+#define PERF_INMODULE_START_ID  0x40
+#define PERF_INMODULE_END_ID0x41
+#define PERF_CROSSMODULE_START_ID   0x50
+#define PERF_CROSSMODULE_END_ID 0x51
+
+//
+// Misc defines
+//
+#define FPDT_RECORD_REVISION_1  (0x01)
+
+//
+// Length field in EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER is a UINT8, 
thus:
+//
+#define FPDT_MAX_PERF_RECORD_SIZE   (MAX_UINT8)
+
+//
+// FPDT Record Types
+//
+#define FPDT_GUID_EVENT_TYPE   0x1010
+#define FPDT_DYNAMIC_STRING_EVENT_TYPE 0x1011
+#define FPDT_DUAL_GUID_STRING_EVENT_TYPE   0x1012
+#define FPDT_GUID_QWORD_EVENT_TYPE 0x1013
+#define FPDT_GUID_QWORD_STRING_EVENT_TYPE  0x1014
+
+//
+// EDKII extended Fpdt record structures
+//
+#define FPDT_STRING_EVENT_RECORD_NAME_LENGTH 24
+
+#pragma pack(1)
+//
+// FPDT Boot Performance Guid Event Record Structure
+//
+typedef struct {
+  EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER Header;
+  ///
+  /// ProgressID < 0x10 are reserved for core performance entries.
+  /// Start measurement point shall have lowered one nibble set to zero and
+  /// corresponding end points shall have lowered one nibble set to non-zero 
value;
+  /// keeping other nibbles same as start point.
+  ///
+  UINT16  ProgressID;
+  ///
+  /// APIC ID for the processor in the system used as a timestamp clock source.
+  /// If only one timestamp clock source is used, this field is Reserved and 
populated as 0.
+  ///
+  UINT32

[edk2] [PATCH v3 0/8] Update EDKII Performance infrastructure based on ACPI FPDT table

[Dandan Bi]

V3:
a. Add "FPDT_" prefix for related definitions in ExtendedFirmwarePerformance.h.
b. Refine the code logic.

V2:
a. Update DxecorePerformanceLib/SmmCorePerformanceLib to report the
boot performance table address instead of records contents.
b. Update FirmwarePerformanceDxe/FirmwarePerformanceSmm to receive the address
of performance records.

This patch series also can be accessed at:
https://github.com/dandanbi/edk2/tree/NewPerformanceInfrastructureV3

These patches are to update EDKII performance infrastructure to log and dump
the performance entry as FPDT record in ACPI FPDT table.This new infrastructure
can support to dump performance data in UEFI Shell and OS both.
(1)PeiPerformanceLib/DxeCorePerformanceLib/SmmCorePerformanceLib log the
performance entry as FPDT record.
(2)FirmwarePerformancePei/FirmwarePerformanceDxe/FirmwarePerformanceSmm
install the FPDT records to the ACPI table.
(3)Update DP to dump the performance info from the FPDT records in
FPDT table.

Cc: Liming Gao 
Cc: Star Zeng 
Dandan Bi (7):
  MdeModulePkg/PeiPerformance:Updated to track FPDT record in PEI phase
  MdeModulePkg/DxeCorePerformanceLib:Track FPDT record in DXE phase
  MdeModulePkg/SmmCorePerformanceLib:Track FPDT record in SMM phase
  MdeModulePkg/FirmwarePerformancePei:Add FPDT records for S3 phase
  MdeModulePkg/FirmwarePerfDxe:Enhance for new pref infrastructure
  MdeModulePkg/FirmwarePerfSmm:Enhance for new pref infrastructure
  ShellPkg/Dp: Updated to dump perf log based on FPDT table

Gao, Liming (1):
  MdeModulePkg:Add definitions for new Performance infrastructure

 .../Include/Guid/ExtendedFirmwarePerformance.h |  291 +
 MdeModulePkg/Include/Guid/FirmwarePerformance.h|   13 +-
 .../DxeCorePerformanceLib/DxeCorePerformanceLib.c  | 1361 +++-
 .../DxeCorePerformanceLib.inf  |   20 +-
 .../DxeCorePerformanceLibInternal.h|   17 +-
 .../Library/PeiPerformanceLib/PeiPerformanceLib.c  |  567 +---
 .../PeiPerformanceLib/PeiPerformanceLib.inf|   14 +-
 .../SmmCorePerformanceLib/SmmCorePerformanceLib.c  | 1068 ---
 .../SmmCorePerformanceLib.inf  |   10 +-
 .../SmmCorePerformanceLibInternal.h|   11 +-
 MdeModulePkg/MdeModulePkg.dec  |   11 +-
 MdeModulePkg/MdeModulePkg.uni  |8 +-
 .../FirmwarePerformanceDxe.c   |  294 +
 .../FirmwarePerformanceDxe.inf |4 +-
 .../FirmwarePerformancePei.c   |   59 +-
 .../FirmwarePerformancePei.inf |5 +-
 .../FirmwarePerformanceSmm.c   |   35 +-
 .../FirmwarePerformanceSmm.inf |1 +
 ShellPkg/DynamicCommand/DpDynamicCommand/Dp.c  |  609 -
 ShellPkg/DynamicCommand/DpDynamicCommand/Dp.h  |7 +-
 ShellPkg/DynamicCommand/DpDynamicCommand/Dp.uni|   11 +-
 ShellPkg/DynamicCommand/DpDynamicCommand/DpApp.inf |5 +-
 .../DpDynamicCommand/DpDynamicCommand.inf  |5 +-
 .../DynamicCommand/DpDynamicCommand/DpInternal.h   |9 +-
 ShellPkg/DynamicCommand/DpDynamicCommand/DpTrace.c |  108 +-
 .../DynamicCommand/DpDynamicCommand/DpUtilities.c  |   37 +-
 .../DynamicCommand/DpDynamicCommand/Literals.c |   24 +-
 .../DynamicCommand/DpDynamicCommand/Literals.h |8 +-
 .../DpDynamicCommand/PerformanceTokens.h   |   28 -
 29 files changed, 3278 insertions(+), 1362 deletions(-)
 create mode 100644 MdeModulePkg/Include/Guid/ExtendedFirmwarePerformance.h
 delete mode 100644 ShellPkg/DynamicCommand/DpDynamicCommand/PerformanceTokens.h

-- 
1.9.5.msysgit.1

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[edk2] [PATCH] BaseTools: Update Expression.py for VOID* support L'a' and 'a'

[Feng, YunhuaX]

Type VOID* support L'a' and 'a', the value transfer to c style value.
L'a' --> {0x61, 0x00}
L'ab' --> {0x61, 0x00, 0x62, 0x00}
'a'  --> {0x61}
'ab' --> {0x61, 0x62}

when the value is L'' or '', will report error

Cc: Liming Gao 
Cc: Yonghong Zhu 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Yunhua Feng 
---
 BaseTools/Source/Python/Common/Expression.py | 19 ---
 BaseTools/Source/Python/Common/Misc.py   |  4 
 2 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/BaseTools/Source/Python/Common/Expression.py 
b/BaseTools/Source/Python/Common/Expression.py
index b8c48460ff..6a1103df2c 100644
--- a/BaseTools/Source/Python/Common/Expression.py
+++ b/BaseTools/Source/Python/Common/Expression.py
@@ -740,7 +740,12 @@ class ValueExpressionEx(ValueExpression):
 try:
 PcdValue = ValueExpression.__call__(self, RealValue, Depth)
 if self.PcdType == 'VOID*' and (PcdValue.startswith("'") or 
PcdValue.startswith("L'")):
-raise BadExpression
+PcdValue, Size = ParseFieldValue(PcdValue)
+PcdValueList = []
+for I in range(Size):
+PcdValueList.append('0x%02X'%(PcdValue & 0xff))
+PcdValue = PcdValue >> 8
+PcdValue = '{' + ','.join(PcdValueList) + '}'
 elif self.PcdType in ['UINT8', 'UINT16', 'UINT32', 'UINT64', 
'BOOLEAN'] and (PcdValue.startswith("'") or \
   PcdValue.startswith('"') or PcdValue.startswith("L'") or 
PcdValue.startswith('L"') or PcdValue.startswith('{')):
 raise BadExpression
@@ -755,6 +760,8 @@ class ValueExpressionEx(ValueExpression):
 TmpValue = 0
 Size = 0
 for Item in PcdValue:
+if Item.startswith('UINT8'):
+ItemSize = 1
 if Item.startswith('UINT16'):
 ItemSize = 2
 elif Item.startswith('UINT32'):
@@ -776,7 +783,10 @@ class ValueExpressionEx(ValueExpression):
 TmpValue = (ItemValue << (Size * 8)) | TmpValue
 Size = Size + ItemSize
 else:
-TmpValue, Size = ParseFieldValue(PcdValue)
+try:
+TmpValue, Size = ParseFieldValue(PcdValue)
+except BadExpression:
+raise BadExpression("Type: %s, Value: %s, format or 
value error" % (self.PcdType, PcdValue))
 if type(TmpValue) == type(''):
 TmpValue = int(TmpValue)
 else:
@@ -858,7 +868,7 @@ class ValueExpressionEx(ValueExpression):
 else:
 raise BadExpression('%s not defined 
before use' % Offset)
 ValueType = ""
-if Item.startswith('UINT16'):
+if Item.startswith('UINT8'):
 ItemSize = 1
 ValueType = "UINT8"
 elif Item.startswith('UINT16'):
@@ -887,6 +897,9 @@ class ValueExpressionEx(ValueExpression):
 
 if Size > 0:
 PcdValue = '{' + ValueStr[:-2] + '}'
+else:
+raise  BadExpression("Type: %s, Value: %s, format or 
value error"%(self.PcdType, PcdValue))
+
 if PcdValue == 'True':
 PcdValue = '1'
 if PcdValue == 'False':
diff --git a/BaseTools/Source/Python/Common/Misc.py 
b/BaseTools/Source/Python/Common/Misc.py
index b34cb4c3be..d80f645d2e 100644
--- a/BaseTools/Source/Python/Common/Misc.py
+++ b/BaseTools/Source/Python/Common/Misc.py
@@ -1572,6 +1572,8 @@ def ParseFieldValue (Value):
 if Value.startswith("L'") and Value.endswith("'"):
 # Unicode Character Constant
 List = list(Value[2:-1])
+if len(List) == 0:
+raise BadExpression('Length %s is %s' % (Value, len(List)))
 List.reverse()
 Value = 0
 for Char in List:
@@ -1580,6 +1582,8 @@ def ParseFieldValue (Value):
 if Value.startswith("'") and Value.endswith("'"):
 # Character constant
 List = list(Value[1:-1])
+if len(List) == 0:
+raise BadExpression('Length %s is %s' % (Value, len(List)))
 List.reverse()
 Value = 0
 for Char in List:
-- 
2.12.2.windows.2

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Re: [edk2] [RFC] MdeModulePkg/PciHostBridgeDxe: Add support for address translation

[Ard Biesheuvel]

On 2 February 2018 at 00:34, Ni, Ruiyu  wrote:
>
>
>> -Original Message-
>> From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org]
>> Sent: Friday, February 2, 2018 1:23 AM
>> To: Ni, Ruiyu 
>> Cc: Guo Heyi ,Dong Wei ; Dong,
>> Eric ; edk2-devel@lists.01.org; linaro-uefi > u...@lists.linaro.org>; Kinney, Michael D ; Zeng,
>> Star 
>> Subject: Re: [edk2] [RFC] MdeModulePkg/PciHostBridgeDxe: Add support for
>> address translation
>>
>> On 1 February 2018 at 05:03, Ni, Ruiyu  wrote:
>> > On 1/29/2018 4:50 PM, Guo Heyi wrote:
>> >>
>> >> Sorry for the late; I caught cold and didn't work for several days
>> >> last week :( Please see my comments below:
>> >>
>> >>
>> >> On Mon, Jan 22, 2018 at 11:36:14AM +0800, Ni, Ruiyu wrote:
>> >>>
>> >>> On 1/18/2018 9:26 AM, Guo Heyi wrote:
>> 
>>  On Wed, Jan 17, 2018 at 02:08:06PM +, Ard Biesheuvel wrote:
>> >
>> > On 15 January 2018 at 14:46, Heyi Guo  wrote:
>> >>
>> >> This is the draft patch for the discussion posted in edk2-devel
>> >> mailing list:
>> >> https://lists.01.org/pipermail/edk2-devel/2017-December/019289.ht
>> >> ml
>> >>
>> >> As discussed in the mailing list, we'd like to add support for
>> >> PCI address translation which is necessary for some non-x86
>> >> platforms. I also want to minimize the changes to the generic
>> >> host bridge driver and platform PciHostBridgeLib implemetations,
>> >> so additional two interfaces are added to expose translation
>> >> information of the platform. To be generic, I add translation for
>> >> each type of IO or memory resources.
>> >>
>> >> The patch is still a RFC, so I only passed the build for qemu64
>> >> and the function has not been tested yet.
>> >>
>> >> Please let me know your comments about it.
>> >>
>> >> Thanks.
>> >>
>> >> Contributed-under: TianoCore Contribution Agreement 1.1
>> >> Signed-off-by: Heyi Guo 
>> >> Cc: Ruiyu Ni 
>> >> Cc: Ard Biesheuvel 
>> >> Cc: Star Zeng 
>> >> Cc: Eric Dong 
>> >> ---
>> >>   .../FdtPciHostBridgeLib/FdtPciHostBridgeLib.c  |  19 
>> >>   .../Bus/Pci/PciHostBridgeDxe/PciHostBridge.c   |  53 ---
>> >>   .../Bus/Pci/PciHostBridgeDxe/PciRootBridge.h   |   8 +-
>> >>   .../Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 101
>> >> ++---
>> >>   MdeModulePkg/Include/Library/PciHostBridgeLib.h|  36 
>> >>   5 files changed, 192 insertions(+), 25 deletions(-)
>> >>
>> >> diff --git
>> >> a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c
>> >> b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c
>> >> index 5b9c887..0c8371a 100644
>> >> ---
>> >> a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c
>> >> +++ b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.
>> >> +++ c
>> >> @@ -360,6 +360,16 @@ PciHostBridgeGetRootBridges (
>> >> return 
>> >>   }
>> >>
>> >> +PCI_ROOT_BRIDGE_TRANSLATION *
>> >> +EFIAPI
>> >> +PciHostBridgeGetTranslations (
>> >> +  UINTN *Count
>> >> +  )
>> >> +{
>> >> +  *Count = 0;
>> >> +  return NULL;
>> >> +}
>> >> +
>> >>   /**
>> >> Free the root bridge instances array returned from
>> >> PciHostBridgeGetRootBridges().
>> >> @@ -377,6 +387,15 @@ PciHostBridgeFreeRootBridges (
>> >> ASSERT (Count == 1);
>> >>   }
>> >>
>> >> +VOID
>> >> +EFIAPI
>> >> +PciHostBridgeFreeTranslations (
>> >> +  PCI_ROOT_BRIDGE_TRANSLATION *Translations,
>> >> +  UINTN   Count
>> >> +  )
>> >> +{
>> >> +}
>> >> +
>> >>   /**
>> >> Inform the platform that the resource conflict happens.
>> >>
>> >> diff --git
>> >> asame/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c
>> >> b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c
>> >> index 1494848..835e411 100644
>> >> --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c
>> >> +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c
>> >> @@ -360,18 +360,38 @@ InitializePciHostBridge (
>> >> PCI_HOST_BRIDGE_INSTANCE*HostBridge;
>> >> PCI_ROOT_BRIDGE_INSTANCE*RootBridge;
>> >> PCI_ROOT_BRIDGE *RootBridges;
>> >> +  PCI_ROOT_BRIDGE_TRANSLATION *Translations;
>> >> UINTN   RootBridgeCount;
>> >> +  UINTN   TranslationCount;
>> >> UINTN   Index;
>> >> PCI_ROOT_BRIDGE_APERTURE

[edk2] [PATCH v3 3/8] MdeModulePkg/DxeCorePerformanceLib:Track FPDT record in DXE phase

[Dandan Bi]

V3:
a. Handle the case when string is empty in String Record.
b. refine the code logic.

V2:
Update DxecorePerformanceLib to report the boot performance table
address instead of records contents.

Updated to convert Pref entry to FPDT record in DXE phase and then
allocate boot performance table to save the record and report
the address of boot performance table to FirmwarePerformanceDxe.

Cc: Liming Gao 
Cc: Star Zeng 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Dandan Bi 
---
 .../DxeCorePerformanceLib/DxeCorePerformanceLib.c  | 1361 +++-
 .../DxeCorePerformanceLib.inf  |   20 +-
 .../DxeCorePerformanceLibInternal.h|   17 +-
 3 files changed, 1080 insertions(+), 318 deletions(-)

diff --git a/MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.c 
b/MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.c
index 7c0e207..44d3bd1 100644
--- a/MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.c
+++ b/MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.c
@@ -8,11 +8,11 @@
   which are consumed by DxePerformanceLib to logging performance data in DXE 
phase.
 
   This library is mainly used by DxeCore to start performance logging to 
ensure that
   Performance Protocol is installed at the very beginning of DXE phase.
 
-Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
 (C) Copyright 2016 Hewlett Packard Enterprise Development LP
 This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD 
License
 which accompanies this distribution.  The full text of the license may be 
found at
 http://opensource.org/licenses/bsd-license.php
@@ -23,27 +23,64 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 **/
 
 
 #include "DxeCorePerformanceLibInternal.h"
 
-
 //
-// The data structure to hold global performance data.
+// Data for FPDT performance records.
 //
-GAUGE_DATA_HEADER*mGaugeData;
+#define SMM_BOOT_RECORD_COMM_SIZE (OFFSET_OF (EFI_SMM_COMMUNICATE_HEADER, 
Data) + sizeof(SMM_BOOT_RECORD_COMMUNICATE))
+#define STRING_SIZE (FPDT_STRING_EVENT_RECORD_NAME_LENGTH * sizeof 
(CHAR8))
+#define FIRMWARE_RECORD_BUFFER  0x1
+#define CACHE_HANDLE_GUID_COUNT 0x1000
+
+BOOT_PERFORMANCE_TABLE  *mAcpiBootPerformanceTable = NULL;
+BOOT_PERFORMANCE_TABLE  mBootPerformanceTableTemplate = {
+  {
+EFI_ACPI_5_0_FPDT_BOOT_PERFORMANCE_TABLE_SIGNATURE,
+sizeof (BOOT_PERFORMANCE_TABLE)
+  },
+  {
+{
+  EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT,// Type
+  sizeof (EFI_ACPI_5_0_FPDT_FIRMWARE_BASIC_BOOT_RECORD),// Length
+  EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_REVISION_FIRMWARE_BASIC_BOOT // Revision
+},
+0,  // Reserved
+//
+// These values will be updated at runtime.
+//
+0,  // ResetEnd
+0,  // OsLoaderLoadImageStart
+0,  // OsLoaderStartImageStart
+0,  // ExitBootServicesEntry
+0   // ExitBootServicesExit
+  }
+};
 
-//
-// The current maximum number of logging entries. If current number of 
-// entries exceeds this value, it will re-allocate a larger array and
-// migration the old data to the larger array.
-//
-UINT32   mMaxGaugeRecords;
+typedef struct {
+  EFI_HANDLEHandle;
+  CHAR8 NameString[FPDT_STRING_EVENT_RECORD_NAME_LENGTH];
+  EFI_GUID  ModuleGuid;
+} HANDLE_GUID_MAP;
 
-//
-// The handle to install Performance Protocol instance.
-//
-EFI_HANDLE   mHandle = NULL;
+HANDLE_GUID_MAP mCacheHandleGuidTable[CACHE_HANDLE_GUID_COUNT];
+UINTN   mCachePairCount = 0;
+
+UINT32  mLoadImageCount   = 0;
+UINT32  mPerformanceLength= 0;
+UINT32  mMaxPerformanceLength = 0;
+UINT32  mBootRecordSize   = 0;
+UINT32  mBootRecordMaxSize= 0;
+
+BOOLEAN mFpdtBufferIsReported = FALSE;
+BOOLEAN mLackSpaceIsReported  = FALSE;
+CHAR8   *mPlatformLanguage= NULL;
+UINT8   *mPerformancePointer  = NULL;
+UINT8   *mBootRecordBuffer= NULL;
+
+EFI_DEVICE_PATH_TO_TEXT_PROTOCOL  *mDevicePathToText = NULL;
 
 //
 // Interfaces for Performance Protocol.
 //
 PERFORMANCE_PROTOCOL mPerformanceInterface = {
@@ -61,179 +98,1042 @@ PERFORMANCE_EX_PROTOCOL mPerformanceExInterface = {
   GetGaugeEx
   };
 
 PERFORMANCE_PROPERTY  mPerformanceProperty;
 
-//
-//  Gauge record lock to avoid data corruption or even memory overflow
-//
-STATIC EFI_LOCK mPerfRecordLock = EFI_INITIALIZE_LOCK_VARIABLE (TPL_NOTIFY);
+/**
+Check whether the Token is a known one which is uesed by core.
+
+@param  Token  Pointer to a Null-terminated ASCII string
+
+@retval TRUE   Is a known one used by core.
+@retval FALSE  Not a known one.
+
+**/
+BOOLEAN
+IsKnownTokens (
+  IN CONST CHAR8  *Token
+  )
+{
+  if (AsciiStrCmp (Token, 

[edk2] [PATCH v3 8/8] ShellPkg/Dp: Updated to dump perf log based on FPDT table

[Dandan Bi]

Cc: Liming Gao 
Cc: Star Zeng 
Cc: Ruiyu Ni 
Cc: Jaben Carsey 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Dandan Bi 
---
 ShellPkg/DynamicCommand/DpDynamicCommand/Dp.c  | 609 -
 ShellPkg/DynamicCommand/DpDynamicCommand/Dp.h  |   7 +-
 ShellPkg/DynamicCommand/DpDynamicCommand/Dp.uni|  11 +-
 ShellPkg/DynamicCommand/DpDynamicCommand/DpApp.inf |   5 +-
 .../DpDynamicCommand/DpDynamicCommand.inf  |   5 +-
 .../DynamicCommand/DpDynamicCommand/DpInternal.h   |   9 +-
 ShellPkg/DynamicCommand/DpDynamicCommand/DpTrace.c | 108 ++--
 .../DynamicCommand/DpDynamicCommand/DpUtilities.c  |  37 +-
 .../DynamicCommand/DpDynamicCommand/Literals.c |  24 +-
 .../DynamicCommand/DpDynamicCommand/Literals.h |   8 +-
 .../DpDynamicCommand/PerformanceTokens.h   |  28 -
 11 files changed, 724 insertions(+), 127 deletions(-)
 delete mode 100644 ShellPkg/DynamicCommand/DpDynamicCommand/PerformanceTokens.h

diff --git a/ShellPkg/DynamicCommand/DpDynamicCommand/Dp.c 
b/ShellPkg/DynamicCommand/DpDynamicCommand/Dp.c
index 3ecc753..fafc64f 100644
--- a/ShellPkg/DynamicCommand/DpDynamicCommand/Dp.c
+++ b/ShellPkg/DynamicCommand/DpDynamicCommand/Dp.c
@@ -11,40 +11,64 @@
   Measurement records contain identifying information (Handle, Token, Module)
   and start and end time values.
   Dp uses this information to group records in different ways.  It also uses
   timer information to calculate elapsed time for each measurement.
  
-  Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
   (C) Copyright 2015-2016 Hewlett Packard Enterprise Development LP
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
   http://opensource.org/licenses/bsd-license.php
  
   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 **/
 
-#include "PerformanceTokens.h"
 #include "Dp.h"
 #include "Literals.h"
 #include "DpInternal.h"
 
+#pragma pack(1)
+
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER  Header;
+  UINT32   Entry;
+} RSDT_TABLE;
+
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER  Header;
+  UINT64   Entry;
+} XSDT_TABLE;
+
+#pragma pack()
+
 EFI_HANDLE   mDpHiiHandle;
 
+typedef struct {
+  EFI_HANDLEHandle;
+  EFI_GUID  ModuleGuid;
+} HANDLE_GUID_MAP;
+
+HANDLE_GUID_MAP  *mCacheHandleGuidTable;
+UINTNmCachePairCount = 0;
+
 //
 /// Module-Global Variables
 ///@{
 CHAR16   mGaugeString[DP_GAUGE_STRING_LENGTH + 1];
 CHAR16   mUnicodeToken[DXE_PERFORMANCE_STRING_SIZE];
 UINT64   mInterestThreshold;
 BOOLEAN  mShowId = FALSE;
+UINT8*mBootPerformanceTable;
+UINTNmBootPerformanceTableSize;
+BOOLEAN  mPeiPhase = FALSE;
+BOOLEAN  mDxePhase = FALSE;
 
 PERF_SUMMARY_DATA SummaryData = { 0 };///< Create the SummaryData 
structure and init. to ZERO.
-
-/// Timer Specific Information.
-TIMER_INFO TimerInfo;
+MEASUREMENT_RECORD  *mMeasurementList = NULL;
+UINTN   mMeasurementNum= 0;
 
 /// Items for which to gather cumulative statistics.
 PERF_CUM_DATA CumData[] = {
   PERF_INIT_CUM_DATA (LOAD_IMAGE_TOK),
   PERF_INIT_CUM_DATA (START_IMAGE_TOK),
@@ -98,10 +122,540 @@ DumpStatistics( void )
   SHELL_FREE_NON_NULL (StringPtr);
   SHELL_FREE_NON_NULL (StringPtrUnknown);
 }
 
 /**
+  This function scan ACPI table in RSDT.
+
+  @param  RsdtACPI RSDT
+  @param  Signature   ACPI table signature
+
+  @return ACPI table
+**/
+VOID *
+ScanTableInRSDT (
+  IN RSDT_TABLE   *Rsdt,
+  IN UINT32   Signature
+  )
+{
+  UINTN Index;
+  UINT32EntryCount;
+  UINT32*EntryPtr;
+  EFI_ACPI_DESCRIPTION_HEADER   *Table;
+
+  EntryCount = (Rsdt->Header.Length - sizeof (EFI_ACPI_DESCRIPTION_HEADER)) / 
sizeof(UINT32);
+
+  EntryPtr = >Entry;
+  for (Index = 0; Index < EntryCount; Index ++, EntryPtr ++) {
+Table = (EFI_ACPI_DESCRIPTION_HEADER*)((UINTN)(*EntryPtr));
+if (Table->Signature == Signature) {
+  return Table;
+}
+  }
+
+  return NULL;
+}
+
+/**
+  This function scan ACPI table in XSDT.
+
+  @param  Xsdt   ACPI XSDT
+  @param  Signature  ACPI table signature
+
+  @return ACPI table
+**/
+VOID *
+ScanTableInXSDT (
+  IN XSDT_TABLE   *Xsdt,
+  IN UINT32   Signature
+  )
+{
+  UINTNIndex;
+  UINT32   EntryCount;
+  UINT64   EntryPtr;
+  UINTN

[edk2] [PATCH v3 5/8] MdeModulePkg/FirmwarePerformancePei:Add FPDT records for S3 phase

[Dandan Bi]

Add FPDT records into boot performance table for S3 phase

Cc: Liming Gao 
Cc: Star Zeng 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Dandan Bi 
---
 .../FirmwarePerformancePei.c   | 59 +-
 .../FirmwarePerformancePei.inf |  5 +-
 2 files changed, 62 insertions(+), 2 deletions(-)

diff --git 
a/MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerformancePei.c
 
b/MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerformancePei.c
index e4800b7..9639fbc 100644
--- 
a/MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerformancePei.c
+++ 
b/MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerformancePei.c
@@ -3,11 +3,11 @@
   Data Table in S3 resume boot mode.
 
   This module register report status code listener to collect performance data
   for S3 Resume Performance Record on S3 resume boot path.
 
-  Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.
+  Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
   http://opensource.org/licenses/bsd-license.php
 
@@ -17,20 +17,24 @@
 **/
 
 #include 
 
 #include 
+#include 
 
 #include 
+#include 
+#include 
 
 #include 
 #include 
 #include 
 #include 
 #include 
 #include 
 #include 
+#include 
 
 /**
   Report status code listener for PEI. This is used to record the performance
   data for S3 FullResume in FPDT.
 
@@ -68,10 +72,17 @@ FpdtStatusCodeListenerPei (
   S3_PERFORMANCE_TABLE *AcpiS3PerformanceTable;
   EFI_ACPI_5_0_FPDT_S3_RESUME_RECORD   *AcpiS3ResumeRecord;
   UINT64   S3ResumeTotal;
   EFI_ACPI_5_0_FPDT_S3_SUSPEND_RECORD  S3SuspendRecord;
   EFI_ACPI_5_0_FPDT_S3_SUSPEND_RECORD  *AcpiS3SuspendRecord;
+  EFI_PEI_READ_ONLY_VARIABLE2_PPI  *VariableServices;
+  UINT8*BootPerformanceTable;
+  FIRMWARE_PERFORMANCE_VARIABLEPerformanceVariable;
+  EFI_HOB_GUID_TYPE*GuidHob;
+  FPDT_PEI_EXT_PERF_HEADER *PeiPerformanceLogHeader;
+  UINT8*FirmwarePerformanceData;
+  UINT8*FirmwarePerformanceTablePtr;
 
   //
   // Check whether status code is what we are interested in.
   //
   if (((CodeType & EFI_STATUS_CODE_TYPE_MASK) != EFI_PROGRESS_CODE) ||
@@ -128,10 +139,56 @@ FpdtStatusCodeListenerPei (
   AcpiS3SuspendRecord->SuspendEnd   = S3SuspendRecord.SuspendEnd;
 
   DEBUG ((EFI_D_INFO, "FPDT: S3 Suspend Performance - SuspendStart = %ld\n", 
AcpiS3SuspendRecord->SuspendStart));
   DEBUG ((EFI_D_INFO, "FPDT: S3 Suspend Performance - SuspendEnd   = %ld\n", 
AcpiS3SuspendRecord->SuspendEnd));
 
+  Status = PeiServicesLocatePpi (
+ ,
+ 0,
+ NULL,
+ (VOID **) 
+ );
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Update S3 boot records into the basic boot performance table.
+  //
+  VarSize = sizeof (PerformanceVariable);
+  Status = VariableServices->GetVariable (
+   VariableServices,
+   EFI_FIRMWARE_PERFORMANCE_VARIABLE_NAME,
+   ,
+   NULL,
+   ,
+   
+   );
+  if (EFI_ERROR (Status)) {
+return Status;
+  }
+  BootPerformanceTable = (UINT8*) (UINTN) 
PerformanceVariable.BootPerformanceTablePointer;
+
+  //
+  // Dump PEI boot records
+  //
+  FirmwarePerformanceTablePtr = (BootPerformanceTable + sizeof 
(BOOT_PERFORMANCE_TABLE));
+  GuidHob   = GetFirstGuidHob ();
+  while (GuidHob != NULL) {
+FirmwarePerformanceData = GET_GUID_HOB_DATA (GuidHob);
+PeiPerformanceLogHeader = (FPDT_PEI_EXT_PERF_HEADER *) 
FirmwarePerformanceData;
+
+CopyMem (FirmwarePerformanceTablePtr, FirmwarePerformanceData + sizeof 
(FPDT_PEI_EXT_PERF_HEADER), (UINTN)(PeiPerformanceLogHeader->SizeOfAllEntries));
+
+GuidHob = GetNextGuidHob (, 
GET_NEXT_HOB (GuidHob));
+
+FirmwarePerformanceTablePtr += 
(UINTN)(PeiPerformanceLogHeader->SizeOfAllEntries);
+  }
+
+  //
+  // Update Table length.
+  //
+  ((BOOT_PERFORMANCE_TABLE *) BootPerformanceTable)->Header.Length = 
(UINT32)((UINTN)FirmwarePerformanceTablePtr - (UINTN)BootPerformanceTable);
+
   return EFI_SUCCESS;
 }
 
 /**
   Main entry for Firmware Performance Data Table PEIM.
diff --git 
a/MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerformancePei.inf
 
b/MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerformancePei.inf
index 53b45a2..a6ce5e6 100644
--- 

[edk2] [PATCH v3 4/8] MdeModulePkg/SmmCorePerformanceLib:Track FPDT record in SMM phase

[Dandan Bi]

V3:
a. Handle the case when string is empty in String Record.
b. Use gEdkiiFpdtExtendedFirmwarePerformanceGuid to report status
code to distinguish with the one in DxeCorePerformanceLib.
c. Refine the code logic.

V2:
Update SmmCorePerformanceLib to report the buffer address of
boot performance records instead of records contents.

Updated to convert Pref entry to FPDT record in SMM phase and then
export records to FPDT table.

Cc: Liming Gao 
Cc: Star Zeng 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Dandan Bi 
---
 .../SmmCorePerformanceLib/SmmCorePerformanceLib.c  | 1068 
 .../SmmCorePerformanceLib.inf  |   10 +-
 .../SmmCorePerformanceLibInternal.h|   11 +-
 3 files changed, 649 insertions(+), 440 deletions(-)

diff --git a/MdeModulePkg/Library/SmmCorePerformanceLib/SmmCorePerformanceLib.c 
b/MdeModulePkg/Library/SmmCorePerformanceLib/SmmCorePerformanceLib.c
index cd1f1a5..57a6240 100644
--- a/MdeModulePkg/Library/SmmCorePerformanceLib/SmmCorePerformanceLib.c
+++ b/MdeModulePkg/Library/SmmCorePerformanceLib/SmmCorePerformanceLib.c
@@ -14,11 +14,11 @@
  This external input must be validated carefully to avoid security issue like
  buffer overflow, integer overflow.
 
  SmmPerformanceHandlerEx(), SmmPerformanceHandler() will receive untrusted 
input and do basic validation.
 
-Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.
 This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD 
License
 which accompanies this distribution.  The full text of the license may be 
found at
 http://opensource.org/licenses/bsd-license.php
 
@@ -28,30 +28,32 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 **/
 
 
 #include "SmmCorePerformanceLibInternal.h"
 
-//
-// The data structure to hold global performance data.
-//
-GAUGE_DATA_HEADER   *mGaugeData;
+#define STRING_SIZE   
(FPDT_STRING_EVENT_RECORD_NAME_LENGTH * sizeof (CHAR8))
+#define FIRMWARE_RECORD_BUFFER0x1000
+#define CACHE_HANDLE_GUID_COUNT   0x1000
 
-//
-// The current maximum number of logging entries. If current number of 
-// entries exceeds this value, it will re-allocate a larger array and
-// migration the old data to the larger array.
-//
-UINT32  mMaxGaugeRecords;
+SMM_BOOT_PERFORMANCE_TABLE*mSmmBootPerformanceTable = NULL;
 
-//
-// The handle to install Performance Protocol instance.
-//
-EFI_HANDLE  mHandle = NULL;
+typedef struct {
+  EFI_HANDLEHandle;
+  CHAR8 NameString[FPDT_STRING_EVENT_RECORD_NAME_LENGTH];
+  EFI_GUID  ModuleGuid;
+} HANDLE_GUID_MAP;
 
-BOOLEAN mPerformanceMeasurementEnabled;
+HANDLE_GUID_MAP  mCacheHandleGuidTable[CACHE_HANDLE_GUID_COUNT];
+UINTNmCachePairCount = 0;
 
-SPIN_LOCK   mSmmPerfLock;
+UINT32   mPerformanceLength= 0;
+UINT32   mMaxPerformanceLength = 0;
+BOOLEAN  mFpdtDataIsReported   = FALSE;
+BOOLEAN  mLackSpaceIsReport= FALSE;
+CHAR8*mPlatformLanguage= NULL;
+SPIN_LOCKmSmmFpdtLock;
+PERFORMANCE_PROPERTY  mPerformanceProperty;
 
 //
 // Interfaces for SMM Performance Protocol.
 //
 PERFORMANCE_PROTOCOL mPerformanceInterface = {
@@ -67,172 +69,630 @@ PERFORMANCE_EX_PROTOCOL mPerformanceExInterface = {
   StartGaugeEx,
   EndGaugeEx,
   GetGaugeEx
 };
 
-PERFORMANCE_PROPERTY mPerformanceProperty;
+/**
+Check whether the Token is a known one which is uesed by core.
+
+@param  Token  Pointer to a Null-terminated ASCII string
+
+@retval TRUE   Is a known one used by core.
+@retval FALSE  Not a known one.
+
+**/
+BOOLEAN
+IsKnownTokens (
+  IN CONST CHAR8  *Token
+  )
+{
+  if (AsciiStrCmp (Token, SEC_TOK) == 0 ||
+  AsciiStrCmp (Token, PEI_TOK) == 0 ||
+  AsciiStrCmp (Token, DXE_TOK) == 0 ||
+  AsciiStrCmp (Token, BDS_TOK) == 0 ||
+  AsciiStrCmp (Token, DRIVERBINDING_START_TOK) == 0 ||
+  AsciiStrCmp (Token, DRIVERBINDING_SUPPORT_TOK) == 0 ||
+  AsciiStrCmp (Token, DRIVERBINDING_STOP_TOK) == 0 ||
+  AsciiStrCmp (Token, LOAD_IMAGE_TOK) == 0 ||
+  AsciiStrCmp (Token, START_IMAGE_TOK) == 0 ||
+  AsciiStrCmp (Token, PEIM_TOK) == 0) {
+return TRUE;
+  } else {
+return FALSE;
+  }
+}
 
 /**
-  Searches in the gauge array with keyword Handle, Token, Module and Identfier.
+Check whether the ID is a known one which map to the known Token.
 
-  This internal function searches for the gauge entry in the gauge array.
-  If there is an entry that exactly matches the given keywords
-  and its end time stamp is zero, then the index of that gauge entry is 
returned;
-  otherwise, the the number of gauge entries in the array is 

[edk2] [PATCH v3 6/8] MdeModulePkg/FirmwarePerfDxe:Enhance for new pref infrastructure

[Dandan Bi]

V3:Add handling for the case when performance feature is not enabled.

V2:
Update FirmwarePerformanceDxe to receive the address
of performance records instead of records content.

1. Remove the macro EXTENSION_RECORD_SIZE, since the extension
size can be got through PcdExtFpdtBootRecordPadSize.

2. Hook EFI_SW_DXE_BS_PC_READY_TO_BOOT_EVENT to install ACPI table

3. Copy SMM record accord to the allocated size

4. Receive Boot performance table address instead of
 contents which are reported DxeCorePerformanceLib.

Cc: Liming Gao 
Cc: Star Zeng 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Dandan Bi 
---
 .../FirmwarePerformanceDxe.c   | 294 -
 .../FirmwarePerformanceDxe.inf |   4 +-
 2 files changed, 51 insertions(+), 247 deletions(-)

diff --git 
a/MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/FirmwarePerformanceDxe.c
 
b/MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/FirmwarePerformanceDxe.c
index b004cac..51a72f0 100644
--- 
a/MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/FirmwarePerformanceDxe.c
+++ 
b/MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/FirmwarePerformanceDxe.c
@@ -3,11 +3,11 @@
 
   This module register report status code listener to collect performance data
   for Firmware Basic Boot Performance Record and other boot performance 
records, 
   and install FPDT to ACPI table.
 
-  Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.
+  Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
   http://opensource.org/licenses/bsd-license.php
 
@@ -18,19 +18,17 @@
 
 #include 
 
 #include 
 #include 
-#include 
 #include 
 #include 
 
 #include 
 #include 
 #include 
 #include 
-#include 
 
 #include 
 #include 
 #include 
 #include 
@@ -40,26 +38,23 @@
 #include 
 #include 
 #include 
 #include 
 
-#define EXTENSION_RECORD_SIZE 0x1
-#define SMM_BOOT_RECORD_COMM_SIZE OFFSET_OF (EFI_SMM_COMMUNICATE_HEADER, Data) 
+ sizeof(SMM_BOOT_RECORD_COMMUNICATE)
+#define SMM_BOOT_RECORD_COMM_SIZE (OFFSET_OF (EFI_SMM_COMMUNICATE_HEADER, 
Data) + sizeof(SMM_BOOT_RECORD_COMMUNICATE))
 
 EFI_RSC_HANDLER_PROTOCOL*mRscHandlerProtocol = NULL;
 
 BOOLEAN mLockBoxReady = FALSE;
 EFI_EVENT   mReadyToBootEvent;
 EFI_EVENT   mLegacyBootEvent;
 EFI_EVENT   mExitBootServicesEvent;
 UINTN   mFirmwarePerformanceTableTemplateKey  = 0;
-UINT32  mBootRecordSize = 0;
-UINT32  mBootRecordMaxSize = 0;
-UINT8   *mBootRecordBuffer = NULL;
 BOOLEAN mDxeCoreReportStatusCodeEnable = FALSE;
 
 BOOT_PERFORMANCE_TABLE  *mAcpiBootPerformanceTable = NULL;
+BOOT_PERFORMANCE_TABLE  *mReceivedAcpiBootPerformanceTable 
= NULL;
 S3_PERFORMANCE_TABLE*mAcpiS3PerformanceTable   = NULL;
 
 FIRMWARE_PERFORMANCE_TABLE  mFirmwarePerformanceTableTemplate = {
   {
 EFI_ACPI_5_0_FIRMWARE_PERFORMANCE_DATA_TABLE_SIGNATURE,
@@ -327,186 +322,66 @@ InstallFirmwarePerformanceDataTable (
   VOID
   )
 {
   EFI_STATUSStatus;
   EFI_ACPI_TABLE_PROTOCOL   *AcpiTableProtocol;
-  UINTN Size;
-  UINT8 *SmmBootRecordCommBuffer;
-  EFI_SMM_COMMUNICATE_HEADER*SmmCommBufferHeader;
-  SMM_BOOT_RECORD_COMMUNICATE   *SmmCommData;
-  UINTN CommSize;
   UINTN BootPerformanceDataSize;
-  UINT8 *BootPerformanceData; 
-  EFI_SMM_COMMUNICATION_PROTOCOL  *Communication;
   FIRMWARE_PERFORMANCE_VARIABLE PerformanceVariable;
-  EDKII_PI_SMM_COMMUNICATION_REGION_TABLE *SmmCommRegionTable;
-  EFI_MEMORY_DESCRIPTOR *SmmCommMemRegion;
-  UINTN Index;
-  VOID  *SmmBootRecordData;
-  UINTN SmmBootRecordDataSize;
-  UINTN ReservedMemSize;
+  UINTN Size;
 
   //
   // Get AcpiTable Protocol.
   //
   Status = gBS->LocateProtocol (, NULL, (VOID **) 
);
   if (EFI_ERROR (Status)) {
 return Status;
   }
 
-  //
-  // Collect boot records from SMM drivers.
-  //
-  SmmBootRecordCommBuffer = NULL;
-  SmmCommData = NULL;
-  SmmBootRecordData   = NULL;
-  SmmBootRecordDataSize   = 0;
-  ReservedMemSize = 0;
-  Status = gBS->LocateProtocol (, NULL, (VOID 
**) );
-  if (!EFI_ERROR (Status)) {
-//
-// Initialize communicate buffer 
-// Get the prepared Reserved Memory Range
+  if 

[edk2] [PATCH v3 2/8] MdeModulePkg/PeiPerformance:Updated to track FPDT record in PEI phase

[Dandan Bi]

V3:Handle the case when string is empty in String Record.

Updated to convert Pref entry to FPDT record in PEI phase and then
report the records to DxeCorePerfLib through GUID hob.

Cc: Liming Gao 
Cc: Star Zeng 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Dandan Bi 
---
 .../Library/PeiPerformanceLib/PeiPerformanceLib.c  | 567 ++---
 .../PeiPerformanceLib/PeiPerformanceLib.inf|  14 +-
 2 files changed, 382 insertions(+), 199 deletions(-)

diff --git a/MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.c 
b/MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.c
index 62527b2..79b67e8 100644
--- a/MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.c
+++ b/MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.c
@@ -5,11 +5,11 @@
   performance logging GUIDed HOB on the first performance logging and then 
logs the
   performance data to the GUIDed HOB. Due to the limitation of temporary RAM, 
the maximum
   number of performance logging entry is specified by 
PcdMaxPeiPerformanceLogEntries or 
   PcdMaxPeiPerformanceLogEntries16.
 
-Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
 (C) Copyright 2015-2016 Hewlett Packard Enterprise Development LP
 This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD 
License
 which accompanies this distribution.  The full text of the license may be 
found at
 http://opensource.org/licenses/bsd-license.php
@@ -20,215 +20,448 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 **/
 
 
 #include 
 
-#include 
+#include 
 
 #include 
 #include 
 #include 
 #include 
 #include 
 #include 
 #include 
 
+#define  STRING_SIZE(FPDT_STRING_EVENT_RECORD_NAME_LENGTH * sizeof 
(CHAR8))
+#define  MAX_RECORD_SIZE(sizeof (FPDT_DYNAMIC_STRING_EVENT_RECORD) + 
STRING_SIZE)
 
 /**
-  Gets the GUID HOB for PEI performance.
+Check whether the Token is a known one which is uesed by core.
 
-  This internal function searches for the GUID HOB for PEI performance.
-  If that GUID HOB is not found, it will build a new one.
-  It outputs the data area of that GUID HOB to record performance log.
+@param  Token  Pointer to a Null-terminated ASCII string
 
-  @paramPeiPerformanceLog   Pointer to Pointer to PEI performance 
log header.
-  @paramPeiPerformanceIdArray   Pointer to Pointer to PEI performance 
identifier array.
+@retval TRUE   Is a known one used by core.
+@retval FALSE  Not a known one.
 
 **/
-VOID
-InternalGetPerformanceHobLog (
-  OUT PEI_PERFORMANCE_LOG_HEADER**PeiPerformanceLog,
-  OUT UINT32**PeiPerformanceIdArray
+BOOLEAN
+IsKnownTokens (
+  IN CONST CHAR8  *Token
   )
 {
-  EFI_HOB_GUID_TYPE   *GuidHob;
-  UINTN   PeiPerformanceSize;
-  UINT16  PeiPerformanceLogEntries;
+  if (AsciiStrCmp (Token, SEC_TOK) == 0 ||
+  AsciiStrCmp (Token, PEI_TOK) == 0 ||
+  AsciiStrCmp (Token, DXE_TOK) == 0 ||
+  AsciiStrCmp (Token, BDS_TOK) == 0 ||
+  AsciiStrCmp (Token, DRIVERBINDING_START_TOK) == 0 ||
+  AsciiStrCmp (Token, DRIVERBINDING_SUPPORT_TOK) == 0 ||
+  AsciiStrCmp (Token, DRIVERBINDING_STOP_TOK) == 0 ||
+  AsciiStrCmp (Token, LOAD_IMAGE_TOK) == 0 ||
+  AsciiStrCmp (Token, START_IMAGE_TOK) == 0 ||
+  AsciiStrCmp (Token, PEIM_TOK) == 0) {
+return TRUE;
+  } else {
+return FALSE;
+  }
+}
 
-  ASSERT (PeiPerformanceLog != NULL);
-  ASSERT (PeiPerformanceIdArray != NULL);
+/**
+Check whether the ID is a known one which map to the known Token.
 
-  PeiPerformanceLogEntries = (UINT16) (PcdGet16 
(PcdMaxPeiPerformanceLogEntries16) != 0 ?
-   PcdGet16 
(PcdMaxPeiPerformanceLogEntries16) :
-   PcdGet8 
(PcdMaxPeiPerformanceLogEntries));
-  GuidHob = GetFirstGuidHob ();
+@param  Identifier  32-bit identifier.
 
-  if (GuidHob != NULL) {
-//
-// PEI Performance HOB was found, then return the existing one.
-//
-*PeiPerformanceLog = GET_GUID_HOB_DATA (GuidHob);
+@retval TRUEIs a known one used by core.
+@retval FALSE   Not a known one.
 
-GuidHob = GetFirstGuidHob ();
-ASSERT (GuidHob != NULL);
-*PeiPerformanceIdArray = GET_GUID_HOB_DATA (GuidHob);
+**/
+BOOLEAN
+IsKnownID (
+  IN UINT32   Identifier
+  )
+{
+  if (Identifier == MODULE_START_ID ||
+  Identifier == MODULE_END_ID ||
+  Identifier == MODULE_LOADIMAGE_START_ID ||
+  Identifier == MODULE_LOADIMAGE_END_ID ||
+  Identifier == MODULE_DB_START_ID ||
+  Identifier == MODULE_DB_END_ID ||
+  Identifier == MODULE_DB_SUPPORT_START_ID ||
+  Identifier == MODULE_DB_SUPPORT_END_ID ||
+  Identifier == MODULE_DB_STOP_START_ID ||
+  

[edk2] [PATCH v3 7/8] MdeModulePkg/FirmwarePerfSmm:Enhance for new pref infrastructure

[Dandan Bi]

V3:
a. Remove unused definitions
b. Get records size form the records buffer when getting size action
is triggered.

V2:
Update FirmwarePerformanceSmm to receive the address
of performance records instead of records content.

Receive buffer address of Boot performance records
which are reported by SmmCorePerformanceLib.

Cc: Liming Gao 
Cc: Star Zeng 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Dandan Bi 
---
 .../FirmwarePerformanceSmm.c   | 35 ++
 .../FirmwarePerformanceSmm.inf |  1 +
 2 files changed, 10 insertions(+), 26 deletions(-)

diff --git 
a/MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableSmm/FirmwarePerformanceSmm.c
 
b/MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableSmm/FirmwarePerformanceSmm.c
index c750331..d4ac849 100644
--- 
a/MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableSmm/FirmwarePerformanceSmm.c
+++ 
b/MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableSmm/FirmwarePerformanceSmm.c
@@ -38,17 +38,16 @@
 #include 
 #include 
 #include 
 #include 
 
-#define EXTENSION_RECORD_SIZE 0x1000
+SMM_BOOT_PERFORMANCE_TABLE*mSmmBootPerformanceTable = NULL;
 
 EFI_SMM_RSC_HANDLER_PROTOCOL  *mRscHandlerProtocol= NULL;
 UINT64mSuspendStartTime   = 0;
 BOOLEAN   mS3SuspendLockBoxSaved  = FALSE;
 UINT32mBootRecordSize = 0;
-UINT32mBootRecordMaxSize = 0;
 UINT8 *mBootRecordBuffer = NULL;
 
 SPIN_LOCK mSmmFpdtLock;
 BOOLEAN   mSmramIsOutOfResource = FALSE;
 
@@ -82,11 +81,10 @@ FpdtStatusCodeListenerSmm (
   )
 {
   EFI_STATUS   Status;
   UINT64   CurrentTime;
   EFI_ACPI_5_0_FPDT_S3_SUSPEND_RECORD  S3SuspendRecord;
-  UINT8*NewRecordBuffer;
 
   //
   // Check whether status code is what we are interested in.
   //
   if ((CodeType & EFI_STATUS_CODE_TYPE_MASK) != EFI_PROGRESS_CODE) {
@@ -94,36 +92,18 @@ FpdtStatusCodeListenerSmm (
   }
   
   //
   // Collect one or more Boot records in boot time
   //
-  if (Data != NULL && CompareGuid (>Type, )) 
{
+  if (Data != NULL && CompareGuid (>Type, 
)) {
 AcquireSpinLock ();
-
-if (mBootRecordSize + Data->Size > mBootRecordMaxSize) {
-  //
-  // Try to allocate big SMRAM data to store Boot record. 
-  //
-  if (mSmramIsOutOfResource) {
-ReleaseSpinLock ();
-return EFI_OUT_OF_RESOURCES;
-  }
-  NewRecordBuffer = ReallocatePool (mBootRecordSize, mBootRecordSize + 
Data->Size + EXTENSION_RECORD_SIZE, mBootRecordBuffer); 
-  if (NewRecordBuffer == NULL) {
-ReleaseSpinLock ();
-mSmramIsOutOfResource = TRUE;
-return EFI_OUT_OF_RESOURCES;
-  }
-  mBootRecordBuffer  = NewRecordBuffer;
-  mBootRecordMaxSize = mBootRecordSize + Data->Size + 
EXTENSION_RECORD_SIZE;
-}
 //
-// Save boot record into the temp memory space.
+// Get the boot performance data.
 //
-CopyMem (mBootRecordBuffer + mBootRecordSize, Data + 1, Data->Size);
-mBootRecordSize += Data->Size;
-
+CopyMem (, Data + 1, Data->Size);
+mBootRecordBuffer = ((UINT8 *) (mSmmBootPerformanceTable)) + sizeof 
(SMM_BOOT_PERFORMANCE_TABLE);
+
 ReleaseSpinLock ();
 return EFI_SUCCESS;
   }
 
   if ((Value != PcdGet32 (PcdProgressCodeS3SuspendStart)) &&
@@ -237,10 +217,13 @@ FpdtSmiHandler (
 
   Status = EFI_SUCCESS;
 
   switch (SmmCommData->Function) {
 case SMM_FPDT_FUNCTION_GET_BOOT_RECORD_SIZE :
+  if (mSmmBootPerformanceTable != NULL) {
+mBootRecordSize = mSmmBootPerformanceTable->Header.Length - sizeof 
(SMM_BOOT_PERFORMANCE_TABLE);
+  }
   SmmCommData->BootRecordSize = mBootRecordSize;
   break;
 
 case SMM_FPDT_FUNCTION_GET_BOOT_RECORD_DATA :
   Status = EFI_UNSUPPORTED;
diff --git 
a/MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableSmm/FirmwarePerformanceSmm.inf
 
b/MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableSmm/FirmwarePerformanceSmm.inf
index 724e7bc..cae0111 100644
--- 
a/MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableSmm/FirmwarePerformanceSmm.inf
+++ 
b/MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableSmm/FirmwarePerformanceSmm.inf
@@ -58,10 +58,11 @@
 [Guids]
   ## SOMETIMES_PRODUCES   ## UNDEFINED # SaveLockBox
   ## PRODUCES ## UNDEFINED # SmiHandlerRegister
   ## SOMETIMES_CONSUMES   ## UNDEFINED # StatusCode Data
   gEfiFirmwarePerformanceGuid
+  gEdkiiFpdtExtendedFirmwarePerformanceGuid  ## SOMETIMES_PRODUCES ## 
UNDEFINED # StatusCode Data
 
 [Pcd]
   gEfiMdeModulePkgTokenSpaceGuid.PcdProgressCodeS3SuspendStart  ## CONSUMES
   gEfiMdeModulePkgTokenSpaceGuid.PcdProgressCodeS3SuspendEnd## CONSUMES
 
-- 
1.9.5.msysgit.1

Re: [edk2] [PATCH] MdeModulePkg/SmmCore: Fix hang due to already-freed memory deference

[Zeng, Star]

Reviewed-by: Star Zeng 

BTW, do you want to say " the second call may hang " instead of " the second 
hang may hang " in the commit log?


Thanks,
Star
-Original Message-
From: Ni, Ruiyu 
Sent: Thursday, February 1, 2018 6:16 PM
To: edk2-devel@lists.01.org
Cc: Yao, Jiewen ; Zeng, Star 
Subject: [PATCH] MdeModulePkg/SmmCore: Fix hang due to already-freed memory 
deference

SmiHandlerUnRegister() validates the DispatchHandle by checking whether the 
first 32bit matches to a certain signature (SMI_HANDLER_SIGNATURE).
But if a caller calls *UnRegister() twice and the memory freed by first call 
still contains the signature, the second hang may hang.

The patch fixes this issue by locating the DispatchHandle in all SMI handlers, 
instead of checking the signature.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni 
Cc: Jiewen Yao 
Cc: Star Zeng 
---
 MdeModulePkg/Core/PiSmmCore/Smi.c | 37 -
 1 file changed, 32 insertions(+), 5 deletions(-)

diff --git a/MdeModulePkg/Core/PiSmmCore/Smi.c 
b/MdeModulePkg/Core/PiSmmCore/Smi.c
index ad483a1877..0c09e7fa10 100644
--- a/MdeModulePkg/Core/PiSmmCore/Smi.c
+++ b/MdeModulePkg/Core/PiSmmCore/Smi.c
@@ -1,7 +1,7 @@
 /** @file
   SMI management.
 
-  Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights 
+ reserved.
   This program and the accompanying materials are licensed and made available 
   under the terms and conditions of the BSD License which accompanies this 
   distribution.  The full text of the license may be found at
@@ -276,14 +276,41 @@ SmiHandlerUnRegister (  {
   SMI_HANDLER  *SmiHandler;
   SMI_ENTRY*SmiEntry;
+  LIST_ENTRY   *EntryLink;
+  LIST_ENTRY   *HandlerLink;
 
-  SmiHandler = (SMI_HANDLER *) DispatchHandle;
-
-  if (SmiHandler == NULL) {
+  if (DispatchHandle == NULL) {
 return EFI_INVALID_PARAMETER;
   }
 
-  if (SmiHandler->Signature != SMI_HANDLER_SIGNATURE) {
+  //
+  // Look for it in root SMI handlers
+  //
+  SmiHandler = NULL;
+  for ( HandlerLink = GetFirstNode ()
+  ; !IsNull (, HandlerLink) && (SmiHandler != 
DispatchHandle)
+  ; HandlerLink = GetNextNode (, HandlerLink)
+  ) {
+SmiHandler = CR (HandlerLink, SMI_HANDLER, Link, 
+ SMI_HANDLER_SIGNATURE);  }
+
+  //
+  // Look for it in non-root SMI handlers  //  for ( EntryLink = 
+ GetFirstNode ()
+  ; !IsNull (, EntryLink) && (SmiHandler != DispatchHandle)
+  ; EntryLink = GetNextNode (, EntryLink)
+  ) {
+SmiEntry = CR (EntryLink, SMI_ENTRY, AllEntries, SMI_ENTRY_SIGNATURE);
+for ( HandlerLink = GetFirstNode (>SmiHandlers)
+; !IsNull (>SmiHandlers, HandlerLink) && (SmiHandler != 
DispatchHandle)
+; HandlerLink = GetNextNode (>SmiHandlers, HandlerLink)
+) {
+  SmiHandler = CR (HandlerLink, SMI_HANDLER, Link, SMI_HANDLER_SIGNATURE);
+}
+  }
+
+  if (SmiHandler != DispatchHandle) {
 return EFI_INVALID_PARAMETER;
   }
 
--
2.15.1.windows.2

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[edk2] [PATCH] MdePkg/SafeString: Directly return when length of source string is 0

[Ruiyu Ni]

Today's implementation of [Ascii]StrnCpyS/[Ascii]StrnCatS doesn't
directly return the the length of source string is 0.

When length of source string is 0, it means the Source points to
a memory that shouldn't be deferenced at all.
So it's not proper to call StrnLenS() in such situation.
In a pool guard enabled environment, when using shell to edit an
existing file which contains empty line, the page fault is met.

The patch fixes the four library functions to align to the behavior
of non-safe version: directly return when length of source string
is 0.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni 
Cc: Jiewen Yao 
Cc: Liming Gao 
Cc: Jian J Wang 
---
 MdePkg/Library/BaseLib/SafeString.c | 18 +-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/MdePkg/Library/BaseLib/SafeString.c 
b/MdePkg/Library/BaseLib/SafeString.c
index 68c33e9b7b..fed818ef33 100644
--- a/MdePkg/Library/BaseLib/SafeString.c
+++ b/MdePkg/Library/BaseLib/SafeString.c
@@ -1,7 +1,7 @@
 /** @file
   Safe String functions.
 
-  Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
+  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -317,6 +317,10 @@ StrnCpyS (
 {
   UINTNSourceLen;
 
+  if (Length == 0) {
+return RETURN_SUCCESS;
+  }
+
   ASSERT (((UINTN) Destination & BIT0) == 0);
   ASSERT (((UINTN) Source & BIT0) == 0);
 
@@ -515,6 +519,10 @@ StrnCatS (
   UINTN   CopyLen;
   UINTN   SourceLen;
 
+  if (Length == 0) {
+return RETURN_SUCCESS;
+  }
+
   ASSERT (((UINTN) Destination & BIT0) == 0);
   ASSERT (((UINTN) Source & BIT0) == 0);
 
@@ -1894,6 +1902,10 @@ AsciiStrnCpyS (
 {
   UINTNSourceLen;
 
+  if (Length == 0) {
+return RETURN_SUCCESS;
+  }
+
   //
   // 1. Neither Destination nor Source shall be a null pointer.
   //
@@ -2082,6 +2094,10 @@ AsciiStrnCatS (
   UINTN   CopyLen;
   UINTN   SourceLen;
 
+  if (Length == 0) {
+return RETURN_SUCCESS;
+  }
+
   //
   // Let CopyLen denote the value DestMax - AsciiStrnLenS(Destination, 
DestMax) upon entry to AsciiStrnCatS.
   //
-- 
2.16.1.windows.1

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Re: [edk2] difference between asm16 and asm files

[Tiger Liu(BJ-RD)]

Hi, Liming:
Got it!

Thanks

Best wishes,

-邮件原件-
发件人: Gao, Liming [mailto:liming@intel.com]
发送时间: 2018年1月31日 17:44
收件人: Tiger Liu(BJ-RD) ; edk2-devel@lists.01.org
主题: RE: [edk2] difference between asm16 and asm files

Tiger:
  Nasm compiler supports to generate 16bit raw code. User doesn't need to 
install the additional tool. And, the raw code is 16bit code. You need 16bit 
assembler. It is also nasm compiler. So, it is obvious to use nasm to directly 
do it.

Thanks
Liming
>-Original Message-
>From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
>Tiger Liu(BJ-RD)
>Sent: Wednesday, January 31, 2018 1:18 PM
>To: Gao, Liming ; edk2-devel@lists.01.org
>Subject: Re: [edk2] difference between asm16 and asm files
>
>Hi, Liming:
>YES, its code need to be the raw execution code.
>I mean:
>1. We could use traditional asm code , compiled it, and use tools to
>translate them to the raw execution code.
>Is there any difficulty to do this?
>
>So, it would depreciate the asm16 or nasmb concept.
>
>Thanks
>-邮件原件-
>发件人: Tiger Liu(BJ-RD)
>发送时间: 2018年1月30日 9:45
>收件人: 'Gao, Liming' ; edk2-devel@lists.01.org
>主题: Re: [edk2] difference between asm16 and asm files
>
>Hi, Liming:
>Thanks for your reply!
>
>I have another question:
>Why not let sec code complied to obj file and linked to lib and EFI image?
>
>I met a problem:
>I tried to use IFDEF marco in an assembly inc file,  and this inc file
>would be included by ResetVec.asm16 But failed, it seemed asm 16
>complier not recognize this marco exist.
>If I changed ResetVec.asm16 to ResetVec.asm, and compiled again, the
>complier will recognize this marco exist.
>But the last step failed, GenFds.exe seems search a binary file, and not found.
>
>Thanks
>-邮件原件-
>发件人: Gao, Liming [mailto:liming@intel.com]
>发送时间: 2018年1月29日 22:30
>收件人: Tiger Liu(BJ-RD) ; edk2-devel@lists.01.org
>主题: RE: [edk2] difference between asm16 and asm files
>
>Asm16 is compiled to the binary file. Asm is compiled to the obj file,
>and linked into lib and EFI image.
>
>Now, asm16 is replaced by nasmb. Asm is replaced by nasm. If you check
>SecCore.inf, you will find ResetVec.asm16 is not used, and
>ResetVec.nasmb is used. I will send the patch to remove the unused
>ResetVec.asm16 to avoid the confuse.
>
>> -Original Message-
>> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf
>> Of Tiger Liu(BJ-RD)
>> Sent: Monday, January 29, 2018 6:49 PM
>> To: edk2-devel@lists.01.org
>> Subject: [edk2] difference between asm16 and asm files
>>
>> Hi, experts:
>> I have a question about asm16 postfix and asm postfix.
>>
>> Such as:
>> UefiCpuPkg\SecCore\Ia32\ResetVec.asm16
>>
>> Why not use asm as postfix?
>>
>> Thanks
>>
>> Best wishes,
>>
>>
>> ?
>> ?
>> CONFIDENTIAL NOTE:
>> This email contains confidential or legally privileged information
>> and is for the sole use of its intended recipient. Any unauthorized
>> review, use,
>copying or forwarding of this email or the content of this email is
>strictly prohibited.
>> ___
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>> edk2-devel@lists.01.org
>> https://lists.01.org/mailman/listinfo/edk2-devel
>
>
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Re: [edk2] [PATCH 1/3] UefiCpuPkg/PiSmmCpuDxeSmm: update comments in IA32 SmmStartup()

[Ard Biesheuvel]

On 31 January 2018 at 10:40, Laszlo Ersek  wrote:
> On 01/30/18 23:25, Kinney, Michael D wrote:
>> Laszlo,
>>
>> I agree that the function is better than a macro.
>>
>> I thought of the alignment issues as well.  CopyMem()
>> is a good solution.  We could also consider
>> WriteUnalignedxx() functions in BaseLib.
>
> IMO, the WriteUnalignedxx functions are a bit pointless in the exact
> form they are declared (this was discussed earlier esp. with regard to
> aarch64). The functions take pointers to objects that already have the
> target type, such as
>
> UINT32
> EFIAPI
> WriteUnaligned32 (
>   OUT UINT32*Buffer,
>   IN  UINT32Value
>   )
>
> Here the type of Buffer should be (VOID *), not (UINT32 *). Otherwise,
> the undefined behavior (due to mis-alignment) surfaces as soon as the
> function is called with an unaligned pointer (i.e. before the target
> area is actually written).
>
>> I was originally thinking this functionality would go
>> into BaseLib.  But with the use of CopyMem(), we can't
>> do that.
>
> Can we put it in BaseMemoryLib instead (which is where CopyMem() is
> from)? That library class is still low-level enough. And, while I count
> 9 library instances, PatchAssembly() is not a large function, we could
> tolerate adding it to all 9 instances, identically.
>
> Let me also ask the opposite question: should we perhaps make the
> PatchAssembly() API *less* abstract? (Also suggested by your naming of
> the macro, PATCH_X86_ASM.) If the instruction encoding on e.g. AARCH64
> doesn't lend itself to such patching (= expressed through the address
> right after the instruction), then even BaseMemoryLib may be too generic
> for the API.
>
>> Maybe we should use WriteUnalignedxx() and
>> add some ASSERT() checks.
>>
>> VOID
>> PatchAssembly (
>>   VOID*BufferEnd,
>>   UINT64  PatchValue,
>>   UINTN   ValueSize
>>   )
>> {
>>   ASSERT ((UINTN)BufferEnd > ValueSize);
>>   switch (ValueSize) {
>>   case 1:
>> ASSERT (PatchValue <= MAX_UINT8);
>> *((UINT8 *)BufferEnd - 1) = (UINT8)PatchValue;
>>   case 2:
>> ASSERT (PatchValue <= MAX_UINT16);
>> WriteUnaligned16 ((UINT16 *)(BufferEnd) - 1, (UINT16)PatchValue));
>> break;
>>   case 4:
>> ASSERT (PatchValue <= MAX_UINT32);
>> WriteUnaligned32 ((UINT32 *)(BufferEnd) - 1, (UINT32)PatchValue));
>> break;
>>   case 8:
>> WriteUnaligned64 ((UINT64 *)(BufferEnd) - 1, PatchValue));
>> break;
>>   default:
>> ASSERT (FALSE);
>>   }
>> }
>
> In my opinion:
>
> - If Ard and Leif say that PatchAssembly() API makes sense for AARCH64,
>   then I think we can go with the above generic implementation (for
>   BaseLib).
>

Code patching on ARM/AARCH64 has some hoops to jump through, i.e.,
clean the D-cache to the point of unification, invalidate the I-cache,
probably some barriers in case the patching function happened to end
up in the same cache line as the patchee (which may not be a concern
for this specific use case, but it does need to be taken into account
if this is turned into a patch-any-assembly-anywhere function)

So if the PatchAssembly() prototype does end up in a generic library
class, we'd have to provide ARM and AARCH64 specific implementations
anyway, and given that I don't see any use for this on ARM/AARCH64 in
the first place, I think this should belong in an IA32/X64 specific
package.

> - If Ard and Leif say the API is only useful on x86, then I suggest that
>   we implement the API separately for all arches (still in BaseLib):
>
>   - On x86, we should simply open-code the unaligned accesses (like you
> originall suggested). The pointer arithmetic will look a bit wild,
> but it's safely hidden behind a BaseLib API, so client code will
> look nice.
>
>   - On all other arches, we should implement the function with
> ASSERT(FALSE).
>
> Thanks!
> Laszlo
>
>>
>> Mike
>>
>>> -Original Message-
>>> From: Laszlo Ersek [mailto:ler...@redhat.com]
>>> Sent: Tuesday, January 30, 2018 1:45 PM
>>> To: Kinney, Michael D ; edk2-
>>> devel-01 
>>> Cc: Ni, Ruiyu ; Paolo Bonzini
>>> ; Yao, Jiewen
>>> ; Dong, Eric 
>>> Subject: Re: [edk2] [PATCH 1/3]
>>> UefiCpuPkg/PiSmmCpuDxeSmm: update comments in IA32
>>> SmmStartup()
>>>
>>> On 01/30/18 21:31, Kinney, Michael D wrote:
 Laszlo,

 We have already used this technique in other NASM files
 to remove DBs.
>>>
>>> OK.
>>>
 Let us know if you have suggestions on how to make the
 C code that performs the patches easier to read and
 maintain.
>>>
>>> How about this:
>>>
>>>   VOID
>>>   PatchAssembly (
>>> VOID   *BufferEnd,
>>> UINT64 PatchValue,
>>> UINTN  ValueSize
>>> )
>>>   {
>>> CopyMem (
>>>   (VOID *)((UINTN)BufferEnd - ValueSize),
>>>   ,
>>>   ValueSize
>>>   );
>>>   }
>>>
>>>   extern