> And, in my recent KVM / QEMU usage instructions for Jiewen:
>
> https://www.mail-archive.com/edk2-devel@lists.01.org/msg19446.html
>
> I provided the following settings:
>
> > # Settings for Ia32 only:
> > [...]
> > QEMU_COMMAND="qemu-system-i386 -cpu coreduo,-nx"
> >
> > # Settings for
On 11/10/16 15:48, Yao, Jiewen wrote:
> Laszlo, your analysis will save me one day to install the Linux QEMU. J
Perfect; I can't wait till you guys adopt QEMU/KVM as a test platform! :)
Cheers
Laszlo
___
edk2-devel mailing list
On 11/10/16 15:53, Paolo Bonzini wrote:
>
>
> On 10/11/2016 15:48, Yao, Jiewen wrote:
>> I cannot reproduce it before, because all my real hardware supports XD.
>> My Windows QEMU also supports XD (to my surprise.)
>
> QEMU can be configured to support XD or not. Possibly Laszlo was using
>
On 10/11/2016 15:48, Yao, Jiewen wrote:
> I cannot reproduce it before, because all my real hardware supports XD.
> My Windows QEMU also supports XD (to my surprise.)
QEMU can be configured to support XD or not. Possibly Laszlo was using
some different default, or testing both cases.
Paolo
t;michael.d.kin...@intel.com>; Paolo Bonzini <pbonz...@redhat.com>; Fan, Jeff
<jeff@intel.com>; Zeng, Star <star.z...@intel.com>
Subject: Re: [edk2] [PATCH V2 0/6] Enable SMM page level protection.
On 11/10/16 11:41, Yao, Jiewen wrote:
> Thanks to report case 3 issue
k2-de...@ml01.01.org; Kinney, Michael
> D <michael.d.kin...@intel.com>; Paolo Bonzini <pbonz...@redhat.com>; Fan,
> Jeff <jeff@intel.com>; Zeng, Star <star.z...@intel.com>
> Subject: Re: [edk2] [PATCH V2 0/6] Enable SMM page level protection.
>
> On 11/09/16 07:25
f ! [ -e "$VARS" ]; then
> cp -- "$TEMPLATE" "$VARS"
> fi
>
> $QEMU_COMMAND \
> -machine q35,smm=on,accel=kvm \
> -m 4096 \
> -smp sockets=1,cores=2,threads=2 \
> -global driver=cfi.pflash01,property=secure,value=on \
> -drive if=pflas
Cc: Tian, Feng <feng.t...@intel.com>; edk2-de...@ml01.01.org; Kinney, Michael D
<michael.d.kin...@intel.com>; Paolo Bonzini <pbonz...@redhat.com>; Fan, Jeff
<jeff@intel.com>; Zeng, Star <star.z...@intel.com>
Subject: Re: [edk2] [PATCH V2 0/6] Enable SMM page level prot
ney, Michael D; Tian, Feng; edk2-de...@ml01.01.org; Zeng, Star; Fan, Jeff
Subject: RE: [edk2] [PATCH V2 0/6] Enable SMM page level protection.
So, I don't understand how the CR3s that are used by the APs when they
serve MP services PPI requests, throughout the PEI phase (*), have
anything to
t;star.z...@intel.com>; Fan, Jeff <jeff....@intel.com>
Subject: RE: [edk2] [PATCH V2 0/6] Enable SMM page level protection.
> Anyway, I think if the BSP and the APs are properly synchronized around
> the SMI injections in S3ResumeExecuteBootScript(), then this bug is
> fixed. In t
lt;michael.d.kin...@intel.com>; Tian, Feng <feng.t...@intel.com>;
edk2-de...@ml01.01.org; Zeng, Star <star.z...@intel.com>; Fan, Jeff
<jeff....@intel.com>
Subject: Re: [edk2] [PATCH V2 0/6] Enable SMM page level protection.
> Another question I have -- and I feel I
On 11/09/16 23:59, Paolo Bonzini wrote:
>
>> Another question I have -- and I feel I should really know it, but I
>> don't... -- is *why* the APs are executing code from the page at
>> 0x9f000.
>
> This I can answer. :)
>
> The APs have done their INIT-SIPI-SIPI, and then went into the
> Another question I have -- and I feel I should really know it, but I
> don't... -- is *why* the APs are executing code from the page at
> 0x9f000.
This I can answer. :)
The APs have done their INIT-SIPI-SIPI, and then went into the CLI;HLT;JMP
loop. When the AP exits SMM, it is in the JMP
On 11/09/16 16:54, Paolo Bonzini wrote:
>
>
> On 09/11/2016 16:01, Yao, Jiewen wrote:
>> 1) CpuS3.c – EarlyInitializeCpu()
>> 2) CpuS3.c – SmmRelocateBases()
>> 3) CpuS3.c – InitializeCpu()
>> 4) S3Resume.c – SendSmiIpiAllExcludingSelf()
>>
>> I believe we can guarantee 1/2/3
Thanks
Laszlo
>
> Thank you
> Yao Jiewen
>
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Laszlo
> Ersek
> Sent: Tuesday, November 8, 2016 9:22 AM
> To: Yao, Jiewen <jiewen@intel.com>
> Cc: Tian, Feng <feng.t...@intel.com>; edk
On 09/11/2016 16:54, Paolo Bonzini wrote:
>> > and 2) AP is in protected mode with paging disabled.
> It is not clear to me what the (4) SIPI done is there for, and why it is
> triggered in S3Resume.c rather than CpuS3.c. And why does it take so
> much for APs to complete it?
SMI of course,
On 09/11/2016 16:01, Yao, Jiewen wrote:
> 1) CpuS3.c – EarlyInitializeCpu()
> 2) CpuS3.c – SmmRelocateBases()
> 3) CpuS3.c – InitializeCpu()
> 4) S3Resume.c – SendSmiIpiAllExcludingSelf()
>
> I believe we can guarantee 1/2/3 is good, because I found we check BSP
> check
ler...@redhat.com>
Cc: Yao, Jiewen <jiewen@intel.com>; edk2-de...@ml01.01.org; Kinney, Michael
D <michael.d.kin...@intel.com>; Tian, Feng <feng.t...@intel.com>; Fan, Jeff
<jeff@intel.com>; Zeng, Star <star.z...@intel.com>
Subject: Re: [edk2] [PATCH V2 0
Kinney, Michael D
<michael.d.kin...@intel.com>; Fan, Jeff <jeff@intel.com>; Zeng, Star
<star.z...@intel.com>
Subject: Re: [edk2] [PATCH V2 0/6] Enable SMM page level protection.
On 09/11/2016 07:25, Yao, Jiewen wrote:
> Current BSP just uses its own context to initialize AP. So th
On 09/11/2016 07:25, Yao, Jiewen wrote:
> Current BSP just uses its own context to initialize AP. So that AP
> takes BSP CR3, which is SMM CR3, unfortunately. After BSP initialized
> APs, the AP is put to HALT-LOOP in X64 mode. It is the last straw,
> because X64 mode halt still need paging.
>
> * Second, the instruction that causes things to blow up is <0f aa>,
> i.e., RSM. I have absolutely no clue why RSM is executed:
It's probably not RSM. RSM is probably the last instruction executed
before, and it's still in the buffer because, as you said, there's no
way that you can
ng, Star <star.z...@intel.com>
Subject: Re: [edk2] [PATCH V2 0/6] Enable SMM page level protection.
On 11/04/16 10:30, Jiewen Yao wrote:
> below is V2 description
> 1) PiSmmCpu: resolve OVMF multiple processors boot hang issue.
> 2) PiSmmCpu: Add debug info on StartupAp()
.t...@intel.com>; edk2-de...@ml01.01.org; Kinney, Michael D
<michael.d.kin...@intel.com>; Paolo Bonzini <pbonz...@redhat.com>; Fan, Jeff
<jeff@intel.com>; Zeng, Star <star.z...@intel.com>
Subject: Re: [edk2] [PATCH V2 0/6] Enable SMM page level protection.
6 9:22 AM
> *To:* Yao, Jiewen <jiewen@intel.com>
> *Cc:* Tian, Feng <feng.t...@intel.com>; edk2-de...@ml01.01.org; Kinney,
> Michael D <michael.d.kin...@intel.com>; Paolo Bonzini
> <pbonz...@redhat.com>; Fan, Jeff <jeff@intel.com>; Zeng, Star
> <s
ewen@intel.com>
Cc: Tian, Feng <feng.t...@intel.com>; edk2-de...@ml01.01.org; Kinney, Michael D
<michael.d.kin...@intel.com>; Paolo Bonzini <pbonz...@redhat.com>; Fan, Jeff
<jeff....@intel.com>; Zeng, Star <star.z...@intel.com>
Subject: Re: [edk2] [PATCH V2
On 11/04/16 10:30, Jiewen Yao wrote:
> below is V2 description
> 1) PiSmmCpu: resolve OVMF multiple processors boot hang issue.
> 2) PiSmmCpu: Add debug info on StartupAp() fails.
> 3) PiSmmCpu: Add ASSERT for AllocatePages().
> 4) PiSmmCpu: Add protection detail in commit message.
> 5)
.@intel.com>; Zeng, Star
> <star.z...@intel.com>
> Subject: Re: [edk2] [PATCH V2 0/6] Enable SMM page level protection.
>
> On 11/04/16 10:30, Jiewen Yao wrote:
>> below is V2 description
>> 1) PiSmmCpu: resolve OVMF multiple processors boot hang issue.
&g
org
Cc: Kinney, Michael D <michael.d.kin...@intel.com>; Tian, Feng
<feng.t...@intel.com>; Fan, Jeff <jeff@intel.com>; Zeng, Star
<star.z...@intel.com>
Subject: Re: [edk2] [PATCH V2 0/6] Enable SMM page level protection.
On 11/04/16 10:30, Jiewen Yao wrote:
>
below is V2 description
1) PiSmmCpu: resolve OVMF multiple processors boot hang issue.
2) PiSmmCpu: Add debug info on StartupAp() fails.
3) PiSmmCpu: Add ASSERT for AllocatePages().
4) PiSmmCpu: Add protection detail in commit message.
5) UefiCpuPkg.dsc: Add page table footprint info in
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