subject:"\[edk2\] \[PATCH v4 1\/6\] MdeModulePkg\: Add PCD PcdPteMemoryEncryptionAddressOrMask"

Re: [edk2] [PATCH v4 1/6] MdeModulePkg: Add PCD PcdPteMemoryEncryptionAddressOrMask

2017-02-27 Thread Zeng, Star

01.01.org Cc: Singh, Brijesh <brijesh.si...@amd.com>; Tian, Feng <feng.t...@intel.com>; Laszlo Ersek <ler...@redhat.com> Subject: Re: [edk2] [PATCH v4 1/6] MdeModulePkg: Add PCD PcdPteMemoryEncryptionAddressOrMask Please see below. > -Original Message- > From: Ze

Re: [edk2] [PATCH v4 1/6] MdeModulePkg: Add PCD PcdPteMemoryEncryptionAddressOrMask

2017-02-27 Thread Duran, Leo

Please see below. > -Original Message- > From: Zeng, Star [mailto:star.z...@intel.com] > Sent: Sunday, February 26, 2017 8:20 PM > To: Duran, Leo ; edk2-de...@ml01.01.org > Cc: Tian, Feng ; Laszlo Ersek ; > Singh, Brijesh

Re: [edk2] [PATCH v4 1/6] MdeModulePkg: Add PCD PcdPteMemoryEncryptionAddressOrMask

2017-02-26 Thread Zeng, Star

We saw you defined 4K/2M/1G in previous patch series, #define PAGING_4K_ADDRESS_MASK_64 0x000FF000ull #define PAGING_2M_ADDRESS_MASK_64 0x000FFFE0ull #define PAGING_1G_ADDRESS_MASK_64 0x000FC000ull But only 1G mask is defined and used in this patch series, is that on

[edk2] [PATCH v4 1/6] MdeModulePkg: Add PCD PcdPteMemoryEncryptionAddressOrMask

2017-02-26 Thread Leo Duran

This PCD holds the address mask for page table entries when memory encryption is enabled on AMD processors supporting the Secure Encrypted Virtualization (SEV) feature. Cc: Feng Tian Cc: Star Zeng Cc: Laszlo Ersek Contributed-under: