wt., 15 sty 2019 o 11:04 Leif Lindholm napisał(a):
>
> On Tue, Jan 15, 2019 at 07:19:04AM +0100, Marcin Wojtas wrote:
> > > > + if (MmioRead32 (BaseAddress + MV_GPIO_OUT_EN_REG) & (1 << GpioPin)) {
> > > > +*Mode = GPIO_MODE_INPUT;
> > > > + } else {
> > > > +if (MmioRead32 (BaseAddress
On Tue, Jan 15, 2019 at 07:19:04AM +0100, Marcin Wojtas wrote:
> > > + if (MmioRead32 (BaseAddress + MV_GPIO_OUT_EN_REG) & (1 << GpioPin)) {
> > > +*Mode = GPIO_MODE_INPUT;
> > > + } else {
> > > +if (MmioRead32 (BaseAddress + MV_GPIO_DATA_IN_REG) & (1 << GpioPin))
> > > {
> > > + *
Hi Leif,
wt., 15 sty 2019 o 00:32 Leif Lindholm napisał(a):
>
> On Thu, Jan 10, 2019 at 02:44:35AM +0100, Marcin Wojtas wrote:
> > Marvell Armada 7k/8k SoCs comprise integrated GPIO controllers,
> > one in AP806 and two in each south bridge hardware blocks.
> >
> > This patch introduces support
On Thu, Jan 10, 2019 at 02:44:35AM +0100, Marcin Wojtas wrote:
> Marvell Armada 7k/8k SoCs comprise integrated GPIO controllers,
> one in AP806 and two in each south bridge hardware blocks.
>
> This patch introduces support for them. The new driver implements
> a generic EMBEDDED_GPIO protocol.
>
Marvell Armada 7k/8k SoCs comprise integrated GPIO controllers,
one in AP806 and two in each south bridge hardware blocks.
This patch introduces support for them. The new driver implements
a generic EMBEDDED_GPIO protocol.
In order to ease description of used GPIO pins and controllers
of the Arma
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