On 10 November 2017 at 09:29, Laszlo Ersek wrote:
> On 11/09/17 22:11, Ard Biesheuvel wrote:
>> On 7 November 2017 at 18:13, Ard Biesheuvel
>> wrote:
>>> On 7 November 2017 at 18:09, Laszlo Ersek wrote:
On 11/05/17 17:29,
On 11/09/17 22:11, Ard Biesheuvel wrote:
> On 7 November 2017 at 18:13, Ard Biesheuvel wrote:
>> On 7 November 2017 at 18:09, Laszlo Ersek wrote:
>>> On 11/05/17 17:29, Ard Biesheuvel wrote:
On 5 November 2017 at 16:27, Ard Biesheuvel
Hi Jian,
I'm CC'ing Ard and Matt, and commenting at the bottom.
On 11/10/17 02:02, Jian J Wang wrote:
>> v5:
>>Coding style clean-up
>
>> v4:
>> a. Remove DoUpdate and check attributes mismatch all the time to avoid
>>a logic hole
>> b. Add warning message if failed to update capability
Add a description of the SoCs GPIO controller as well as a description
of DIP switch block #3, which is wired to GPIOs 0 - 7, both on the
evaluation board as well as the Developer Box.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel
This adds support for the first working sample of the MZSC2AM board,
revision 0.1
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel
Reviewed-by: Leif Lindholm
---
Add a driver that produces the I2C master protocol on top of the I2C
controllers that are implemented in the SynQuacer Socionext SoC. Note
that this supports two modes simultaneously: I2C controllers that are
only usable at boot time, and usable via the I2C protocol stack, and
I2C controllers that
Ordinary computers typically have a physical switch or jumper on the
board that allows non-volatile settings to be cleared. Let's implement
the same using DIP switch #1 on block #3, and clear the EFI variable
store if it is set to ON at boot time.
Contributed-under: TianoCore Contribution
Add a DT node for the external interrupt unit (EXIU), which handles
interrupts from GPIO lines. We need OS support for this for things
like PHY interrupts and a 'wake' button.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel
In preparation of adding support for setting a DIP switch to clear the
EFI variable store, update the early capsule handling logic to take the
boot mode into account.
This is necessary for two reasons:
- we override the boot mode when a capsule is detected,
- the capsule detection itself involves
Describe the SynQuacer SoC's eMMC controller in DT so the OS can
attach to it.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel
---
Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 26
1 file changed, 26
In order to be able to sample the state of the DIP switches at early
boot on the Developer Box platform, implement the GPIO PPI based on
the GPIO block that is implemented in the SynQuacer SoC.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel
Add the drivers required to use the onboard eMMC on the SynQuacer
Evaluation Board.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel
---
NOTE: this depends on an upstream EDK2 change that is currently still under
discussion
Add the power button as a gpio-keys KEY_POWER button, and mark it as
a wakeup source so it can be used under the OS both as a 'sleep' and
as a 'wake' button.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel
---
Invoke the newly introduced SD/MMC override protocol to override
the capabilities register after reading it from the device registers,
and to call the pre/post host init and reset hooks at the appropriate
times.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel
Many ARM based SoCs have integrated SDHCI controllers, and often,
these implementations deviate in subtle ways from the pertinent
specifications. On the one hand, these deviations are quite easy
to work around, but on the other hand, having a collection of SoC
specific workarounds in the generic
Many SDHCI implementations exist that are almost spec complicant, and
could be driver by the generic SD/MMC host controller driver except
for some minimal necessary init time tweaks.
Adding such tweaks to the generic driver is undesirable. On the other
hand, forking the driver for every platform
On 10 November 2017 at 15:49, Laszlo Ersek wrote:
> This allows the PEI core to report the maximum temporary SEC/PEI stack
> usage on the DEBUG_INFO level, in the PeiCheckAndSwitchStack() function
> [MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c]:
>
> * Normal boot:
>
>> Temp
Add a package .DEC description for SynQuacer with an [Includes]
section, and add header files containing descriptions of the
platform's memory map and PCIe configuration. No code yet.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel
Implement the glue library that exposes the PCIe root complexes to
the generic PCI host bridge driver. Since that driver is the first
one to access the PCI config space, put the low level init code for
the RCs into this library's constructor.
Contributed-under: TianoCore Contribution Agreement
Having two distinct root complexes is not supported by the standard
set of PciLib/PciExpressLib/PciSegmentLib, so let's reimplement one
of the latter specifically for this platform (and forget about the
others).
This also allows us to implement the Synopsys Designware PCIe specific
workaround for
Create a specialized PlatformPeiLib implementation that invokes the
platform specific firmware interface (currently, just a data structure
left in SRAM) to set the ARM standard PcdSystemMemoryBase|Size PCDs,
and expose the information via a newly added DramInfo PPI.
Contributed-under: TianoCore
(1) In the PEI phase, the PCD database is maintained in a GUID HOB. In
OVMF, we load the PCD PEIM before any other PEIMs (using APRIORI PEI),
so that all other PEIMs can use dynamic PCDs. Consequently,
- the PCD GUID HOB is initially allocated from the temporary SEC/PEI
heap,
This allows the PEI core to report the maximum temporary SEC/PEI stack
usage on the DEBUG_INFO level, in the PeiCheckAndSwitchStack() function
[MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c]:
* Normal boot:
> Temp Stack : BaseAddress=0x814000 Length=0x4000
> Temp Heap : BaseAddress=0x81
This allows the PEI core to report the maximum temporary SEC/PEI stack
usage on the DEBUG_INFO level, in the PeiCheckAndSwitchStack() function
[MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c]:
* Normal boot:
> Temp Stack : BaseAddress=0x814000 Length=0x4000
> Temp Heap : BaseAddress=0x81
Currently EAX is used as an intermediary in setting ESP to
SEC_TOP_OF_STACK, and in passing SEC_TOP_OF_STACK to
SecCoreStartupWithStack() as the "TopOfCurrentStack" argument.
In a later patch we'll use EAX differently, so replace it with EBX under
the current use.
Cc: Ard Biesheuvel
Add the NETSEC driver to the SynQuacerEvalBoard platform.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel
Reviewed-by: Leif Lindholm
---
Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 46
From: Pipat Methavanitpong
This imports the driver sources provided by Socionext for the FIP006
SPI NOR flash device found on SynQuacer SoCs. It has been slightly
tweaked to bring it up to date with the changes made on the EDK2 side
since it was forked.
The SynQuacer SOC has two separate PCIe RCs, which means there is
no single value for the translation offset between I/O port accesses
and MMIO accesses. So add a special implementation of EFI_CPU_IO2_PROTOCOL
that takes the two disjoint I/O windows into account.
Contributed-under: TianoCore
This implements a driver that will take care of platform specific
initialization, such as declaring non-discoverable devices, and
installing the device tree blob as a configuration table.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel
This is a barebones port based on the .DSC/.FDF and ArmPlatformLib
code provided by Socionext. It can boot into the UiApp menu screen
or the UEFI Shell, but lacks support for any peripherals.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel
Add the platform glue for the NOR flash driver.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel
Reviewed-by: Leif Lindholm
---
Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c
Add a device tree description of the SynQuacer SoC, and expose it for
the SynQuacerEvalBoard platforms. This includes the menu option in the
UEFI boot menu to switch between ACPI and DT.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel
In order to support capsule update, implement PlatformFlashAccessLib that
exposes write access to the UEFI NOR partition.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel
Reviewed-by: Leif Lindholm
---
Wire up the various drivers and libraries for the SynQuacerEvalBoard
platform. Also enable the usual PCI suspects: XHCI, SATA and NVME,
and the various bus, partition and file system drivers that we need
to make use of PCIe devices.
Given how PCI support enables USB support too, and taking the
Wire up the non-volatile EFI variable store support, by switching from
the emulation driver to the real one, and enabling the prerequisite
FTW and NOR flash drivers.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel
Reviewed-by: Leif
Implement MemoryInitPeiLib based on the newly added DramInfo
PPI, which retrieves the DRAM information from lower level
firmware.
Note that the firmware volumes in SPI NOR are mapped with
different attributes: the FV containing the PEI modules that
may execute in place is mapped as uncached
Add support for dealing with capsules left in memory by the OS before
reboot. This needs to be done early, before the memory is reused, which
is why the initial handling must reside here.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel
Add all the boilerplate to make the SPI NOR image updateable using
signed capsules and the FMP protocol.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel
Reviewed-by: Leif Lindholm
---
Now that we switched to PrePeiCore, we can execute the firmware image
in place, using a stack and temporary heap in non-secure SRAM. This
allows us to query the secure firmware for the size and placement of
DRAM, and also allows the use of capsules for firmware update.
NOTE: this requires ARM
This adds support for the Socionext Synquacer SC2A11 evaluation board
and revision 0.1/0.2 of the Developer Box.
It implements support for the core peripherals (CPU, GIC, serial), and
for the two PCIe RCs present on this board, as well as the NETSEC network
controller.
The DT description
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel
Reviewed-by: Leif Lindholm
---
Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 7 ++-
Implement workaround suggested by Socionext to get legacy endpoints
with 32-bit BARs working. This fixes the issue on Developer Box with
the onboard ASM1061 SATA controller.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel
In order to improve the 'out of the box' experience when booting
this system with a monitor and keyboard attached, include the serial
console preference driver that prevents the installer GUI to only
appear on the serial port in this case.
Contributed-under: TianoCore Contribution Agreement 1.1
On 11/10/17 19:11, Laszlo Ersek wrote:
> On 11/10/17 16:56, Ard Biesheuvel wrote:
>> On 10 November 2017 at 15:49, Laszlo Ersek wrote:
>>> This allows the PEI core to report the maximum temporary SEC/PEI stack
>>> usage on the DEBUG_INFO level, in the PeiCheckAndSwitchStack()
On 11/10/17 16:56, Ard Biesheuvel wrote:
> On 10 November 2017 at 15:49, Laszlo Ersek wrote:
>> This allows the PEI core to report the maximum temporary SEC/PEI stack
>> usage on the DEBUG_INFO level, in the PeiCheckAndSwitchStack() function
>>
I would submit a patch but over the years of fixes and enhancements,
they don't go anywhere. Then a couple years later someone does a
half-baked fix and I have to run merge resolution on svn.
Anyway, the problem with that is the s1 compare to 0 should be before
the s1++ (otherwise it matches when
Hello,
Here are some observations I've encountered trying to utilize edk2 for
certain builds. Part of the problem seems to be with implicit
assumptions in how edk2 is used. I'm trying to build things using edk2
from a clean enviroment on an automated builder. i.e. there isn't a
workspace that
Hi Ray,
On 11/10/17 01:52, Ni, Ruiyu wrote:
>
>
>> -Original Message-
>> From: Laszlo Ersek [mailto:ler...@redhat.com]
>> Sent: Thursday, November 9, 2017 9:16 PM
>> To: Ni, Ruiyu ; Justen, Jordan L
>> ; Jeff Fan
RealTimeClockRuntimeDxe defers the hardware/platform specific handling
of reading/setting the hardware clock to RealTimeClockLib, but for
unknown reasons, it also defers common functionality such as input
validation and recording the timezone and DST settings (which are
informational only and not
This library, which is intended to encapsulate the hardware specifics
of the ARM PL031 RTC, also implements its own input validation routines
and record the timezone and DST settings in its own set of EFI variables.
This functionality has recently been added to the core driver, so let's
remove it
This moves input validation and recording of the DST and timezone settings
(which cannot usually be done by the hardware) into the core RTC driver in
EmbeddedPkg, and removes it from one of the RealTimeClockLib implementations,
the one for the ARM PL031.
v3: fix leap day assert condition
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