2017-06-20 23:35 GMT+03:00 Peter C. Wallace :
>
>> This is not unexpected, the card is probably fine
>
> The 7I47S has differential inputs, They are not designed to interface with
> single ended signals but can if needed.
>
> The only way the inputs will work reliably is to have
On Tue, 20 Jun 2017, Andrew wrote:
Date: Tue, 20 Jun 2017 22:33:43 +0300
From: Andrew <pkm...@gmail.com>
Reply-To: "Enhanced Machine Controller (EMC)"
<emc-users@lists.sourceforge.net>
To: "Enhanced Machine Controller (EMC)" <emc-users@lists.sourceforge
2017-06-17 20:15 GMT+03:00 Andrew:
> 2017-06-17 18:34 GMT+03:00 Danny Miller:
>
>> Similarly the inputs aren't true differential, they're an optoisolator's
>> input diode with a series resistor to produce the rated trigger current
>> when +5v is applied + to -. Due to some esoteric details in
2017-06-17 18:34 GMT+03:00 Danny Miller:
> That's not a true differential output. It's an optoisolator's two output
> terminals. Since they're isolated, neither terminal is tied to a gnd or +
> so you can connect it high or low.
>
> When tripped, it conducts current (supplied externally) from +
That's not a true differential output. It's an optoisolator's two
output terminals. Since they're isolated, neither terminal is tied to a
gnd or + so you can connect it high or low.
When tripped, it conducts current (supplied externally) from + to -. It
cannot generate its own voltage,
Hello,
The stepper drive has open collector alarm output.
Can I use a differential RX input on 7i47s to read it?
Thanks
Andrew
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2017-04-06 22:43 GMT+03:00 Peter C. Wallace:
>
> As far as I can tell from the source the svst1_4_7i47S does put stepgen 0
> at
> TX4,TX5 Stepgen 1 at TX6,TX7, stepgen 2 at TX0,TX1 and stepgen 3 at TX2,TX3
>
Right! That's what I observed.
Err... now I see that it's in the manual, J1 pinout..
users@lists.sourceforge.net>
> Subject: [Emc-users] Mesa 7i47S issue
>
> Hello!
>
> I've been testing 7i80 (7i80hd_16_svst1_4_7i47s.bit) with 7i47S.
> According to the manual and hm2 load report I should have stepgen0..3 at
> TX0...TX7 outputs.
> But what I seem to have is
Hello!
I've been testing 7i80 (7i80hd_16_svst1_4_7i47s.bit) with 7i47S.
According to the manual and hm2 load report I should have stepgen0..3 at
TX0...TX7 outputs.
But what I seem to have is stepgen0..1 at TX4...7, stepgen2..3 is at TX0..3.
This is pretty confusing.
Or am I missing something?