r post text ...
From: flashrom on behalf of Sandy Zhang
Sent: Monday, August 14, 2017 4:36:00 AM
To: David Hendricks
Cc: flashrom@flashrom.org
Subject: Re: [flashrom] When flashrom support Intel Purley platform Lewisburg
PCH?
Hi David,
Lewisburg PCH defines sixty SPI region
Hi David,
Lewisburg PCH defines sixty SPI regions, but from the code in ichspi.c, I
find it defines only 10 regions, is this the reason about only 10 regions
was described in the log file?
code as below: (num_freg define the spi regions)
int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
{
Hi David,
About set permissions for the "BIOS" master via BRWA and BRRA in the FRACC
register, do you mean modify the below location by FITC.exe? if yes, I have
changed the "Host CPU/BIOS Write Access" & "Host CPU/BIOS Read Access"'s value
to 0x to enable all the sixty region's access, but the
On Sun, Aug 13, 2017 at 6:26 PM, Sandy Zhang wrote:
> Hi David,
>
> I'm inline.
>
I don't see your responses. Did you intend to reply to my comments?
>
> 2017-08-14 9:17 GMT+08:00 David Hendricks :
>
>> Hi Sandy,
>>
>> Responses in-line.
>>
>> On Fri, Aug 11, 2017 at 1:38 AM, Sandy Zhang
>> w
Hi David,
I'm inline.
2017-08-14 9:17 GMT+08:00 David Hendricks :
> Hi Sandy,
>
> Responses in-line.
>
> On Fri, Aug 11, 2017 at 1:38 AM, Sandy Zhang
> wrote:
>
>> Hi David,
>>
>> Sorry, I have a doubt about the range outside, from the binary map,
>> we can find the Spare 3 Region size is
Hi Sandy,
Responses in-line.
On Fri, Aug 11, 2017 at 1:38 AM, Sandy Zhang wrote:
> Hi David,
>
> Sorry, I have a doubt about the range outside, from the binary map,
> we can find the Spare 3 Region size is 0x00FF - 0xFF + 1 = 0x1,
> and the binary size map to this range is also
Hi Sandy,
That range is outside of what you have defined in your flash descriptor.
Can you update your flash descriptor to include it?
On Thu, Aug 10, 2017 at 4:43 AM, Sandy Zhang wrote:
> Hi David,
>
> I have used your program to verify, but it still can't flash, it prompts
> "Transaction erro
Hi David,
I have used your program to verify, but it still can't flash, it prompts
"Transaction error between offset 0x00ff and 0x00ff003f (= 0x00ff003f
+ 63)"!
2017-08-10 15:29 GMT+08:00 David Hendricks :
> Hi Sandy,
> Recent Intel PCHs use hardware sequencing which abstracts a lot of
Hi Sandy,
Recent Intel PCHs use hardware sequencing which abstracts a lot of details
about the chip. So we don't actually need flashrom to explicitly support
the W25Q256.
Here is a tarball based on the latest sources from git:
https://drive.google.com/file/d/0Bz3WBh8gVeIuSlJYZ2c1bS1LdGc/view?usp=s
Hi David,
I have get the package from the web, but I can't find the code about
"25Q256" in flashchip.c, so, maybe this will lead to flash fail.
2017-08-09 15:11 GMT+08:00 Sandy Zhang :
> Hi David,
>
> Yes, My system's ISA/LPC vendor id and device id is 8086:a1c6,
> In fact, I can't access the cl
Hi David,
Yes, My system's ISA/LPC vendor id and device id is 8086:a1c6,
In fact, I can't access the clone https://review.coreboot.org/flashrom.git,
I attempt to add the patch to flashrom-0.9.9, but I found the difference
is a bit big between these files, I'm very hard to add the
patch completely
Hi Sandy,
What is the result of `lspci -nn | grep ISA` on your system? I uploaded a
patch for Lewisburg PCI IDs here: https://review.coreboot.org/#/c/20922/
I have tested Lewisburg PCH + W25Q256xxx and it seems to work. Let me know
if you need any help applying the patch and testing it out on your
Hi David,
Do you know whether the configuration "Lewisburg PCH + W25Q256xxx SPI" has
been tested with the flashrom? thank you!
2017-08-08 3:55 GMT+08:00 David Hendricks :
> Hi Sandy,
> Correct - The PCH will not allow us to write anything to regions which are
> not defined in the flash desc
Hi Sandy,
Correct - The PCH will not allow us to write anything to regions which are
not defined in the flash descriptor. You could add those regions to the
"BIOS" region if you wish to update them from your host OS. The SPI
Programming Guide for your PCH (Lewisburg?) should also have info about
ad
Hi David,
It seems that the below 2 regions are "write denied":
00A26000 00A35FFF 0001DER #1 Region
00A36000 00FE 005BA00010 Gbe A Region
By the way, can you tell me what is the other parament "EW", "S" and "E"
meana? thank you!
2017-08-07 13:02 GM
Hi Sandy,
It might not have done what you expect. The error is because offsets
0xa26000-0xff are not defined in the flash descriptor, so the PCH gives
us an error when flashrom attempts to update it. ":WD" next to the offsets
in the log means "write denied".
If you wish to update that region o
Hi David,
Thank you very much, I will try to add the patch to flashrom-0.9.9, As a
BIOS engineer, it is a bit difficult for me to complete this.
Do you know when will make it into a release tarball?
BR
Sandy
2017-08-05 0:05 GMT+08:00 David Hendricks :
> On Aug 3, 2017 11:51 PM, "Sandy Zhang"
On Aug 3, 2017 11:51 PM, "Sandy Zhang" wrote:
> Hi David,
>
> Thanks for your reply, can you tell me where to download the flash package
> like "flashrom-0.9.9.tar" which is downloaded from the address ''
> https://www.flashrom.org/Downloads";? thank you!
>
The Skylake patches have not made it
Hi David,
Thanks for your reply, can you tell me where to download the flash package
like "flashrom-0.9.9.tar" which is downloaded from the address ''
https://www.flashrom.org/Downloads";? thank you!
BR
Sandy
2017-08-04 14:35 GMT+08:00 David Hendricks :
> Hi Sandy,
> Skylake support was rec
Hi Sandy,
Skylake support was recently merged: https://review.coreboot.org/18973
However you may need to add your PCH PCI ID. What does `lspci -nn | grep
LPC` show on your test system?
And yes, a 32MB ROM should work fine.
On Mon, Jul 31, 2017 at 4:11 AM, Sandy Zhang wrote:
> Hi,
>
> Can you t
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