>>: Jecel Assumpcao Jr
>> The key thing is to have some model of parallelism which is used by the
>> source code. If you try to extract automatically parallelism from
>> "normal" application code you will just make things needlessly
>> complicated for yourself.
>: Nathan Cain
>
> Precisely. You
Hello, I've just joined this list but I've been following the posts for a
while, along with the whitepapers and software on the VPRI site. I've also
written http://en.wikipedia.org/wiki/COLA_(software_architecture) (and was
given a much-appreciated thank-you from Ian Piumarta), but now that I've
On Tue, Mar 3, 2009 at 2:34 PM, Jecel Assumpcao Jr wrote:
> The key thing is to have some model of parallelism which is used by the
> source code. If you try to extract automatically parallelism from
> "normal" application code you will just make things needlessly
> complicated for yourself.
>
> -
On Mon, Mar 2, 2009 at 11:42 PM, Luke Breuer wrote:
> On Mon, Mar 2, 2009 at 10:15 AM, Nathan Cain > wrote:
>
>> I am wondering what work is being done/planned for targeting FPGA
>> platforms. My interests overlap with this field, and I would like to
>> contribute towards such an effort. I hav
Gerardo Richarte wrote on Tue, 03 Mar 2009 09:14:50 -0200
> Hi Ian,
>
> Ian Piumarta wrote:
> > I'd love to see somebody figure out how to dynamically generate bit
> > files from an intermediate representation (Jolt ASTs, for example) to
> > allow reprogramming of the hardware on the fly.
> Take a
Hi Ian,
Ian Piumarta wrote:
> I'd love to see somebody figure out how to dynamically generate bit
> files from an intermediate representation (Jolt ASTs, for example) to
> allow reprogramming of the hardware on the fly.
Take a look at project Madeo
(http://www.esug.org/Conferences/2008/Innovation+
