On 07/02/2013 01:37 PM, Marco van de Voort wrote:
Any device whose I/O is not galvanically isolated and shortcut proof
is not suitable for true embedded usage.
That is why the BBB is done as a mezzanine (piggyback) board./
-Michael
/
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fpc-devel
Jonas: please excuse this, I'm trying to keep it relevant.
Michael Schnell wrote:
Something like RTLinux with the equivalent of a PLC implemented at the
core level is obviously one solution to this sort of problem.
This again is why I vote for the BBB. The TI CPU chip used, features two
ARM
On 07/03/2013 10:11 AM, Mark Morgan Lloyd wrote:
Do you have any URLs etc. for the BBB in this context?
This has close to nothing to do with the BeagleBone board: it's just a
processor feature. The BeagleBone board in fact supports it as several
pins of the chips that can internally be
Michael Schnell wrote:
On 07/03/2013 10:11 AM, Mark Morgan Lloyd wrote:
Do you have any URLs etc. for the BBB in this context?
This has close to nothing to do with the BeagleBone board: it's just a
processor feature. The BeagleBone board in fact supports it as several
pins of the chips
On 07/03/2013 12:36 PM, Mark Morgan Lloyd wrote:
So there's a (slight) risk that a careless kernel on the main CPU
could mess up something safety-critical, or at least (as you've said)
could have a small effect on timing.
Not at all if you only use the PRUS vicinity hardware interface. If you
Michael Schnell wrote:
On 07/03/2013 10:11 AM, Mark Morgan Lloyd wrote:
Do you have any URLs etc. for the BBB in this context?
This has close to nothing to do with the BeagleBone board: it's just a
processor feature. The BeagleBone board in fact supports it as several
pins of the chips that
On 07/03/2013 03:35 PM, Mark Morgan Lloyd wrote:
It looks as though the PRU is a custom design (i.e. not an ARM
derivative) which TI has also used in some of the OMAP series,
Nope while the AM17xxx processors dud use a custom design for the
coprocessors, the AM335x uses ARM Cortex M3
