On Mon, Jan 12, 2015 at 05:21:24PM +0100, Micha?? Stanek wrote:
> OK, I added AHCI_Q_ABAR0 as a new quirk and test the bit in
> ahci_pci_attach. It works the same. New patch is in the attachment.
>
Committed as r277100.
Thank you.
___
freebsd-current@fr
2015-01-09 18:27 GMT+01:00 Konstantin Belousov :
> On Fri, Jan 09, 2015 at 06:07:39PM +0100, Micha?? Stanek wrote:
> > 2015-01-08 21:40 GMT+01:00 Konstantin Belousov :
> >
> > > > However, if
> > > > AHCI uses 64-bit base addresses, then this register consists of two
> > > dwords
> > > > starting
On Fri, Jan 09, 2015 at 06:07:39PM +0100, Micha?? Stanek wrote:
> 2015-01-08 21:40 GMT+01:00 Konstantin Belousov :
>
> > > However, if
> > > AHCI uses 64-bit base addresses, then this register consists of two
> > dwords
> > > starting at offset 0x20 - BAR4 and BAR5. This is the case on our arm64
>
2015-01-08 21:40 GMT+01:00 Konstantin Belousov :
> > However, if
> > AHCI uses 64-bit base addresses, then this register consists of two
> dwords
> > starting at offset 0x20 - BAR4 and BAR5. This is the case on our arm64
> > target and possibly other platforms using 64-bit BARs for AHCI.
> Is it s
On Thu, Jan 08, 2015 at 05:09:23PM +0100, Micha?? Stanek wrote:
> Hello all,
>
> I ran into an issue with AHCI BAR allocation on arm64. The AHCI PCI driver
> in sys/dev/ahci/ahci_pci.c assumes that ABAR (AHCI Base Address) register
> is located at offset 0x24 (BAR5) in the PCI header. Specificatio
> On Jan 8, 2015, at 9:09 AM, Michał Stanek wrote:
>
>
This looks good to my eyes… Given the ordering of the words in the BAR,
you won’t get false positives. It uses the PCI bus code to make the
determination, which eliminates duplication of code in drivers… I like it.
Warner
signature.asc
Sep 17 00:00:00 2001
From: Michal Stanek
Date: Wed, 7 Jan 2015 18:28:18 +0100
Subject: [PATCH] Add support for 64-bit AHCI BAR.
---
sys/dev/ahci/ahci_pci.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/sys/dev/ahci/ahci_pci.c b/sys/dev/ahci/ahci_pci.c
ind
