Re: Please test PAUSE on non-Intel processors
CPU: Cyrix 486DX2 (486-class CPU) Origin = "CyrixInstead" DIR=0xa01b Stepping=10 Revision=0 # ./pausetest Testing PAUSE instruction: Register esp changed: 0xbfbffd04 -> 0xbfbffcc8 -- Bob Bishop +44 (0)118 977 4017 [EMAIL PROTECTED]fax +44 (0)118 989 4254 To Unsubscribe: send mail to [EMAIL PROTECTED] with "unsubscribe freebsd-current" in the body of the message
Re: Please test PAUSE on non-Intel processors
I get: stylus:~$ cc pausetest.c stylus:~$ ./a.out Testing PAUSE instruction: Register esp changed: 0xbfbff79c -> 0xbfbff760 .. I assume this is functional. =) I have: CPU: AMD Athlon(tm) MP 1900+ (1592.90-MHz 686-class CPU) Origin = "AuthenticAMD" Id = 0x662 Stepping = 2 Features=0x383fbff AMD Features=0xc048 Programming 24 pins in IOAPIC #0 IOAPIC #0 intpin 2 -> irq 0 FreeBSD/SMP: Multiprocessor System Detected: 2 CPUs cpu0 (BSP): apic id: 1, version: 0x00040010, at 0xfee0 cpu1 (AP): apic id: 0, version: 0x00040010, at 0xfee0 io0 (APIC): apic id: 2, version: 0x00170011, at 0xfec0 Pentium Pro MTRR support enabled Using $PIR table, 268435454 entries at 0xc00fdef0 John Baldwin [[EMAIL PROTECTED]] wrote : > Hey gang, although Intel's document seems to claim that they tested > proper operation of pause I'd like people with non-Intel processors > to verify that it actually works. Please compile the attached test > program and run it. The output should look like this: > > > ./pt > Testing PAUSE instruction: > Register esp changed: 0xbfbff9fc -> 0xbfbff9c0 > > If you get a signal or any of the other registers change their value, > please let me know. I've tested this on a Pentium III mobile, a K6-II, > and an Athlon. The program cmopiles ok on both stable and current. > > -FW: <[EMAIL PROTECTED]>- > > Date: Tue, 21 May 2002 15:26:36 -0700 (PDT) > Sender: [EMAIL PROTECTED] > From: John Baldwin <[EMAIL PROTECTED]> > To: [EMAIL PROTECTED], [EMAIL PROTECTED] > Subject: cvs commit: src/sys/kern kern_mutex.c > > jhb 2002/05/21 15:26:36 PDT > > Modified files: > sys/kern kern_mutex.c > Log: > Add appropriate IA32 "pause" instructions to improve performanec on > Pentium 4's and newer IA32 processors. The "pause" instruction has been > verified by Intel to be a NOP on all currently existing IA32 processors > prior to the Pentium 4. > > Revision ChangesPath > 1.95 +17 -1 src/sys/kern/kern_mutex.c > > --End of forwarded message- > > -- > > John Baldwin <[EMAIL PROTECTED]> <>< http://www.FreeBSD.org/~jhb/ > "Power Users Use the Power to Serve!" - http://www.FreeBSD.org/ Content-Description: pausetest.c > /* > * Simple program to see if the new IA32 PAUSE instruction works properly. > * We test two different things: 1) that we don't get an illegal instruction > * fault, and 2) that no registers change state. > */ > > #include > #include > > #define NUM_SEGREGS 6 > #define NUM_REGS15 > > #define PUSH_REGS \ > " pushf ;\n" \ > " pusha ;\n" \ > " push %cs ;\n" \ > " push %ds ;\n" \ > " push %es ;\n" \ > " push %fs ;\n" \ > " push %gs ;\n" \ > " push %ss ;\n" > > const char *register_names[NUM_REGS] = { > "ss", "gs", "fs", "es", "ds", "cs", > "edi", "esi", "ebp", "esp", "ebx", "edx", "ecx", "eax", > "eflags" > }; > > struct register_set { > register_t r_regs[NUM_REGS]; > /* > register_t r_ss; > register_t r_gs; > register_t r_fs; > register_t r_es; > register_t r_ds; > register_t r_cs; > register_t r_edi; > register_t r_esi; > register_t r_ebp; > register_t r_isp; > register_t r_ebx; > register_t r_edx; > register_t r_ecx; > register_t r_eax; > register_t r_eflags; > */ > }; > > void > compare_registers(struct register_set after, struct register_set before) > { > int i; > > for (i = 0; i < NUM_SEGREGS; i++) { > before.r_regs[i] &= 0x; > after.r_regs[i] &= 0x; > } > for (i = 0; i < NUM_REGS; i++) > if (before.r_regs[i] != after.r_regs[i]) > printf("Register %s changed: %#x -> %#x\n", > register_names[i], before.r_regs[i], > after.r_regs[i]); > } > > void > test_pause(void) > { > __asm __volatile( > " mov $10,%ecx ;\n" > PUSH_REGS > " pause ;\n" > PUSH_REGS > " call compare_registers ;\n" > " addl $0x78,%esp ;\n"); > } > > int > main(int ac, char **av) > { > > printf("Testing PAUSE instruction:\n"); > test_pause(); > return (0); > } -- Jonathan Mini <[EMAIL PROTECTED]> http://www.haikugeek.com "He who is not aware of his ignorance will be only misled by his knowledge." -- Richard Whatley To Unsubscribe: send mail to [EMAIL PROTECTED] with "unsubscribe freebsd-current" in the body of the message
Re: Please test PAUSE on non-Intel processors
On Fri, 24 May 2002 10:25:53 -0400 (EDT) John Baldwin <[EMAIL PROTECTED]> wrote: > Hey gang, although Intel's document seems to claim that they tested > proper operation of pause I'd like people with non-Intel processors > to verify that it actually works. Please compile the attached test > program and run it. The output should look like this: > > > ./pt > Testing PAUSE instruction: > Register esp changed: 0xbfbff9fc -> 0xbfbff9c0 > > If you get a signal or any of the other registers change their value, > please let me know. I've tested this on a Pentium III mobile, a > K6-II, and an Athlon. The program cmopiles ok on both stable and > current. > CPU: AMD Athlon(tm) Processor (1210.79-MHz 686-class CPU) Origin = "AuthenticAMD" Id = 0x642 Stepping = 2 Features=0x183f9ff AMD Features=0xc044<,AMIE,DSP,3DNow!> [earth] /home/paul/temp: uname -v FreeBSD 4.5-STABLE #0: Wed Feb 27 03:19:35 EST 2002 [EMAIL PROTECTED]:/usr/obj/usr/src/sys/EARTH [earth] /home/paul/temp: ./pausetest Testing PAUSE instruction: Register esp changed: 0xbfbffa54 -> 0xbfbffa18 -- Cogeco ergo sum msg38778/pgp0.pgp Description: PGP signature
Re: Please test PAUSE on non-Intel processors
* John Baldwin <[EMAIL PROTECTED]> [2002-05-24 08:27]: > Hey gang, although Intel's document seems to claim that they tested > proper operation of pause I'd like people with non-Intel processors > to verify that it actually works. Please compile the attached test > program and run it. The output should look like this: > > > ./pt > Testing PAUSE instruction: > Register esp changed: 0xbfbff9fc -> 0xbfbff9c0 > CPU: AMD Athlon(tm) XP 1800+ (1534.00-MHz 686-class CPU) Origin = "AuthenticAMD" Id = 0x662 Stepping = 2 Features=0x383fbff AMD Features=0xc048<,AMIE,DSP,3DNow!> Testing PAUSE instruction: Register esp changed: 0xbfbffb44 -> 0xbfbffb08 To Unsubscribe: send mail to [EMAIL PROTECTED] with "unsubscribe freebsd-current" in the body of the message
RE: Please test PAUSE on non-Intel processors
On 24-May-2002 (14:25:53/GMT) John Baldwin wrote: > Please compile the attached test program and run it... FreeBSD 5.0-CURRENT #34: Wed May 8 02:31:46 CEST 2002 CPU: Pentium III/Pentium III Xeon/Celeron (501.14-MHz 686-class CPU) Origin = "GenuineIntel" Id = 0x672 Stepping = 2 Features=0x387fbff [...] FreeBSD/SMP: Multiprocessor System Detected: 2 CPUs # ./pausetest Testing PAUSE instruction: Register esp changed: 0xbfbff7dc -> 0xbfbff7a0 FreeBSD 4.5-STABLE #9: Mon Apr 22 16:54:08 CEST 2002 CPU: IDT WinChip 2 (199.90-MHz 586-class CPU) Origin = "CentaurHauls" Id = 0x585 Stepping = 5 Features=0x8000b5 # ./pausetest Testing PAUSE instruction: Register esp changed: 0xbfbffb98 -> 0xbfbffb5c FreeBSD 4.5-STABLE #4: Mon Apr 22 17:39:58 GMT 2002 CPU: IDT WinChip C6 (199.74-MHz 586-class CPU) Origin = "CentaurHauls" Id = 0x541 Stepping = 1 Features=0x8000b5 # ./pausetest Testing PAUSE instruction: Register esp changed: 0xbfbffb9c -> 0xbfbffb60 FreeBSD 4.4-STABLE #3: Sun Sep 25 11:26:23 GMT 2001 CPU: i486 SX2 (486-class CPU) Origin = "GenuineIntel" Id = 0x45b Stepping = 11 Features=0x2 # ./pausetest Testing PAUSE instruction: Register esp changed: 0xbfbffba0 -> 0xbfbffb64 FreeBSD 4.5-STABLE #3: Mon Apr 22 14:54:18 GMT 2002 CPU: Cyrix 6x86MX (200.46-MHz 686-class CPU) Origin = "CyrixInstead" Id = 0x600 Stepping = 0 DIR=0x0753 Features=0x80a135 # ./pausetest Testing PAUSE instruction: Register esp changed: 0xbfbffbb8 -> 0xbfbffb7c Riccardo. To Unsubscribe: send mail to [EMAIL PROTECTED] with "unsubscribe freebsd-current" in the body of the message
Re: Please test PAUSE on non-Intel processors
At Fri, 24 May 2002 10:25:53 -0400 (EDT), John Baldwin wrote: > Hey gang, although Intel's document seems to claim that they tested > proper operation of pause I'd like people with non-Intel processors > to verify that it actually works. It works fine on my Transmeta Crusoe TM5600, about as non-intel as you can get: Testing PAUSE instruction: Register esp changed: 0xbfbffa0c -> 0xbfbff9d0 dmesg excerpt: FreeBSD 5.0-CURRENT #0: Sun Apr 28 16:02:43 GMT 2002 root@nomad:/usr/obj/usr/src/sys/NOMAD CPU: Transmeta(tm) Crusoe(tm) Processor TM5600 (595.50-MHz 586-class CPU) Origin = "GenuineTMx86" Id = 0x543 real memory = 184483840 (180160K bytes) avail memory = 174391296 (170304K bytes) -Peter- To Unsubscribe: send mail to [EMAIL PROTECTED] with "unsubscribe freebsd-current" in the body of the message
Re: Please test PAUSE on non-Intel processors
Itanium running x86 binaries: CPU: Itanium (800.03-Mhz) Origin = "GenuineIntel" Model = 0 Revision = 4 Features = 0x0 ia64# ./pausetest Testing PAUSE instruction: Register esp changed: 0xdbc4 -> 0xdb88 ia64# file ./pausetest ./pausetest: ELF 32-bit LSB executable, Intel 80386, version 1 (FreeBSD), statically linked, not stripped Yes, we do run with x86 userland VM size = 4GB on freebsd/ia64 since the kernel is elsewhere :-) Cheers, -Peter -- Peter Wemm - [EMAIL PROTECTED]; [EMAIL PROTECTED]; [EMAIL PROTECTED] "All of this is for nothing if we don't go to the stars" - JMS/B5 To Unsubscribe: send mail to [EMAIL PROTECTED] with "unsubscribe freebsd-current" in the body of the message
Re: Please test PAUSE on non-Intel processors
CPU: AMD Athlon(tm) MP Processor (1194.68-MHz 686-class CPU) Origin = "AuthenticAMD" Id = 0x661 Stepping = 1 Features=0x383fbff AMD Features=0xc044 (%:~)- ./pausetest Testing PAUSE instruction: Register esp changed: 0xbfbff9c4 -> 0xbfbff988 -- vrak AKA Per-Arne Holtmon Akø E-mail: [EMAIL PROTECTED] ICQ UIN: 944 HP: http://home.online.no/~perarneh/ To Unsubscribe: send mail to [EMAIL PROTECTED] with "unsubscribe freebsd-current" in the body of the message
Re: Please test PAUSE on non-Intel processors
On Fri, May 24, 2002 at 10:25:53AM -0400, John Baldwin wrote: > Hey gang, although Intel's document seems to claim that they tested > proper operation of pause I'd like people with non-Intel processors > to verify that it actually works. Please compile the attached test > program and run it. The output should look like this: > > > ./pt > Testing PAUSE instruction: > Register esp changed: 0xbfbff9fc -> 0xbfbff9c0 > Intel Pentium 166/MMX: Testing PAUSE instruction: Register esp changed: 0xbfbffad8 -> 0xbfbffa9c AMD 386sx/33: Testing PAUSE instruction: Register esp changed: 0xbfbffb20 -> 0xbfbffae4 Both machines running 4.6-PRERELEASE -- Erik Trulsson [EMAIL PROTECTED] To Unsubscribe: send mail to [EMAIL PROTECTED] with "unsubscribe freebsd-current" in the body of the message
Re: Please test PAUSE on non-Intel processors
On Fri, 24 May 2002, John Baldwin wrote: > Hey gang, although Intel's document seems to claim that they tested > proper operation of pause I'd like people with non-Intel processors > to verify that it actually works. Please compile the attached test > program and run it. The only non-intel or AMD hardware I have access to is a debian linux box with a Cyrix 233 processor. gavin@gaspode:~$ cat /proc/cpuinfo vendor_id : CyrixInstead cpu family : 6 model : 2 model name : M II 3.5x Core/Bus Clock stepping: 8 cpu MHz : 233.863 flags : fpu de tsc msr cx8 pge cmov mmx cyrix_arr gavin@gaspode:~$ ./a.out Testing PAUSE instruction: Register esp changed: 0xbd68 -> 0xbd2c gavin@gaspode:~$ So no problem there. Hope that's useful. Gavin To Unsubscribe: send mail to [EMAIL PROTECTED] with "unsubscribe freebsd-current" in the body of the message
Re: Please test PAUSE on non-Intel processors
$ dmesg | head | tail -4 CPU: AMD Athlon(tm) XP 1700+ (1466.51-MHz 686-class CPU) Origin = "AuthenticAMD" Id = 0x662 Stepping = 2 Features=0x383f9ff AMD Features=0xc048<,AMIE,DSP,3DNow!> $ ./pt Testing PAUSE instruction: Register esp changed: 0xbfbff860 -> 0xbfbff824 To Unsubscribe: send mail to [EMAIL PROTECTED] with "unsubscribe freebsd-current" in the body of the message
Re: Please test PAUSE on non-Intel processors
On 2002-05-24 10:25, John Baldwin wrote: > Please compile the attached test program and run it. The output > should look like this: > > > ./pt > Testing PAUSE instruction: > Register esp changed: 0xbfbff9fc -> 0xbfbff9c0 Intel Pentium 133 here, the output looks fine: hades+charon:/tmp$ cc -o pausetest pausetest.c hades+charon:/tmp$ ./pausetest Testing PAUSE instruction: Register esp changed: 0xbfbff65c -> 0xbfbff620 - Giorgos To Unsubscribe: send mail to [EMAIL PROTECTED] with "unsubscribe freebsd-current" in the body of the message
Re: Please test PAUSE on non-Intel processors
On 24 Mai, John Baldwin wrote: > Hey gang, although Intel's document seems to claim that they tested > proper operation of pause I'd like people with non-Intel processors > to verify that it actually works. Please compile the attached test > program and run it. The output should look like this: > >> ./pt > Testing PAUSE instruction: > Register esp changed: 0xbfbff9fc -> 0xbfbff9c0 > > If you get a signal or any of the other registers change their value, > please let me know. I've tested this on a Pentium III mobile, a K6-II, > and an Athlon. The program cmopiles ok on both stable and current. CPU: AMD Duron(tm) Processor (801.83-MHz 686-class CPU) Origin = "AuthenticAMD" Id = 0x631 Stepping = 1 Features=0x183f9ff AMD Features=0xc044 (10) netchild@ttyp2 % ./pausetest Testing PAUSE instruction: Register esp changed: 0xbfbff424 -> 0xbfbff3e8 Bye, Alexander. -- Where do you think you're going today? http://www.Leidinger.net Alexander @ Leidinger.net GPG fingerprint = C518 BC70 E67F 143F BE91 3365 79E2 9C60 B006 3FE7 To Unsubscribe: send mail to [EMAIL PROTECTED] with "unsubscribe freebsd-current" in the body of the message
Re: Please test PAUSE on non-Intel processors
CPU: Cyrix 6x86MX (166.19-MHz 686-class CPU) Origin = "CyrixInstead" Id = 0x600 Stepping = 0 DIR=0x0452 Features=0x80a135 spambox2% ./pausetest Testing PAUSE instruction: Register esp changed: 0xbfbffbbc -> 0xbfbffb80 CPU: AMD Duron(tm) Processor (995.77-MHz 686-class CPU) Origin = "AuthenticAMD" Id = 0x670 Stepping = 0 Features=0x383f9ff AMD Features=0xc044<,AMIE,DSP,3DNow!> seagoon% ./pausetest Testing PAUSE instruction: Register esp changed: 0xbfbffb3c -> 0xbfbffb00 CPU: AMD-K6(tm) 3D processor (501.14-MHz 586-class CPU) Origin = "AuthenticAMD" Id = 0x58c Stepping = 12 Features=0x8021bf AMD Features=0x8800 hal%./pausetest Testing PAUSE instruction: Register esp changed: 0xbfbffb8c -> 0xbfbffb50 CPU: AMD-K6tm w/ multimedia extensions (233.86-MHz 586-class CPU) Origin = "AuthenticAMD" Id = 0x562 Stepping = 2 Features=0x8001bf atlas% ./pausetest Testing PAUSE instruction: Register esp changed: 0xbfbffbe4 -> 0xbfbffba8 -- Bob Bishop +44 (0)118 977 4017 [EMAIL PROTECTED]fax +44 (0)118 989 4254 To Unsubscribe: send mail to [EMAIL PROTECTED] with "unsubscribe freebsd-current" in the body of the message
Re: Please test PAUSE on non-Intel processors
I tested this on my T-bird athlon 800, and this is the result: Testing PAUSE instruction: Register esp changed: 0xbfbffb38 -> 0xbfbffafc So I guess there's no problem. Ken On Fri, 24 May 2002, John Baldwin wrote: > Hey gang, although Intel's document seems to claim that they tested > proper operation of pause I'd like people with non-Intel processors > to verify that it actually works. Please compile the attached test > program and run it. The output should look like this: > > > ./pt > Testing PAUSE instruction: > Register esp changed: 0xbfbff9fc -> 0xbfbff9c0 > > If you get a signal or any of the other registers change their value, > please let me know. I've tested this on a Pentium III mobile, a K6-II, > and an Athlon. The program cmopiles ok on both stable and current. > > -FW: <[EMAIL PROTECTED]>- > > Date: Tue, 21 May 2002 15:26:36 -0700 (PDT) > Sender: [EMAIL PROTECTED] > From: John Baldwin <[EMAIL PROTECTED]> > To: [EMAIL PROTECTED], [EMAIL PROTECTED] > Subject: cvs commit: src/sys/kern kern_mutex.c > > jhb 2002/05/21 15:26:36 PDT > > Modified files: > sys/kern kern_mutex.c > Log: > Add appropriate IA32 "pause" instructions to improve performanec on > Pentium 4's and newer IA32 processors. The "pause" instruction has been > verified by Intel to be a NOP on all currently existing IA32 processors > prior to the Pentium 4. > > Revision ChangesPath > 1.95 +17 -1 src/sys/kern/kern_mutex.c > > --End of forwarded message- > > -- > > John Baldwin <[EMAIL PROTECTED]> <>< http://www.FreeBSD.org/~jhb/ > "Power Users Use the Power to Serve!" - http://www.FreeBSD.org/ > To Unsubscribe: send mail to [EMAIL PROTECTED] with "unsubscribe freebsd-current" in the body of the message
Please test PAUSE on non-Intel processors
Hey gang, although Intel's document seems to claim that they tested proper operation of pause I'd like people with non-Intel processors to verify that it actually works. Please compile the attached test program and run it. The output should look like this: > ./pt Testing PAUSE instruction: Register esp changed: 0xbfbff9fc -> 0xbfbff9c0 If you get a signal or any of the other registers change their value, please let me know. I've tested this on a Pentium III mobile, a K6-II, and an Athlon. The program cmopiles ok on both stable and current. -FW: <[EMAIL PROTECTED]>- Date: Tue, 21 May 2002 15:26:36 -0700 (PDT) Sender: [EMAIL PROTECTED] From: John Baldwin <[EMAIL PROTECTED]> To: [EMAIL PROTECTED], [EMAIL PROTECTED] Subject: cvs commit: src/sys/kern kern_mutex.c jhb 2002/05/21 15:26:36 PDT Modified files: sys/kern kern_mutex.c Log: Add appropriate IA32 "pause" instructions to improve performanec on Pentium 4's and newer IA32 processors. The "pause" instruction has been verified by Intel to be a NOP on all currently existing IA32 processors prior to the Pentium 4. Revision ChangesPath 1.95 +17 -1 src/sys/kern/kern_mutex.c --End of forwarded message- -- John Baldwin <[EMAIL PROTECTED]> <>< http://www.FreeBSD.org/~jhb/ "Power Users Use the Power to Serve!" - http://www.FreeBSD.org/ /* * Simple program to see if the new IA32 PAUSE instruction works properly. * We test two different things: 1) that we don't get an illegal instruction * fault, and 2) that no registers change state. */ #include #include #define NUM_SEGREGS 6 #define NUM_REGS15 #define PUSH_REGS \ " pushf ;\n" \ " pusha ;\n" \ " push %cs ;\n" \ " push %ds ;\n" \ " push %es ;\n" \ " push %fs ;\n" \ " push %gs ;\n" \ " push %ss ;\n" const char *register_names[NUM_REGS] = { "ss", "gs", "fs", "es", "ds", "cs", "edi", "esi", "ebp", "esp", "ebx", "edx", "ecx", "eax", "eflags" }; struct register_set { register_t r_regs[NUM_REGS]; /* register_t r_ss; register_t r_gs; register_t r_fs; register_t r_es; register_t r_ds; register_t r_cs; register_t r_edi; register_t r_esi; register_t r_ebp; register_t r_isp; register_t r_ebx; register_t r_edx; register_t r_ecx; register_t r_eax; register_t r_eflags; */ }; void compare_registers(struct register_set after, struct register_set before) { int i; for (i = 0; i < NUM_SEGREGS; i++) { before.r_regs[i] &= 0x; after.r_regs[i] &= 0x; } for (i = 0; i < NUM_REGS; i++) if (before.r_regs[i] != after.r_regs[i]) printf("Register %s changed: %#x -> %#x\n", register_names[i], before.r_regs[i], after.r_regs[i]); } void test_pause(void) { __asm __volatile( " mov $10,%ecx ;\n" PUSH_REGS " pause ;\n" PUSH_REGS " call compare_registers ;\n" " addl $0x78,%esp ;\n"); } int main(int ac, char **av) { printf("Testing PAUSE instruction:\n"); test_pause(); return (0); }