[Freedreno] [PATCH v3 16/19] drm/msm: Add .commit() callback to msm_kms functions

From: Jeykumar Sankaran Called right before wait_for_commit_done() to perform kickoff for active crtcs. Changes in v3: - None Signed-off-by: Jeykumar Sankaran [seanpaul split this out of the megapatch] Signed-off-by: Sean Paul --- drivers/gpu/drm/msm/msm_atomic.c | 5 +

[Freedreno] [PATCH v3 19/19] drm/msm: Add SDM845 DPU support

From: Jeykumar Sankaran SDM845 SoC includes the Mobile Display Sub System (MDSS) which is a top level wrapper consisting of Display Processing Unit (DPU) and display peripheral modules such as Display Serial Interface (DSI) and DisplayPort (DP). MDSS functions essentially as a back-end

[Freedreno] [PATCH v3 18/19] dt-bindings: msm/disp: Add bindings for Snapdragon 845 DPU

From: Jeykumar Sankaran Adds bindings for Snapdragon 845 display processing unit Changes in v2: - Use SoC specific compatibles for mdss and dpu (Rob Herring) - Use assigned-clocks to set initial clock frequency (Rob Herring) Changes in v3 (all suggested by Rob Herring): - Rename mdss_phys to

[Freedreno] [PATCH v3 17/19] drm/msm: Add pm_suspend/resume callbacks to msm_kms

From: Jeykumar Sankaran Used by the dpu driver for custom suspend/resume. Changes in v3: - None Signed-off-by: Jeykumar Sankaran [seanpaul split this out of the megapatch] Signed-off-by: Sean Paul --- drivers/gpu/drm/msm/msm_drv.c | 10 ++ drivers/gpu/drm/msm/msm_kms.h | 3 +++ 2

[Freedreno] [PATCH v3 15/19] drm/msm: #define MAX_ in msm_drv.h

From: Jeykumar Sankaran dpu uses these elsewhere in the driver (in addition to increasing MAX_PLANES, that'll come later), so pull them out into #define. Changes in v3: - None Signed-off-by: Jeykumar Sankaran [seanpaul pulled this out of the dpu megapatch] Signed-off-by: Sean Paul ---

[Freedreno] [PATCH v3 12/19] drm/msm: Clean up dangling atomic_wq

I missed this during the atomic conversion Changes in v3: - None Signed-off-by: Sean Paul --- drivers/gpu/drm/msm/msm_drv.c | 4 drivers/gpu/drm/msm/msm_drv.h | 1 - 2 files changed, 5 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index

[Freedreno] [PATCH v3 13/19] drm/msm: #define MDP version numbers

From: Jeykumar Sankaran Useful for incoming DPU support Changes in v3: - None Signed-off-by: Jeykumar Sankaran [seanpaul split this from the dpu megapatch] Signed-off-by: Sean Paul --- drivers/gpu/drm/msm/msm_drv.c | 11 +++ 1 file changed, 7 insertions(+), 4 deletions(-) diff

[Freedreno] [PATCH v3 14/19] drm/msm: Use labels for unwinding in the error path

From: Jeykumar Sankaran This simplifies cleanup, to make sure nothing drops out in case of error. Changes in v3: - None Signed-off-by: Jeykumar Sankaran [seanpaul split out of dpu megapatch and renamed labels] Signed-off-by: Sean Paul --- drivers/gpu/drm/msm/msm_drv.c | 44

[Freedreno] [PATCH v3 11/19] drm/msm: higher values of pclk can exceed 32 bits when multiplied by a factor

From: Abhinav Kumar Make the pclk_rate u64 to accommodate higher pixel clock rates. Changes in v3: - Converted pclk_rate to u32 (Archit) - Rebase on dsi cleanup set in msm-next Cc: Sibi Sankar Cc: Archit Taneja Signed-off-by: Abhinav Kumar Signed-off-by: Sean Paul ---

[Freedreno] [PATCH v3 08/19] drm/msm: Move wait_for_vblanks into mdp complete_commit() hooks

DPU doesn't use this, so push it into the mdp drivers. Changes in v3: - None Signed-off-by: Sean Paul Signed-off-by: Rajesh Yadav --- drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 2 ++ drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 2 ++ drivers/gpu/drm/msm/msm_atomic.c | 2 -- 3 files

[Freedreno] [PATCH v3 07/19] drm/msm/dsi: set encoder mode for DRM bridge explicitly

From: Abhinav Kumar Currently, DRM bridge for DPU relies on the default video mode setting to set the encoder mode. Add an explicit call to set the encoder mode for bridges. Changes in v3: - None Reviewed-by: Archit Taneja Signed-off-by: Abhinav Kumar Signed-off-by: Sean Paul ---

[Freedreno] [PATCH v3 09/19] drm/msm/mdp5: subclass msm_mdss for mdp5

From: Rajesh Yadav SoCs having mdp5 or dpu have identical tree like device hierarchy where MDSS top level wrapper manages common power resources for all child devices. Subclass msm_mdss so that msm_mdss includes common defines and mdp5/dpu mdss derivations to include any extensions. Add mdss

[Freedreno] [PATCH v3 10/19] drm/msm: enable zpos normalization

From: Jeykumar Sankaran Enable drm core zpos normalization for planes. Changes in v3: - None Signed-off-by: Jeykumar Sankaran Reviewed-by: Sean Paul Signed-off-by: Sean Paul --- drivers/gpu/drm/msm/msm_drv.c | 3 +++ 1 file changed, 3 insertions(+) diff --git

[Freedreno] [PATCH v3 04/19] drm/msm/dsi: adjust dsi timing for dual dsi mode

From: Chandan Uddaraju For dual dsi mode, the horizontal timing needs to be divided by half since both the dsi controllers will be driving this panel. Adjust the pixel clock and DSI timing accordingly. Changes in v3: - Added Archit's R-b - Rebase on dsi cleanup set in msm-next Cc: Sibi Sankar

[Freedreno] [PATCH v3 05/19] drm/msm/dsi: Use one connector for dual DSI mode

From: Chandan Uddaraju Current DSI driver uses two connectors for dual DSI case even though we only have one panel. Fix this by implementing one connector/bridge for dual DSI use case. Use master DSI controllers to register one connector/bridge. Changes in v3: - None Reviewed-by: Archit Taneja

[Freedreno] [PATCH v3 06/19] drm/msm/dsi: initialize postdiv_lock before use for 10nm pll

From: Rajesh Yadav postdiv_lock spinlock was used before initialization for 10nm pll. It causes following spin_bug: "BUG: spinlock bad magic on CPU#0". Initialize spinlock before its usage. Changes in v3: - Added Archit's R-b Reviewed-by: Archit Taneja Signed-off-by: Rajesh Yadav

[Freedreno] [PATCH v3 00/19] drm/msm: Add support for SDM845 Display Processing Unit (DPU)

Hello! Here's v3 (well, kind of v2/v3) I revved the dt-bindings in the meantime. Refer to [1] for all of the gory details on the driver. It's been baking in linux-next for ~week now and the outstanding dt-bindings changes are sorted, so I figured it's time for another try. Note that I've removed

[Freedreno] [PATCH v3 02/19] drm: Add support for pps and compression mode command packet

From: vkorjani After enabling DSC we need to send compression mode command packet and pps data packet, for which 2 new data types are added 07h Compression Mode Data Type Write , short write, 2 parameters 0Ah PPS Long Write (word count determines number of bytes) This patch adds support to

[Freedreno] [PATCH v3 01/19] dt-bindings: msm/dsi: Add mdp transfer time to msm dsi binding

From: Jeykumar Sankaran Adds mdp transfer time to msm dsi binding Changes in v3: - Added Rob's R-b Reviewed-by: Rob Herring Signed-off-by: Jeykumar Sankaran Signed-off-by: Rajesh Yadav Signed-off-by: Sean Paul --- .../devicetree/bindings/display/msm/dsi.txt | 16 1

[Freedreno] [PATCH v3 03/19] drm: add msm compressed format modifiers

From: Jeykumar Sankaran Qualcomm Snapdragon chipsets uses compressed format to optimize BW across multiple IP's. This change adds needed modifier support in drm for a simple 4x4 tile based compressed variants of base formats. Changes in v3: - Removed duplicate entry for

Re: [Freedreno] [PATCH 01/21] dt-bindings: msm/dsi: Add mdp transfer time to msm dsi binding

On Mon, Jul 09, 2018 at 01:31:37PM -0400, Sean Paul wrote: > From: Jeykumar Sankaran > > Adds mdp transfer time to msm dsi binding > > Signed-off-by: Jeykumar Sankaran > Signed-off-by: Rajesh Yadav > Signed-off-by: Sean Paul > --- > .../devicetree/bindings/display/msm/dsi.txt | 16

[Freedreno] [PATCH v15] drm/bridge: add support for sn65dsi86 bridge driver

Add support for TI's sn65dsi86 dsi2edp bridge chip. The chip converts DSI transmitted signal to eDP signal, which is fed to the connected eDP panel. This chip can be controlled via either i2c interface or dsi interface. Currently in driver all the control registers are being accessed through i2c