Hi Jeykumar,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on robclark/msm-next]
[also build test ERROR on v4.20-rc4 next-20181130]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci
On Thu, Nov 29, 2018 at 4:23 PM Tomasz Figa wrote:
>
> On Thu, Nov 29, 2018 at 12:03 PM Robin Murphy wrote:
> >
> > On 29/11/2018 19:57, Tomasz Figa wrote:
> > > On Thu, Nov 29, 2018 at 11:40 AM Jordan Crouse
> > > wrote:
> > >>
> > >> On Thu, Nov 29, 2018 at 01:48:15PM -0500, Rob Clark wrote:
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate. Use default values if the ref
clock is not specified.
Signed-off-by: Matthias Kaehlcke
---
Changes in v3:
- use default name and rate if the ref clock is not specified
in the DT
- store vco_ref_clk_name
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Note: This change could break old out-of-tree DTS files that
use the 14nm PHY.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Douglas Anderson
---
Changes in v3:
- fixed check for EPROBE_DEFER
- added
Add 'xo_board' as ref clock for the DSI PHY, it was previously
hardcoded in the PLL 'driver' for the 28nm 8960 PHY.
Signed-off-by: Matthias Kaehlcke
---
Changes in v3:
- patch added to the series
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Note: This change could break old out-of-tree DTS files that
use the 10nm PHY
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Douglas Anderson
---
Changes in v3:
- fixed check for EPROBE_DEFER
- added note
Add 'bi_tcxo' as ref clock for the DSI PHYs, it was previously
hardcoded in the PLL 'driver' for the 10nm PHY.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Douglas Anderson
---
based on "[v4,1/3] arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file"
The MSM DSI PHY drivers currently hardcode the name and the rate of
the PHY ref clock. Get the ref clock from the device tree instead.
Note: testing of this series was limited to SDM845 and the 10nm PHY
Major changes in v3:
- keep supporting DTs without ref clock for the 28nm and the 28nm
8960
Add 'xo_board' as ref clock for the DSI PHYs, it was previously
hardcoded in the PLL 'driver' for the 28nm PHY.
Signed-off-by: Matthias Kaehlcke
Reviewed-by: Douglas Anderson
---
Changes in v3:
- added 'Reviewed-by: Douglas Anderson ' tag
Changes in v2:
- patch added to the series
---
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate. Use default values if the ref
clock is not specified.
Signed-off-by: Matthias Kaehlcke
---
Changes in v3:
- use default name and rate if the ref clock is not specified
in the DT
- store vco_ref_clk_name
Allow the PHY drivers to get the ref clock from the DT.
Signed-off-by: Matthias Kaehlcke
---
Changes in V3:
- added note that the ref clock is only required for new DTS
files/entries
Changes in v2:
- add the ref clock for all PHYs, not only the 10nm one
- updated commit message
---
On 2018-11-30 12:07, Sean Paul wrote:
On Fri, Nov 30, 2018 at 11:45:55AM -0800, Jeykumar Sankaran wrote:
On 2018-11-29 14:15, Sean Paul wrote:
> On Tue, Nov 20, 2018 at 02:04:14PM -0800, Jeykumar Sankaran wrote:
> > On 2018-11-07 07:55, Sean Paul wrote:
> > > On Tue, Nov 06, 2018 at 02:36:30PM
On Tue, Nov 27, 2018 at 10:00:50PM -0800, Doug Anderson wrote:
> Hi,
>
> On Mon, Nov 26, 2018 at 3:12 PM Matthias Kaehlcke wrote:
> > @@ -409,8 +410,9 @@ static void dsi_pll_28nm_destroy(struct msm_dsi_pll
> > *pll)
> > static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
> > {
> >
On Tue, Nov 27, 2018 at 09:56:46PM -0800, Doug Anderson wrote:
> Hi,
>
> On Mon, Nov 26, 2018 at 3:12 PM Matthias Kaehlcke wrote:
> >
> > Get the ref clock of the PHY from the device tree instead of
> > hardcoding its name and rate.
>
> In the case of the 14nm PHY I think it's OK that you break
On Tue, Nov 27, 2018 at 09:41:39PM -0800, Doug Anderson wrote:
> Hi,
>
> On Mon, Nov 26, 2018 at 3:12 PM Matthias Kaehlcke wrote:
> >
> > Allow the PHY drivers to get the ref clock from the DT.
> >
> > Signed-off-by: Matthias Kaehlcke
> > ---
> > Changes in v2:
> > - add the ref clock for all
From: Sean Paul
This patch wraps dpu_core_perf_crtc_release_bw() with modeset locks
since it digs into the state objects.
Changes in v2:
- None
Changes in v3:
- Use those nifty new DRM_MODESET_LOCK_ALL_* helpers (Daniel)
Cc: Daniel Vetter
Cc: Jeykumar Sankaran
Signed-off-by: Sean Paul
---
On Fri, Nov 30, 2018 at 11:45:55AM -0800, Jeykumar Sankaran wrote:
> On 2018-11-29 14:15, Sean Paul wrote:
> > On Tue, Nov 20, 2018 at 02:04:14PM -0800, Jeykumar Sankaran wrote:
> > > On 2018-11-07 07:55, Sean Paul wrote:
> > > > On Tue, Nov 06, 2018 at 02:36:30PM -0800, Jeykumar Sankaran wrote:
>
On Thu, Nov 29, 2018 at 08:25:20PM +0530, Vivek Gautam wrote:
> On Wed, Nov 28, 2018 at 10:07 PM Robin Murphy wrote:
> >
> > On 28/11/2018 16:24, Stephen Boyd wrote:
> > > Quoting Vivek Gautam (2018-11-27 02:11:41)
> > >> @@ -1966,6 +1970,23 @@ static const struct of_device_id
> > >>
On Fri, Nov 30, 2018 at 02:57:45PM +0530, Sandeep Panda wrote:
> Fix the AUX_CMD_SEND bit for ti,sn65dsi86 bridge chip. With wrong
> value the dpcd aux transactions with eDP panel are failing.
>
> Signed-off-by: Sandeep Panda
Pushed to -misc-fixes, thanks for the patch
Sean
> ---
>
On Fri, Nov 30, 2018 at 10:36 AM Arnd Bergmann wrote:
>
> On Fri, Nov 30, 2018 at 4:31 PM Rob Clark wrote:
> >
> > On Fri, Nov 30, 2018 at 10:12 AM Arnd Bergmann wrote:
> > >
> > > On Fri, Nov 30, 2018 at 4:02 PM Rob Clark wrote:
> > > >
> > > > Signed-off-by: Rob Clark
> > > > ---
> > > >
On Fri, Nov 30, 2018 at 4:31 PM Rob Clark wrote:
>
> On Fri, Nov 30, 2018 at 10:12 AM Arnd Bergmann wrote:
> >
> > On Fri, Nov 30, 2018 at 4:02 PM Rob Clark wrote:
> > >
> > > Signed-off-by: Rob Clark
> > > ---
> > > drivers/gpu/drm/msm/msm_drv.c | 4 +++-
> > > 1 file changed, 3
On Fri, Nov 30, 2018 at 10:12 AM Arnd Bergmann wrote:
>
> On Fri, Nov 30, 2018 at 4:02 PM Rob Clark wrote:
> >
> > Signed-off-by: Rob Clark
> > ---
> > drivers/gpu/drm/msm/msm_drv.c | 4 +++-
> > 1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/msm/msm_drv.c
On Fri, Nov 30, 2018 at 10:14 AM Arnd Bergmann wrote:
>
> On Fri, Nov 30, 2018 at 4:02 PM Rob Clark wrote:
> >
>
> > -
> > -#define MSM_INFO_FLAGS (MSM_INFO_IOVA)
> > +/* Get or set GEM buffer info. The requested value can be passed
> > + * directly in 'value', or for data larger than 64b
On Fri, Nov 30, 2018 at 4:02 PM Rob Clark wrote:
>
> -
> -#define MSM_INFO_FLAGS (MSM_INFO_IOVA)
> +/* Get or set GEM buffer info. The requested value can be passed
> + * directly in 'value', or for data larger than 64b 'value' is a
> + * pointer to userspace buffer, with 'len' specifying the
On Fri, Nov 30, 2018 at 4:02 PM Rob Clark wrote:
>
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/msm_drv.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
> index 6ebbd5010722..782cc33916d6 100644
Add UAPI to get/set GEM objects' debug name.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_drv.c | 36 ++-
include/uapi/drm/msm_drm.h| 2 ++
2 files changed, 37 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_drv.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 6ebbd5010722..782cc33916d6 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++
To lower CPU overhead, future userspace will be switching to pinning
iova and avoiding the use of relocs, and only include cmds table entries
for IB1 level cmdstream (but not IB2 or state-groups).
This leaves the kernel unsure what to dump for rd/hangrd cmdstream
dumping. So add a
Alpha enable in the pixel format will help in
selecting the blend rule. By keeping alpha enable
to true we are allowing foreground alpha to blend
with the layer. If alpha is don't care, then we
should not allow pixel alpha to be part of blend
equation.
Signed-off-by: Jayant Shekhar
---
On Fri, Nov 30, 2018 at 10:35:27AM +0100, Daniel Vetter wrote:
> > Whether the cache maintenance operation needs to actually do anything
> > or not is a function of `dev`. We can have some devices that are
> > coherent with CPU caches, and some that are not, on the same system.
>
> So the thing
On Thu, Nov 29, 2018 at 08:15:23PM -0500, Rob Clark wrote:
> As far as hiding cache ops behind iommu layer, I guess I'd been
> thinking more of just letting the drivers that want to bypass dma
> layer take things into their own hands.. tbh I think/assume/hope
> drm/msm is more the exception than
On Thu, Nov 29, 2018 at 09:24:17AM -0800, Tomasz Figa wrote:
> [CC Marek]
>
> On Thu, Nov 29, 2018 at 9:09 AM Daniel Vetter wrote:
> >
> > On Thu, Nov 29, 2018 at 5:57 PM Christoph Hellwig wrote:
> > > On Thu, Nov 29, 2018 at 05:28:07PM +0100, Daniel Vetter wrote:
> > > > Just spend a bit of
Fix the AUX_CMD_SEND bit for ti,sn65dsi86 bridge chip. With wrong
value the dpcd aux transactions with eDP panel are failing.
Signed-off-by: Sandeep Panda
---
drivers/gpu/drm/bridge/ti-sn65dsi86.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
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