[ Upstream commit 6cd5235c3135ea84b32469ea51b2aae384eda8af ]
The call to of_get_child_by_name returns a node pointer with refcount
incremented thus it must be explicitly decremented after the last
usage.
Detected by coccinelle with the following warnings:
[ Upstream commit 6cd5235c3135ea84b32469ea51b2aae384eda8af ]
The call to of_get_child_by_name returns a node pointer with refcount
incremented thus it must be explicitly decremented after the last
usage.
Detected by coccinelle with the following warnings:
[ Upstream commit 6cd5235c3135ea84b32469ea51b2aae384eda8af ]
The call to of_get_child_by_name returns a node pointer with refcount
incremented thus it must be explicitly decremented after the last
usage.
Detected by coccinelle with the following warnings:
[ Upstream commit 6cd5235c3135ea84b32469ea51b2aae384eda8af ]
The call to of_get_child_by_name returns a node pointer with refcount
incremented thus it must be explicitly decremented after the last
usage.
Detected by coccinelle with the following warnings:
On Wed, May 29, 2019 at 01:58:16PM -0600, Jeffrey Hugo wrote:
> On 5/29/2019 1:30 PM, Brian Masney wrote:
> > On Wed, May 29, 2019 at 08:41:31AM -0600, Jeffrey Hugo wrote:
> > > On Wed, May 29, 2019 at 4:28 AM Brian Masney
> > > wrote:
> > > >
> > > > On Tue, May 28, 2019 at 08:53:49PM -0600,
Add support for per-instance pagetables for 5XX targets. Create a support
buffer for preemption to hold the SMMU pagetable information for a
preempted ring, enable TTBR1 to support split pagetables and add the
necessary PM4 commands to trigger a pagetable switch at the beginning
of a user command.
Targets that support per-instance pagetable switching will have to keep
track of which pagetable belongs to each instance to be able to recover
for preemption.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_ringbuffer.h | 1 +
1 file changed, 1 insertion(+)
diff --git
Move the address space steup code out of the generic msm GPU code to
to the individual GPU targets. This allows us to do target specific
setup such as gpummu for a2xx or split pagetables and per-instance
pagetables for newer a5xx and a6xx targets. All this is at the
expense of duplicated code in
Add support for creating a auxiliary domain from the IOMMU device to
implement per-instance pagetables. Also add a helper function to
return the pagetable base address (ttbr) and asid to the caller so
that the GPU target code can set up the pagetable switch.
Signed-off-by: Jordan Crouse
---
Add support to create a GPU target specific address space for
a context. For those targets that support per-instance
pagetables they will return a new address space set up for
the instance if possible otherwise just use the global
device pagetable.
Signed-off-by: Jordan Crouse
---
Add a new domain attribute to enable split pagetable support for devices
devices that support it.
Signed-off-by: Jordan Crouse
---
include/linux/iommu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index a815cf6..a2f07cf 100644
---
Add a helper function to create a GEM address space attached to
an iommu auxiliary domain for a per-instance pagetable.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.h | 4 +++
drivers/gpu/drm/msm/msm_gem_vma.c | 53 +++
2 files changed,
This is v3 of the per-instance pagetable support. Biggest change in this
revision is moving nearly all of the split pagetable support into
io-pgtable-arm and setting up specific ops to handle the unique behavior
of the split pagetables. Now that I've spent some time with it, I like how
it turned
When we move to 64 bit addressing for a5xx and a6xx targets we will start
seeing pagefaults at larger addresses so format them appropriately in the
log message for easier debugging.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_iommu.c | 2 +-
1 file changed, 1 insertion(+), 1
A5XX and newer GPUs can be run in either 32 or 64 bit mode. The GPU
registers and the microcode use 64 bit virtual addressing in either
case but the upper 32 bits are ignored if the GPU is in 32 bit mode.
There is no performance disadvantage to remaining in 64 bit mode even
if we are only
Support auxiliary domains for arm-smmu-v2 to initialize and support multiple
pagetables for a single SMMU context bank. Since the smmu-v2 hardware
doesn't have any built in support for switching the pagetable base it is
left as an exercise to the caller to actually use the pagetable; aux
domains
Pass the index of the MMU domain in struct msm_file_private instead
of assuming gpu->id throughout the submit path. This clears the way
to change ctx->aspace to a per-instance pagetable.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.c| 2 ++
Add a new sub-format ARM_64_LPAE_SPLIT_S1 to create and set up
split pagetables (TTBR0 and TTBR1). The initialization function
sets up the correct va_size and sign extension bits and
correctly programs the TCR registers. Split pagetable formats
use their own own map/unmap wrappers to ensure that
Add an attribute to return the base address of the pagetable. This is used
by auxiliary domains from arm-smmu to return the address of the pagetable
to the leaf driver so that it can set the appropriate pagetable through
it's own means.
Signed-off-by: Jordan Crouse
---
include/linux/iommu.h |
If DOMAIN_ATTR_SPLIT_TABLES is specified for a domain pass
ARM_64_LPAE_SPLIT_S1 to io_pgtable_ops to allocate and
initialize TTBR0 and TTBR1 pagetables.
v3: Moved all the pagetable specific work into io-pgtable-arm
in previous patch
Signed-off-by: Jordan Crouse
---
drivers/iommu/arm-smmu.c |
Some client devices want to directly map the IOMMU themselves instead
of using the DMA domain. Allow those devices to opt in to direct
mapping by way of a list of compatible strings.
v3: use iommu_request_dm_for_dev() to set up a default identity domain
for a group, per Robin
Signed-off-by:
thanks, I've pushed this one to envytools tree
BR,
-R
On Wed, May 29, 2019 at 8:20 AM Jeffrey Hugo wrote:
>
> ---
> rnndb/adreno/a5xx.xml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/rnndb/adreno/a5xx.xml b/rnndb/adreno/a5xx.xml
> index ae654eeb..16203512 100644
> ---
On 5/29/2019 1:30 PM, Brian Masney wrote:
On Wed, May 29, 2019 at 08:41:31AM -0600, Jeffrey Hugo wrote:
On Wed, May 29, 2019 at 4:28 AM Brian Masney wrote:
On Tue, May 28, 2019 at 08:53:49PM -0600, Jeffrey Hugo wrote:
On Tue, May 28, 2019 at 8:46 PM Brian Masney wrote:
On Tue, May 28,
On Wed, May 29, 2019 at 08:41:31AM -0600, Jeffrey Hugo wrote:
> On Wed, May 29, 2019 at 4:28 AM Brian Masney wrote:
> >
> > On Tue, May 28, 2019 at 08:53:49PM -0600, Jeffrey Hugo wrote:
> > > On Tue, May 28, 2019 at 8:46 PM Brian Masney
> > > wrote:
> > > >
> > > > On Tue, May 28, 2019 at
The A540 is a derivative of the A530, and is found in the MSM8998 SoC.
Signed-off-by: Jeffrey Hugo
---
drivers/gpu/drm/msm/adreno/a5xx.xml.h | 28
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 21 ++
drivers/gpu/drm/msm/adreno/a5xx_power.c| 76 +-
---
rnndb/adreno/a5xx.xml | 1 +
1 file changed, 1 insertion(+)
diff --git a/rnndb/adreno/a5xx.xml b/rnndb/adreno/a5xx.xml
index ae654eeb..16203512 100644
--- a/rnndb/adreno/a5xx.xml
+++ b/rnndb/adreno/a5xx.xml
@@ -1523,6 +1523,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/
Adreno driver support for the A540 found in the MSM8998 SoC
v2:
-Removed extra RBBM write
-Corrected added RBBM writes to allow for hwcg disable
-Patch to add REG_A5XX_HLSQ_DBG_ECO_CNTL to envytools
-Regenerated a5xx header file with updated envytools
-Used REG_A5XX_HLSQ_DBG_ECO_CNTL in code
On 5/8/19 23:42, Rob Clark wrote:
> From: Georgi Djakov
>
Let's put some text in the commit message:
The interconnect API provides an interface for consumer drivers to express
their bandwidth needs in the SoC. This data is aggregated and the on-chip
interconnect hardware is configured to the
On 5/13/19 17:47, Sean Paul wrote:
> On Wed, May 08, 2019 at 01:42:12PM -0700, Rob Clark wrote:
>> From: Jayant Shekhar
>>
>> The interconnect framework is designed to provide a
>> standard kernel interface to control the settings of
>> the interconnects on a SoC.
>>
>> The interconnect API uses
On Wed, May 29, 2019 at 08:23:17AM +0200, Linus Walleij wrote:
> On Wed, May 29, 2019 at 3:17 AM Brian Masney wrote:
>
> > It's in low speed mode but its usable.
>
> How low speed is that?
I don't have a number but my test with 4.17 is to run
'cat /etc/passwd > /dev/tty1' over a serial cable.
On Wed, May 29, 2019 at 3:17 AM Brian Masney wrote:
> It's in low speed mode but its usable.
How low speed is that?
> I assume that it's related to the
> vblank events not working properly?
They are only waiting for 50 ms before timing out, I raised it
to 100ms in the -next kernel. I'm still
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