[Freedreno] [PATCH v2 3/7] drm/msm: Attach the IOMMU device during initialization

2020-01-02 Thread Sharat Masetty
From: Jordan Crouse Everywhere an IOMMU object is created by msm_gpu_create_address_space the IOMMU device is attached immediately after. Instead of carrying around the infrastructure to do the attach from the device specific code do it directly in the msm_iommu_init() function. This gets it out

[Freedreno] [PATCH v2 5/7] drm: msm: a6xx: Properly free up the iommu objects

2020-01-02 Thread Sharat Masetty
This patch calls the right function to destroy the iommu domain as well as free the associated iommu structure there by facilitating proper clean up of resources upon failure of creating an address space. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- 1 file

[Freedreno] [PATCH v2 6/7] drm/msm: rearrange the gpu_rmw() function

2020-01-02 Thread Sharat Masetty
The register read-modify-write construct is generic enough that it can be used by other subsystems as needed, create a more generic rmw() function and have the gpu_rmw() use this new function. Signed-off-by: Sharat Masetty Reviewed-by: Jordan Crouse --- drivers/gpu/drm/msm/msm_drv.c | 8

[Freedreno] [PATCH v2 4/7] drm/msm: Refactor address space initialization

2020-01-02 Thread Sharat Masetty
From: Jordan Crouse Refactor how address space initialization works. Instead of having the address space function create the MMU object (and thus require separate but equal functions for gpummu and iommu) use a single function and pass the MMU struct. Make the generic code cleaner by using

[Freedreno] [PATCH v2 7/7] drm/msm/a6xx: Add support for using system cache(LLC)

2020-01-02 Thread Sharat Masetty
The last level system cache can be partitioned to 32 different slices of which GPU has two slices preallocated. One slice is used for caching GPU buffers and the other slice is used for caching the GPU SMMU pagetables. This patch talks to the core system cache driver to acquire the slice handles,

[Freedreno] [PATCH v2 0/7] drm/msm/a6xx: System Cache Support

2020-01-02 Thread Sharat Masetty
Some hardware variants contain a system level cache or the last level cache(llc). This cache is typically a large block which is shared by multiple clients on the SOC. GPU uses the system cache to cache both the GPU data buffers(like textures) as well the SMMU pagetables. This helps with improved

[Freedreno] [PATCH v2 2/7] iommu/arm-smmu: Add domain attribute for QCOM system cache

2020-01-02 Thread Sharat Masetty
From: Vivek Gautam Add iommu domain attribute for using system cache aka last level cache on QCOM SoCs by client drivers like GPU to set right attributes for caching the hardware pagetables into the system cache. Signed-off-by: Vivek Gautam Co-developed-by: Sai Prakash Ranjan Signed-off-by:

[Freedreno] [PATCH v2 1/7] iommu/arm-smmu: Pass io_pgtable_cfg to impl specific init_context

2020-01-02 Thread Sharat Masetty
From: Jordan Crouse Pass the propposed io_pgtable_cfg to the implementation specific init_context() function to give the implementation an opportunity to to modify it before it gets passed to io-pgtable. Signed-off-by: Jordan Crouse Signed-off-by: Sai Prakash Ranjan ---