On 26/03/2021 23:48, abhin...@codeaurora.org wrote:
Hi Dmitry
On 2021-03-26 13:36, Dmitry Baryshkov wrote:
On 26/03/2021 21:05, abhin...@codeaurora.org wrote:
Hi Dmitry
On 2021-03-24 08:18, Dmitry Baryshkov wrote:
There is no reason to set clock parents manually, use device tree to
assign DS
db820c wants to use the qcom smmu path to get HUPCF set (which keeps
the GPU from wedging and then sometimes wedging the kernel after a
page fault), but it doesn't have separate pagetables support yet in
drm/msm so we can't go all the way to the TTBR1 path.
Signed-off-by: Eric Anholt
---
We've b
This enables the adreno-specific SMMU path that sets HUPCF so
(user-managed) page faults don't wedge the GPU.
Signed-off-by: Eric Anholt
---
We've been seeing a flaky test per day or so in Mesa CI where the
kernel gets wedged after an iommu fault turns into CP errors. With
this patch, the CI is
Hi Dmitry
On 2021-03-26 13:36, Dmitry Baryshkov wrote:
On 26/03/2021 21:05, abhin...@codeaurora.org wrote:
Hi Dmitry
On 2021-03-24 08:18, Dmitry Baryshkov wrote:
There is no reason to set clock parents manually, use device tree to
assign DSI/display clock parents to DSI PHY clocks. Dropping t
So that we can start using drm_dbg_*() for
drm_dp_link_train_channel_eq_delay() and
drm_dp_lttpr_link_train_channel_eq_delay().
Signed-off-by: Lyude Paul
Reviewed-by: Laurent Pinchart
---
drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 2 +-
drivers/gpu/drm/drm_dp_helper.c
This is something that we've wanted for a while now: the ability to
actually look up the respective drm_device for a given drm_dp_aux struct.
This will also allow us to transition over to using the drm_dbg_*() helpers
for debug message printing, as we'll finally have a drm_device to reference
for d
So that we can start using drm_dbg_*() in
drm_dp_link_train_clock_recovery_delay().
Signed-off-by: Lyude Paul
Reviewed-by: Laurent Pinchart
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 2 +-
drivers/gpu/drm/drm_dp_helper.c | 3 ++-
On 26/03/2021 21:05, abhin...@codeaurora.org wrote:
Hi Dmitry
On 2021-03-24 08:18, Dmitry Baryshkov wrote:
There is no reason to set clock parents manually, use device tree to
assign DSI/display clock parents to DSI PHY clocks. Dropping this manual
setup allows us to drop repeating code and to
Hi Dmitry
On 2021-03-24 08:18, Dmitry Baryshkov wrote:
There is no reason to set clock parents manually, use device tree to
assign DSI/display clock parents to DSI PHY clocks. Dropping this
manual
setup allows us to drop repeating code and to move registration of hw
clock providers to generic
On 2021-03-24 08:18, Dmitry Baryshkov wrote:
msm_dsi_pll_set_usecase() function is not used outside of individual
DSI
PHY drivers, so drop it in favour of calling the the respective
set_usecase functions directly.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/d
On 2021-03-24 08:18, Dmitry Baryshkov wrote:
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 3 +++
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 6 --
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 6 --
driv
On 2021-03-24 08:18, Dmitry Baryshkov wrote:
With the current upstream driver the msm_dsi_phy_type enum does not
make
much sense: all DSI PHYs are probed using the dt bindings, the phy type
is not passed between drivers. Use quirks in phy individual PHY drivers
to differentiate minor harware dif
On 2021-03-24 08:18, Dmitry Baryshkov wrote:
DSI PHY init callback would either map dsi_phy_regulator or
dsi_phy_lane
depending on the PHY type. Replace those callbacks with configuration
options governing mapping those regions.
Signed-off-by: Dmitry Baryshkov
This is a nice cleanup which wil
On 2021-03-24 08:18, Dmitry Baryshkov wrote:
Move all PLL-related callbacks into struct msm_dsi_phy_cfg. This limits
the amount of data in the struct msm_dsi_pll.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dsi/dsi.h | 6 --
drivers/gp
On 2021-03-24 08:18, Dmitry Baryshkov wrote:
Add devm_clk_hw_register_divider() - devres version of
clk_hw_register_divider().
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
include/linux/clk-provider.h | 17 +
1 file changed, 17 insertions(+)
diff --git a/i
On 2021-03-24 08:18, Dmitry Baryshkov wrote:
Add devm_clk_hw_register_mux() - devres-managed version of
clk_hw_register_mux().
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/clk/clk-mux.c| 35 +++
include/linux/clk-provider.h |
On 2021-03-24 08:18, Dmitry Baryshkov wrote:
The only PLL using multiple enable sequences is the 28nm PLL, which
just
does the single step in the loop. Push that support back into the PLL
code.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dsi/phy/dsi_p
Hi Dmitry
On 2021-03-24 08:18, Dmitry Baryshkov wrote:
From: Daniel Palmer
Add a devm helper for clk_hw_register_fixed_factor() so that drivers
that internally
register fixed factor clocks for things like dividers don't need to
manually unregister
them on remove or if probe fails.
Signed-off-
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