On 01/04/2021 01:47, Rob Clark wrote:
On Wed, Mar 31, 2021 at 9:03 AM Dmitry Baryshkov
wrote:
On 31/03/2021 14:27, Kalyan Thota wrote:
WARN_ON was introduced by the below commit to catch runtime resumes
that are getting triggered before icc path was set.
"drm/msm/disp/dpu1: icc path needs
Currently DPU driver scales bandwidth and core clock for sc7180 only,
while the rest of chips get static bandwidth votes. Make all chipsets
scale bandwidth and clock per composition requirements like sc7180 does.
Drop old voting path completely.
Tested on RB3 (SDM845) and RB5 (SM8250).
Fill clk_inefficiency_factor, bw_inefficiency_factor and
min_prefill_lines in hw catalog data for sdm845 and sm8[12]50.
Efficiency factors are blindly copied from sc7180 data, while
min_prefill_lines is based on downstream display driver.
Signed-off-by: Dmitry Baryshkov
---
From: Rob Clark
The last patch lost the breakdown of active vs inactive GEM objects in
$debugfs/gem. But we can add some better stats to summarize not just
active vs inactive, but also purgable/purged to make up for that.
Signed-off-by: Rob Clark
Tested-by: Douglas Anderson
Reviewed-by:
From: Rob Clark
In normal cases the gem obj lock is acquired first before mm_lock. The
exception is iterating the various object lists. In the shrinker path,
deadlock is avoided by using msm_gem_trylock() and skipping over objects
that cannot be locked. But for debugfs the straightforward
From: Rob Clark
When the system is under heavy memory pressure, we can end up with lots
of concurrent calls into the shrinker. Keeping a running tab on what we
can shrink avoids grabbing a lock in shrinker->count(), and avoids
shrinker->scan() getting called when not profitable.
Also, we can
From: Rob Clark
Unused since commit c951a9b284b9 ("drm/msm: Remove msm_gem_free_work")
Signed-off-by: Rob Clark
Tested-by: Douglas Anderson
---
drivers/gpu/drm/msm/msm_gem.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gem.h b/drivers/gpu/drm/msm/msm_gem.h
From: Rob Clark
I've been spending some time looking into how things behave under high
memory pressure. The first patch is a random cleanup I noticed along
the way. The second improves the situation significantly when we are
getting shrinker called from many threads in parallel. And the last
On Wed, Mar 31, 2021 at 4:39 PM Doug Anderson wrote:
>
> Hi,
>
> On Wed, Mar 31, 2021 at 4:23 PM Rob Clark wrote:
> >
> > On Wed, Mar 31, 2021 at 3:44 PM Doug Anderson wrote:
> > >
> > > Hi,
> > >
> > > On Wed, Mar 31, 2021 at 3:14 PM Rob Clark wrote:
> > > >
> > > > @@ -818,11 +820,19 @@
Hi,
On Wed, Mar 31, 2021 at 3:14 PM Rob Clark wrote:
>
> From: Rob Clark
>
> Unused since c951a9b284b907604759628d273901064c60d09f
Not terribly important, but checkpatch always yells at me when I don't
reference commits by saying:
commit c951a9b284b9 ("drm/msm: Remove msm_gem_free_work")
>
Hi,
On Wed, Mar 31, 2021 at 3:14 PM Rob Clark wrote:
>
> From: Rob Clark
>
> I've been spending some time looking into how things behave under high
> memory pressure. The first patch is a random cleanup I noticed along
> the way. The second improves the situation significantly when we are
>
Hi,
On Wed, Mar 31, 2021 at 4:23 PM Rob Clark wrote:
>
> On Wed, Mar 31, 2021 at 3:44 PM Doug Anderson wrote:
> >
> > Hi,
> >
> > On Wed, Mar 31, 2021 at 3:14 PM Rob Clark wrote:
> > >
> > > @@ -818,11 +820,19 @@ static void update_inactive(struct msm_gem_object
> > > *msm_obj)
> > >
Hi,
On Wed, Mar 31, 2021 at 3:14 PM Rob Clark wrote:
>
> From: Rob Clark
>
> The last patch lost the breakdown of active vs inactive GEM objects in
> $debugfs/gem. But we can add some better stats to summarize not just
> active vs inactive, but also purgable/purged to make up for that.
>
>
On Wed, Mar 31, 2021 at 4:13 PM Doug Anderson wrote:
>
> Hi,
>
> On Wed, Mar 31, 2021 at 3:14 PM Rob Clark wrote:
> >
> > @@ -111,23 +111,15 @@ static const struct file_operations msm_gpu_fops = {
> > static int msm_gem_show(struct drm_device *dev, struct seq_file *m)
> > {
> > struct
On Wed, Mar 31, 2021 at 3:44 PM Doug Anderson wrote:
>
> Hi,
>
> On Wed, Mar 31, 2021 at 3:14 PM Rob Clark wrote:
> >
> > @@ -818,11 +820,19 @@ static void update_inactive(struct msm_gem_object
> > *msm_obj)
> > mutex_lock(>mm_lock);
> > WARN_ON(msm_obj->active_count != 0);
> >
Hi,
On Wed, Mar 31, 2021 at 3:14 PM Rob Clark wrote:
>
> @@ -111,23 +111,15 @@ static const struct file_operations msm_gpu_fops = {
> static int msm_gem_show(struct drm_device *dev, struct seq_file *m)
> {
> struct msm_drm_private *priv = dev->dev_private;
> - struct msm_gpu *gpu
Hi,
On Wed, Mar 31, 2021 at 3:14 PM Rob Clark wrote:
>
> @@ -818,11 +820,19 @@ static void update_inactive(struct msm_gem_object
> *msm_obj)
> mutex_lock(>mm_lock);
> WARN_ON(msm_obj->active_count != 0);
>
> + if (msm_obj->dontneed)
> +
On Wed, Mar 31, 2021 at 9:03 AM Dmitry Baryshkov
wrote:
>
> On 31/03/2021 14:27, Kalyan Thota wrote:
> > WARN_ON was introduced by the below commit to catch runtime resumes
> > that are getting triggered before icc path was set.
> >
> > "drm/msm/disp/dpu1: icc path needs to be set before dpu
On Thu, Mar 25, 2021 at 7:37 AM Jordan Crouse wrote:
>
> jcrouse at codeaurora.org ha started bouncing. Redirect to a
nit: s/ha/has/
> more permanent address.
>
> Signed-off-by: Jordan Crouse
Acked-by: Rob Clark
> ---
>
> .mailmap | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git
From: Rob Clark
The last patch lost the breakdown of active vs inactive GEM objects in
$debugfs/gem. But we can add some better stats to summarize not just
active vs inactive, but also purgable/purged to make up for that.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_fb.c | 3 ++-
From: Rob Clark
When the system is under heavy memory pressure, we can end up with lots
of concurrent calls into the shrinker. Keeping a running tab on what we
can shrink avoids grabbing a lock in shrinker->count(), and avoids
shrinker->scan() getting called when not profitable.
Also, we can
From: Rob Clark
I've been spending some time looking into how things behave under high
memory pressure. The first patch is a random cleanup I noticed along
the way. The second improves the situation significantly when we are
getting shrinker called from many threads in parallel. And the last
From: Rob Clark
In normal cases the gem obj lock is acquired first before mm_lock. The
exception is iterating the various object lists. In the shrinker path,
deadlock is avoided by using msm_gem_trylock() and skipping over objects
that cannot be locked. But for debugfs the straightforward
From: Rob Clark
Unused since c951a9b284b907604759628d273901064c60d09f
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gem.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gem.h b/drivers/gpu/drm/msm/msm_gem.h
index b3a0a880cbab..7a9107cf1818 100644
---
On 2021-03-31 03:57, Dmitry Baryshkov wrote:
The src_truthtable config is not used for some of phys, which use other
means of configuring the master/slave usecases. Inline this function
with the goal of removing src_pll_id argument in the next commit.
Signed-off-by: Dmitry Baryshkov
Tested-by:
On 2021-03-31 03:57, Dmitry Baryshkov wrote:
Phy driver already knows the source PLL id basing on the set usecase
and
the current PLL id. Stop passing it to the phy_enable call. As a
reminder, dsi manager will always use DSI 0 as a clock master in a
slave
mode, so PLL 0 is always a
On 3/31/21 7:34 AM, kalya...@codeaurora.org wrote:
> On 2021-03-31 00:04, Steev Klimaszewski wrote:
>> On 3/22/21 4:17 AM, Kalyan Thota wrote:
>>> From: Kalyan Thota
>>>
>>> DPU runtime resume will request for a min vote on the AXI bus as
>>> it is a necessary step before turning ON the AXI
On 2021-03-31 03:57, Dmitry Baryshkov wrote:
Make save_state/restore callbacks accept struct msm_dsi_phy rather than
struct msm_dsi_pll. This moves them to struct msm_dsi_phy_ops, allowing
us to drop struct msm_dsi_pll_ops.
Signed-off-by: Dmitry Baryshkov
Tested-by: Stephen Boyd # on sc7180
On 2021-03-16 15:38, Christoph Hellwig wrote:
[...]
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index f1e38526d5bd40..996dfdf9d375dd 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++
On 2021-03-31 16:32, Will Deacon wrote:
On Wed, Mar 31, 2021 at 02:09:37PM +0100, Robin Murphy wrote:
On 2021-03-31 12:49, Will Deacon wrote:
On Tue, Mar 30, 2021 at 05:28:19PM +0100, Robin Murphy wrote:
On 2021-03-30 14:58, Will Deacon wrote:
On Tue, Mar 30, 2021 at 02:19:38PM +0100, Robin
On 31/03/2021 14:27, Kalyan Thota wrote:
WARN_ON was introduced by the below commit to catch runtime resumes
that are getting triggered before icc path was set.
"drm/msm/disp/dpu1: icc path needs to be set before dpu runtime resume"
For the targets where the bw scaling is not enabled, this
Hi,
On Wed, Mar 31, 2021 at 4:27 AM Kalyan Thota wrote:
>
> @@ -294,6 +294,9 @@ static int dpu_kms_parse_data_bus_icc_path(struct dpu_kms
> *dpu_kms)
> struct icc_path *path1;
> struct drm_device *dev = dpu_kms->dev;
>
> + if (!dpu_supports_bw_scaling(dev))
> +
On Wed, Mar 31, 2021 at 02:09:37PM +0100, Robin Murphy wrote:
> On 2021-03-31 12:49, Will Deacon wrote:
> > On Tue, Mar 30, 2021 at 05:28:19PM +0100, Robin Murphy wrote:
> > > On 2021-03-30 14:58, Will Deacon wrote:
> > > > On Tue, Mar 30, 2021 at 02:19:38PM +0100, Robin Murphy wrote:
> > > > > On
fixing Jordan's email so he actually sees this
On Wed, Mar 31, 2021 at 7:02 AM Dmitry Baryshkov
wrote:
>
> I suppose the microcode version check for a650 is incorrect. It checks
> for the version 1.95, while the firmware released have major version of 0:
> 0.91 (vulnerable), 0.99 (fixing the
I suppose the microcode version check for a650 is incorrect. It checks
for the version 1.95, while the firmware released have major version of 0:
0.91 (vulnerable), 0.99 (fixing the issue).
Lower version requirements to accept firmware 0.99.
Fixes: 8490f02a3ca4 ("drm/msm: a6xx: Make sure the SQE
Hello,
On 10/02/2021 03:52, Jordan Crouse wrote:
Most a6xx targets have security issues that were fixed with new versions
of the microcode(s). Make sure that we are booting with a safe version of
the microcode for the target and print a message and error if not.
v2: Add more informative error
Fixes the following sparse warnings:
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c:189:9:expected void [noderef]
__iomem *addr
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c:189:9:got void *
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c:190:9: warning: incorrect type in
argument 2 (different
On 2021-03-31 12:49, Will Deacon wrote:
On Tue, Mar 30, 2021 at 05:28:19PM +0100, Robin Murphy wrote:
On 2021-03-30 14:58, Will Deacon wrote:
On Tue, Mar 30, 2021 at 02:19:38PM +0100, Robin Murphy wrote:
On 2021-03-30 14:11, Will Deacon wrote:
On Tue, Mar 16, 2021 at 04:38:22PM +0100,
On 2021-03-31 00:04, Steev Klimaszewski wrote:
On 3/22/21 4:17 AM, Kalyan Thota wrote:
From: Kalyan Thota
DPU runtime resume will request for a min vote on the AXI bus as
it is a necessary step before turning ON the AXI clock.
The change does below
1) Move the icc path set before requesting
On Tue, Mar 30, 2021 at 05:28:19PM +0100, Robin Murphy wrote:
> On 2021-03-30 14:58, Will Deacon wrote:
> > On Tue, Mar 30, 2021 at 02:19:38PM +0100, Robin Murphy wrote:
> > > On 2021-03-30 14:11, Will Deacon wrote:
> > > > On Tue, Mar 16, 2021 at 04:38:22PM +0100, Christoph Hellwig wrote:
> > > >
WARN_ON was introduced by the below commit to catch runtime resumes
that are getting triggered before icc path was set.
"drm/msm/disp/dpu1: icc path needs to be set before dpu runtime resume"
For the targets where the bw scaling is not enabled, this WARN_ON is
a false alarm. Fix the WARN
Phy driver already knows the source PLL id basing on the set usecase and
the current PLL id. Stop passing it to the phy_enable call. As a
reminder, dsi manager will always use DSI 0 as a clock master in a slave
mode, so PLL 0 is always a clocksource for DSI 0 and it is always a
clocksource for DSI
Drop the struct msm_dsi_pll abstraction, by including vco's clk_hw
directly into struct msm_dsi_phy.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Tested-by: Stephen Boyd # on sc7180 lazor
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/Kconfig | 8 --
Drop duplicate fields pdev and id from dsi_pll_Nnm instances. Reuse
those fields from the provided msm_dsi_phy.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Tested-by: Stephen Boyd # on sc7180 lazor
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c| 72 +--
The 7nm, 10nm and 14nm drivers would store interim data used during
VCO/PLL rate setting in the global dsi_pll_Nnm structure. Move this data
structures to the onstack storage. While we are at it, drop
unused/static 'config' data, unused config fields, etc.
Signed-off-by: Dmitry Baryshkov
Make save_state/restore callbacks accept struct msm_dsi_phy rather than
struct msm_dsi_pll. This moves them to struct msm_dsi_phy_ops, allowing
us to drop struct msm_dsi_pll_ops.
Signed-off-by: Dmitry Baryshkov
Tested-by: Stephen Boyd # on sc7180 lazor
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
Replace PLL accessor functions (pll_read/pll_write*) with the DSI PHY
accessors, reducing duplication.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Tested-by: Stephen Boyd # on sc7180 lazor
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 24 +--
The src_truthtable config is not used for some of phys, which use other
means of configuring the master/slave usecases. Inline this function
with the goal of removing src_pll_id argument in the next commit.
Signed-off-by: Dmitry Baryshkov
Tested-by: Stephen Boyd # on sc7180 lazor
---
All PHY drivers would map dsi_pll area. Some PHY drivers would also
map dsi_phy area again (a leftover from old PHY/PLL separation). Move
all ioremaps to the common dsi_phy driver code and drop individual
ioremapped areas from PHY drivers.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav
Instead of setting the variable and then using it just in the one place,
determine vco_delay directly at the PLL configuration time.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Tested-by: Stephen Boyd # on sc7180 lazor
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 12
Move all PLL-related callbacks into struct msm_dsi_phy_cfg. This limits
the amount of data in the struct msm_dsi_pll.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Tested-by: Stephen Boyd # on sc7180 lazor
---
drivers/gpu/drm/msm/dsi/dsi.h | 6 --
Use devm_of_clk_add_hw_provider() to register provided clocks. This
allows dropping the remove function alltogether.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Tested-by: Stephen Boyd # on sc7180 lazor
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 22 +-
1
Morph msm_dsi_pll_save/restore_state() into msm_dsi_phy_save/restore_state(),
thus removing last bits of knowledge about msm_dsi_pll from dsi_manager.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Tested-by: Stephen Boyd # on sc7180 lazor
---
drivers/gpu/drm/msm/dsi/dsi.h
All MSM DSI PHYs provide two clocks: byte and pixel ones.
Register/unregister provided clocks from the generic place, removing
boilerplate code from all MSM DSI PHY drivers.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Tested-by: Stephen Boyd # on sc7180 lazor
---
With the current upstream driver the msm_dsi_phy_type enum does not make
much sense: all DSI PHYs are probed using the dt bindings, the phy type
is not passed between drivers. Use quirks in phy individual PHY drivers
to differentiate minor harware differences and drop the enum.
Signed-off-by:
msm_dsi_pll_set_usecase() function is not used outside of individual DSI
PHY drivers, so drop it in favour of calling the the respective
set_usecase functions directly.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Tested-by: Stephen Boyd # on sc7180 lazor
---
Use devres-enabled version of clock registration functions. This lets us
remove dsi_pll destroy callbacks completely.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Tested-by: Stephen Boyd # on sc7180 lazor
---
drivers/gpu/drm/msm/dsi/dsi.h | 4 -
DSI PHY init callback would either map dsi_phy_regulator or dsi_phy_lane
depending on the PHY type. Replace those callbacks with configuration
options governing mapping those regions.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Tested-by: Stephen Boyd # on sc7180 lazor
---
These drivers do not use vco_delay variable, so drop it from all of
them.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Tested-by: Stephen Boyd # on sc7180 lazor
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 3 ---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 4
10nm and 7nm already do not use these helpers, as they handle setting
slave DSI clocks after enabling VCO. Modify the rest of PHY drivers to
remove unnecessary indirection and drop enable_seq/disable_seq PLL
callbacks.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Tested-by:
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Tested-by: Stephen Boyd # on sc7180 lazor
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 3 +++
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 6 --
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 6 --
Add devm_clk_hw_register_mux() - devres-managed version of
clk_hw_register_mux().
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Acked-by: Stephen Boyd
---
drivers/clk/clk-mux.c| 35 +++
include/linux/clk-provider.h | 13 +
2
The only PLL using multiple enable sequences is the 28nm PLL, which just
does the single step in the loop. Push that support back into the PLL
code.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Tested-by: Stephen Boyd # on sc7180 lazor
---
Add devm_clk_hw_register_divider() - devres version of
clk_hw_register_divider().
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Acked-by: Stephen Boyd
---
include/linux/clk-provider.h | 17 +
1 file changed, 17 insertions(+)
diff --git
Restructure MSM DSI PHY drivers. What started as an attempt to grok the
overcomplicated PHY drivers, has lead up to the idea of merging PHY and
PLL code, reducing abstractions, code duplication, dropping dead code,
etc.
The patches were mainly tested on RB5 (sm8250, 7nm) and DB410c (apq8016,
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