On Wed, 2 Nov 2022 21:44:10 +0300, Dmitry Baryshkov wrote:
> Change order of SMMU clocks to match the schema.
>
>
Applied, thanks!
[01/11] arm64: dts: qcom: msm8996: change order of SMMU clocks on this platform
commit: d6e636787d462c047a424dd442b68a249edde2a7
Best regards,
--
Bjorn
On Mon, Nov 7, 2022 at 4:22 PM Jessica Zhang wrote:
>
>
>
> On 11/7/2022 2:09 PM, Rob Clark wrote:
> > On Mon, Nov 7, 2022 at 1:32 PM Jessica Zhang
> > wrote:
> >>
> >>
> >>
> >> On 11/7/2022 11:37 AM, Ville Syrjälä wrote:
> >>> On Fri, Oct 28, 2022 at 03:59:49PM -0700, Jessica Zhang wrote:
>
On 11/7/2022 2:09 PM, Rob Clark wrote:
On Mon, Nov 7, 2022 at 1:32 PM Jessica Zhang wrote:
On 11/7/2022 11:37 AM, Ville Syrjälä wrote:
On Fri, Oct 28, 2022 at 03:59:49PM -0700, Jessica Zhang wrote:
Introduce and add support for COLOR_FILL and COLOR_FILL_FORMAT
properties. When the
Each compatible has a different set of clocks which are associated with it.
Add in the list of clocks for each compatible.
Cc: Rob Clark
Cc: Abhinav Kumar
Cc: Dmitry Baryshkov
Cc: Sean Paul
Cc: David Airlie
Cc: Daniel Vetter
Cc: Rob Herring
Cc: Krzysztof Kozlowski
Cc:
When converting from .txt to .yaml dt-binding descriptions we appear to
have missed some of the previous detail on the number and names of
permissible clocks.
Fixes: 4dbe55c97741 ("dt-bindings: msm: dsi: add yaml schemas for DSI bindings")
Reviewed-by: Dmitry Baryshkov
Cc: Rob Clark
Cc: Abhinav
Sort the order of the compatible strings alphanumerically.
Cc: Rob Clark
Cc: Abhinav Kumar
Cc: Dmitry Baryshkov
Cc: Sean Paul
Cc: David Airlie
Cc: Daniel Vetter
Cc: Rob Herring
Cc: Krzysztof Kozlowski
Cc: linux-arm-...@vger.kernel.org
Cc: dri-de...@lists.freedesktop.org
Cc:
Currently we do not differentiate between the various users of the
qcom,mdss-dsi-ctrl. The driver is flexible enough to operate from one
compatible string but, the hardware does have some significant differences
in the number of clocks.
To facilitate documenting the clocks add the following
There's a typo in describing the core clock as an 'escape' clock. The
accurate description is 'core'.
Fixes: 4dbe55c97741 ("dt-bindings: msm: dsi: add yaml schemas for DSI bindings")
Cc: Rob Clark
Cc: Abhinav Kumar
Cc: Dmitry Baryshkov
Cc: Sean Paul
Cc: David Airlie
Cc: Daniel Vetter
Cc:
When converting from .txt to .yaml we didn't include descriptions for the
existing regulator supplies.
- vdd
- vdda
- vddio
Add those descriptions into the yaml now as they were prior to the
conversion. Mark the supplies as required as was previously the case in the
.txt implementation.
power-domain is required for the sc7180 dispcc GDSC but not every qcom SoC
has a similar dependency for example the aqp8064.
Most Qcom SoC's using mdss-dsi-ctrl seem to have the ability to
power-collapse the MDP without collapsing DSI.
For example the qcom vendor kernel commit for apq8084,
The existing msm8916.dtsi does not depend on nor require operating points.
Fixes: 4dbe55c97741 ("dt-bindings: msm: dsi: add yaml schemas for DSI bindings")
Reviewed-by: Dmitry Baryshkov
Acked-by: Krzysztof Kozlowski
Cc: Rob Clark
Cc: Abhinav Kumar
Cc: Dmitry Baryshkov
Cc: Sean Paul
Cc:
On Mon, Nov 07, 2022 at 09:37:08PM +0200, Ville Syrjälä wrote:
> On Fri, Oct 28, 2022 at 03:59:49PM -0700, Jessica Zhang wrote:
> > Introduce and add support for COLOR_FILL and COLOR_FILL_FORMAT
> > properties. When the color fill value is set, and the framebuffer is set
> > to NULL, memory fetch
On 07/11/2022 07:27, Abhinav Kumar wrote:
On 9/22/2022 4:30 AM, Dmitry Baryshkov wrote:
SM8350 and SM8450 use 5nm DSI PHYs, which share register definitions
with 7nm DSI PHYs. Rather than duplicating the driver, handle 5nm
variants inside the common 5+7nm driver.
I do realize that there is
On Mon, Nov 7, 2022 at 1:32 PM Jessica Zhang wrote:
>
>
>
> On 11/7/2022 11:37 AM, Ville Syrjälä wrote:
> > On Fri, Oct 28, 2022 at 03:59:49PM -0700, Jessica Zhang wrote:
> >> Introduce and add support for COLOR_FILL and COLOR_FILL_FORMAT
> >> properties. When the color fill value is set, and the
On 11/7/2022 11:37 AM, Ville Syrjälä wrote:
On Fri, Oct 28, 2022 at 03:59:49PM -0700, Jessica Zhang wrote:
Introduce and add support for COLOR_FILL and COLOR_FILL_FORMAT
properties. When the color fill value is set, and the framebuffer is set
to NULL, memory fetch will be disabled.
November 3, 2022 at 8:22 PM, "Sean Anderson" mailto:sean.ander...@seco.com?to=%22Sean%20Anderson%22%20%3Csean.anderson%40seco.com%3E
> wrote:
>
> Every user of this function either uses component_compare_of or
> something equivalent. Most of them immediately put the device node as
> well.
On Fri, Oct 28, 2022 at 03:59:49PM -0700, Jessica Zhang wrote:
> Introduce and add support for COLOR_FILL and COLOR_FILL_FORMAT
> properties. When the color fill value is set, and the framebuffer is set
> to NULL, memory fetch will be disabled.
Thinking a bit more universally I wonder if there
From: Ville Syrjälä
struct drm_display_mode embeds a list head, so overwriting
the full struct with another one will corrupt the list
(if the destination mode is on a list). Use drm_mode_copy()
instead which explicitly preserves the list head of
the destination mode.
Even if we know the
From: Ville Syrjälä
Initialize on-stack modes with drm_mode_init() to guarantee
no stack garbage in the list head, or that we aren't copying
over another mode's list head.
Based on the following cocci script, with manual fixups:
@decl@
identifier M;
expression E;
@@
- struct drm_display_mode M
On 10/5/2022 2:36 PM, Akhil P Oommen wrote:
Some clients like adreno gpu driver would like to ensure that its gdsc
is collapsed at hardware during a gpu reset sequence. This is because it
has a votable gdsc which could be ON due to a vote from another subsystem
like tz, hyp etc or due to an
On 07/11/2022 12:36, Krzysztof Kozlowski wrote:
On 07/11/2022 11:46, Konrad Dybcio wrote:
On 06/11/2022 05:30, Bjorn Andersson wrote:
On Fri, Nov 04, 2022 at 04:13:56PM +0300, Dmitry Baryshkov wrote:
Enable MDSS/DPU/DSI0 on SM8450-HDK device. Note, there is no panel
configuration (yet).
On 07/11/2022 11:46, Konrad Dybcio wrote:
>
>
> On 06/11/2022 05:30, Bjorn Andersson wrote:
>> On Fri, Nov 04, 2022 at 04:13:56PM +0300, Dmitry Baryshkov wrote:
>>> Enable MDSS/DPU/DSI0 on SM8450-HDK device. Note, there is no panel
>>> configuration (yet).
>>>
>>> Signed-off-by: Dmitry Baryshkov
On 06/11/2022 05:30, Bjorn Andersson wrote:
On Fri, Nov 04, 2022 at 04:13:56PM +0300, Dmitry Baryshkov wrote:
Enable MDSS/DPU/DSI0 on SM8450-HDK device. Note, there is no panel
configuration (yet).
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 18
From: Konrad Dybcio
SDM845 only has INTF0-3 and has no business caring about the INTF4 irq.
Suggested-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 -
1 file changed, 1 deletion(-)
diff --git
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