This is a series of changes for DSI to enable support for DSC v1.2.
This includes:
1) Dividing the pclk_rate by the compression ratio when DSC is enabled
2) Fixing the word count calculation for DSC
3) Setting the DATA_COMPRESS bit when DSC is enabled
With these changes (and the dependency
Add a dpu_hw_intf op to enable data compression.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 4
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 7 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 2 ++
3 files changed, 13
Add data_compress feature to DPU HW catalog.
In DPU 7.x and later, there is a DATA_COMPRESS register that must be set
within the DPU INTF block for DSC to work.
As core_rev (and related macros) was removed from the dpu_kms struct, the
most straightforward way to indicate the presence of this
Currently, word count is calculated using slice_count. This is incorrect
as downstream uses slice per packet, which is different from
slice_count.
Slice count represents the number of soft slices per interface, and its
value will not always match that of slice per packet. For example, it is
Divide the pclk rate by the compression ratio when DSC is enabled
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
On 5/2/2023 4:58 PM, Dmitry Baryshkov wrote:
On 03/05/2023 02:57, Abhinav Kumar wrote:
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
There is little sense to get intf index just to call dpu_rm_get_intf()
on it. Move dpu_rm_get_intf() call to dpu_encoder_get_intf() function.
On 01/05/2023 02:57, Dmitry Baryshkov wrote:
The atomic_mode_set() callback only sets the phys_enc's IRQ data. As the
INTF and WB are statically allocated to each encoder/phys_enc, drop the
atomic_mode_set callback and set the IRQs during encoder init.
Signed-off-by: Dmitry Baryshkov
Please
On 03/05/2023 02:58, Abhinav Kumar wrote:
On 5/2/2023 4:54 PM, Dmitry Baryshkov wrote:
On 03/05/2023 02:51, Abhinav Kumar wrote:
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
The function dpu_encoder_get_wb() returns controller_id if the
corresponding WB is present in the catalog. We can
On 03/05/2023 02:57, Abhinav Kumar wrote:
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
There is little sense to get intf index just to call dpu_rm_get_intf()
on it. Move dpu_rm_get_intf() call to dpu_encoder_get_intf() function.
Signed-off-by: Dmitry Baryshkov
---
On 5/2/2023 4:54 PM, Dmitry Baryshkov wrote:
On 03/05/2023 02:51, Abhinav Kumar wrote:
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
The function dpu_encoder_get_wb() returns controller_id if the
corresponding WB is present in the catalog. We can inline this function
and rely on
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
There is little sense to get intf index just to call dpu_rm_get_intf()
on it. Move dpu_rm_get_intf() call to dpu_encoder_get_intf() function.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 20
On 03/05/2023 02:51, Abhinav Kumar wrote:
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
The function dpu_encoder_get_wb() returns controller_id if the
corresponding WB is present in the catalog. We can inline this function
and rely on dpu_rm_get_wb() returning NULL for indices for which the
On 03/05/2023 02:19, Abhinav Kumar wrote:
On 5/2/2023 4:15 PM, Dmitry Baryshkov wrote:
On Wed, 3 May 2023 at 02:04, Abhinav Kumar
wrote:
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
Remove intf_idx and wb_idx fields from struct dpu_encoder_phys and
struct dpu_enc_phys_init_params. Set
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
The function dpu_encoder_get_wb() returns controller_id if the
corresponding WB is present in the catalog. We can inline this function
and rely on dpu_rm_get_wb() returning NULL for indices for which the
WB is not present on the device.
On 5/2/2023 2:38 PM, Dmitry Baryshkov wrote:
On 03/05/2023 00:03, Kuogee Hsieh wrote:
Add support for DSC 1.2 by providing the necessary hooks to program
the DPU DSC 1.2 encoder.
Changes in v3:
-- fixed kernel test rebot report that "__iomem *off" is declared but
not
used at
On 5/2/2023 4:15 PM, Dmitry Baryshkov wrote:
On Wed, 3 May 2023 at 02:04, Abhinav Kumar wrote:
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
Remove intf_idx and wb_idx fields from struct dpu_encoder_phys and
struct dpu_enc_phys_init_params. Set the hw_intf and hw_wb directly and
use
On Wed, 3 May 2023 at 02:04, Abhinav Kumar wrote:
>
>
>
> On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
> > Remove intf_idx and wb_idx fields from struct dpu_encoder_phys and
> > struct dpu_enc_phys_init_params. Set the hw_intf and hw_wb directly and
> > use them to get the instance index.
> >
>
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
Remove intf_idx and wb_idx fields from struct dpu_encoder_phys and
struct dpu_enc_phys_init_params. Set the hw_intf and hw_wb directly and
use them to get the instance index.
Signed-off-by: Dmitry Baryshkov
---
From whatever I can see, this
On 03/05/2023 00:02, Kuogee Hsieh wrote:
At legacy chipsets, it required DPU_PINGPONG_DSC bit be set to indicate
pingpong ops functions are required to complete DSC data path setup if
this chipset has DSC hardware block presented. This patch add
DPU_PINGPONG_DSC bit to both PP_BLK and PP_BLK_TE
On 03/05/2023 00:03, Kuogee Hsieh wrote:
From: Abhinav Kumar
Add DSC 1.2 hardware blocks to the catalog with necessary sub-block and
feature flag information. Each display compression engine (DCE) contains
dual hard slice DSC encoders so both share same base address but with
its own different
On 03/05/2023 00:03, Kuogee Hsieh wrote:
Add support for DSC 1.2 by providing the necessary hooks to program
the DPU DSC 1.2 encoder.
Changes in v3:
-- fixed kernel test rebot report that "__iomem *off" is declared but not
used at dpu_hw_dsc_config_1_2()
-- unrolling thresh loops
On 03/05/2023 00:33, Abhinav Kumar wrote:
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
Move common DPU physical encoder initialization code to the new function
dpu_encoder_phys_init().
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 31
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
Move common DPU physical encoder initialization code to the new function
dpu_encoder_phys_init().
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 31 +--
On 03/05/2023 00:02, Kuogee Hsieh wrote:
During DSC setup, the crossbar mux need to be programmed to engage
DSC to specified PINGPONG. Hence during tear down, the crossbar mux
need to be reset to disengage DSC from PINGPONG. This patch add
PINGPONG_NONE to serve as disable to reset crossbar mux.
On 03/05/2023 00:02, Kuogee Hsieh wrote:
Legacy DPU requires PP block to be involved during DSC setting up.
This patch adds DDPU_PINGPONG_DSC feature bit to indicate that both
DPU_PINGPONG_DSC
dpu_hw_pp_setup_dsc() and dpu_hw_pp_dsc_enable() pingpong ops
functions are required to complete
On 03/05/2023 00:02, Kuogee Hsieh wrote:
From: Abhinav Kumar
There are some platforms has DSC blocks but it is not declared at catalog.
For completeness, this patch adds DSC blocks for platforms which missed
them.
Signed-off-by: Abhinav Kumar
---
On 03/05/2023 00:02, Kuogee Hsieh wrote:
This series adds the DPU side changes to support DSC 1.2 encoder. This
was validated with both DSI DSC 1.2 panel and DP DSC 1.2 monitor.
The DSI and DP parts will be pushed later on top of this change.
This seriel is rebase on [1], [2] and catalog fixes
On 02/05/2023 23:59, Abhinav Kumar wrote:
On 5/2/2023 1:54 PM, Dmitry Baryshkov wrote:
On Tue, 2 May 2023 at 23:45, Abhinav Kumar
wrote:
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
There is no need to clean up debugfs manually, it will be done by the
DRM core on device deregistration.
From: Abhinav Kumar
Add DSC 1.2 hardware blocks to the catalog with necessary sub-block and
feature flag information. Each display compression engine (DCE) contains
dual hard slice DSC encoders so both share same base address but with
its own different sub block address.
Signed-off-by: Abhinav
Current DSC flush update is piggyback inside dpu_hw_ctl_intf_cfg_v1().
This patch separates DSC flush away from dpu_hw_ctl_intf_cfg_v1() by
adding dpu_hw_ctl_update_pending_flush_dsc_v1() to handle both per
DSC engine and DSC flush bits at same time to make it consistent with
the location of flush
Add support for DSC 1.2 by providing the necessary hooks to program
the DPU DSC 1.2 encoder.
Changes in v3:
-- fixed kernel test rebot report that "__iomem *off" is declared but not
used at dpu_hw_dsc_config_1_2()
-- unrolling thresh loops
Reported-by: kernel test robot
Signed-off-by: Kuogee
During DSC setup, the crossbar mux need to be programmed to engage
DSC to specified PINGPONG. Hence during tear down, the crossbar mux
need to be reset to disengage DSC from PINGPONG. This patch add
PINGPONG_NONE to serve as disable to reset crossbar mux.
Signed-off-by: Kuogee Hsieh
---
At legacy chipsets, it required DPU_PINGPONG_DSC bit be set to indicate
pingpong ops functions are required to complete DSC data path setup if
this chipset has DSC hardware block presented. This patch add
DPU_PINGPONG_DSC bit to both PP_BLK and PP_BLK_TE marcos if it has DSC
hardware block
Legacy DPU requires PP block to be involved during DSC setting up.
This patch adds DDPU_PINGPONG_DSC feature bit to indicate that both
dpu_hw_pp_setup_dsc() and dpu_hw_pp_dsc_enable() pingpong ops
functions are required to complete DSC data path set up and start
DSC engine.
Reported-by : Marijn
From: Abhinav Kumar
There are some platforms has DSC blocks but it is not declared at catalog.
For completeness, this patch adds DSC blocks for platforms which missed
them.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 7 +++
This series adds the DPU side changes to support DSC 1.2 encoder. This
was validated with both DSI DSC 1.2 panel and DP DSC 1.2 monitor.
The DSI and DP parts will be pushed later on top of this change.
This seriel is rebase on [1], [2] and catalog fixes from [3].
[1]:
On 5/2/2023 1:54 PM, Dmitry Baryshkov wrote:
On Tue, 2 May 2023 at 23:45, Abhinav Kumar wrote:
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
There is no need to clean up debugfs manually, it will be done by the
DRM core on device deregistration.
Signed-off-by: Dmitry Baryshkov
---
On Tue, 2 May 2023 at 23:45, Abhinav Kumar wrote:
>
>
>
> On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
> > There is no need to clean up debugfs manually, it will be done by the
> > DRM core on device deregistration.
> >
> > Signed-off-by: Dmitry Baryshkov
> > ---
>
> There are two reasons to
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
There is no need to clean up debugfs manually, it will be done by the
DRM core on device deregistration.
Signed-off-by: Dmitry Baryshkov
---
There are two reasons to have the debugfs removed in the early_unregister:
1) Today, registration
On 5/1/2023 2:27 PM, Dmitry Baryshkov wrote:
On 02/05/2023 00:22, Abhinav Kumar wrote:
On 5/1/2023 1:45 PM, Dmitry Baryshkov wrote:
On 01/05/2023 22:58, Abhinav Kumar wrote:
On 4/30/2023 4:57 PM, Dmitry Baryshkov wrote:
There is no reason to split the dpu_encoder interface into
From: Rob Clark
Otherwise it is not always obvious if a dt or iommu change is causing us
to fall back to global pgtable.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_iommu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_iommu.c
From: Rob Clark
When the special handling of qcom,adreno-smmu was moved into
qcom_smmu_create(), it was overlooked that we didn't have all the
required entries in qcom_smmu_impl_of_match. So we stopped getting
adreno_smmu_priv on sc7180, breaking per-process pgtables.
Fixes: 30b912a03d91
Drop support for DPU_PLANE_QOS_VBLANK_CTRL flag. It is not used both
in upstream driver and in vendor SDE driver.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c| 8
Now as the struct dpu_hw_pipe_qos_cfg consists of only one bool field,
drop the structure and use corresponding bool directly.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 10 +++---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 13 ++---
This flag is always passed to _dpu_plane_set_qos_ctrl(), so drop it and
remove corresponding conditions from the mentioned function.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 27 +++
1 file changed, 8 insertions(+), 19 deletions(-)
diff
After removal of DPU_PLANE_QOS_VBLANK_CTRL, several fields of struct
dpu_hw_pipe_qos_cfg are fixed to false/0. Drop them from the structure
(and drop the corresponding code from the functions).
The DPU_PLANE_QOS_VBLANK_AMORTIZE flag is also removed, since it is now
a NOP.
Signed-off-by: Dmitry
Get rid of intermediatory configuration structure and defines. Pass the
format and the enablement bit directly to the new helper. The
WB_CDP_CNTL register ignores BIT(2), so we can write it for both SSPP
and WB CDP settings.
Signed-off-by: Dmitry Baryshkov
---
Rework SSPP and WB code to use common helper for programming QoS
settings.
Signed-off-by: Dmitry Baryshkov
---
.../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 31 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 19 +
Slightly rearrainge code in dpu_plane_sspp_update_pipe() to group
QoS/LUT related functions.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
The function dpu_plane_sspp_update_pipe() contains code to skip enabling
the QoS and OT limitis for CURSOR pipes. However all DPU since sdm845
repurpose DMA SSPP for the cursor planes because they lack the real
CURSOR SSPP. Fix the condition to actually check that the plane is
CURSOR or not.
Merge SSPP and WB code programming QoS and CDP. This allows us to drop
intermediate structures and duplicate code.
Changes since v1:
- Fixed kerneldoc for _dpu_plane_set_qos_ctrl()
- Fixed danger_safe_en programming conditions (Jeykumar)
- Simplified the code surrounding setup_cdp() calls
Reorder SSPP register definitions to sort them in the ascending order.
Move register bitfields after the register definitions.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 66 +++--
1 file changed, 34 insertions(+), 32 deletions(-)
diff
On 02/05/2023 03:56, Jeykumar Sankaran wrote:
On 4/30/2023 1:57 PM, Dmitry Baryshkov wrote:
The function dpu_plane_sspp_update_pipe() contains code to skip enabling
the QoS and OT limitis for CURSOR pipes. However all DPU since sdm845
repurpose DMA SSPP for the cursor planes because they lack
On 2.05.2023 09:49, Akhil P Oommen wrote:
> On Sat, Apr 01, 2023 at 01:54:43PM +0200, Konrad Dybcio wrote:
>> Some (particularly SMD_RPM, a.k.a non-RPMh) SoCs implement A6XX GPUs
>> but don't implement the associated GMUs. This is due to the fact that
>> the GMU directly pokes at RPMh. Sadly,
On 28/04/2023 15:45, Rob Clark wrote:
On Fri, Apr 28, 2023 at 3:56 AM Tvrtko Ursulin
wrote:
On 27/04/2023 18:53, Rob Clark wrote:
From: Rob Clark
Add support to dump GEM stats to fdinfo.
v2: Fix typos, change size units to match docs, use div_u64
v3: Do it in core
v4: more kerneldoc
On 01/05/2023 17:58, Rob Clark wrote:
On Fri, Apr 28, 2023 at 4:05 AM Tvrtko Ursulin
wrote:
On 27/04/2023 18:53, Rob Clark wrote:
From: Rob Clark
These are useful in particular for VM scenarios where the process which
has opened to drm device file is just a proxy for the real user in a
On Sat, Apr 01, 2023 at 01:54:43PM +0200, Konrad Dybcio wrote:
> Some (particularly SMD_RPM, a.k.a non-RPMh) SoCs implement A6XX GPUs
> but don't implement the associated GMUs. This is due to the fact that
> the GMU directly pokes at RPMh. Sadly, this means we have to take care
> of enabling &
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