On 25/11/2023 15:17, Konrad Dybcio wrote:
> Every Qualcomm SoC physically has a "CRYPTO0<->DDR" interconnect lane.
> Allow this property to be present, no matter the SoC.
>
> Signed-off-by: Konrad Dybcio
> ---
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysztof
On 25/11/2023 15:17, Konrad Dybcio wrote:
> QCM2290 has a single BWMONv4 intance for CPU. Document it.
>
> Signed-off-by: Konrad Dybcio
> ---
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysztof
On 25/11/2023 15:17, Konrad Dybcio wrote:
> In addition to MDP0, the cpu-cfg interconnect is also necessary.
> Allow it.
>
> Signed-off-by: Konrad Dybcio
> ---
> Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
>
On 25/11/2023 15:17, Konrad Dybcio wrote:
> Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there are
> other connection paths:
> - a path that connects rotator block to the DDR.
> - a path that needs to be handled to ensure MDSS register access
> functions properly, namely the "reg
On 25/11/2023 15:17, Konrad Dybcio wrote:
> The "qcom,dsi-ctrl-6g-qcm2290" has been deprecated in commit 0c0f65c6dd44
> ("dt-bindings: msm: dsi-controller-main: Add compatible strings for every
> current SoC"), but the example hasn't been updated to reflect that.
>
> Fix that.
>
> Fixes:
On 25/11/2023 14:17, Konrad Dybcio wrote:
The "qcom,dsi-ctrl-6g-qcm2290" has been deprecated in commit 0c0f65c6dd44
("dt-bindings: msm: dsi-controller-main: Add compatible strings for every
current SoC"), but the example hasn't been updated to reflect that.
Fix that.
Fixes: 0c0f65c6dd44
