On Wed, 13 Dec 2023 13:30:16 -0800, Jessica Zhang wrote:
> This series drops the frame_count and enable parameters (as they're always
> set to the same value). It also sets input_sel=0x1 for INTF.
>
Applied, thanks!
[1/2] drm/msm/dpu: Set input_sel bit for INTF
On Tue, 07 Nov 2023 02:43:33 +0200, Dmitry Baryshkov wrote:
> The funcion dp_display_get_next_bridge() can return -EPROBE_DEFER if the
> next bridge is not (yet) available. However returning -EPROBE_DEFER from
> msm_dp_modeset_init() is not ideal. This leads to -EPROBE return from
>
On Wed, 13 Dec 2023 at 20:58, Kuogee Hsieh wrote:
>
> At DSC V1.1 DCE (Display Compression Engine) contains a DSC encoder.
> However, at DSC V1.2 DCE consists of two DSC encoders, one has an odd
> index and another one has an even index. Each encoder can work
> independently. But only two DSC
On Wed, 13 Dec 2023 at 23:30, Jessica Zhang wrote:
>
> Drop the enable and frame_count parameters from dpu_hw_setup_misr() as they
> are always set to the same values.
>
> In addition, replace MISR_FRAME_COUNT_MASK with MISR_FRAME_COUNT as
> frame_count is always set to the same value.
>
> Fixes:
On 12/13/2023 1:30 PM, Jessica Zhang wrote:
Drop the enable and frame_count parameters from dpu_hw_setup_misr() as they
are always set to the same values.
In addition, replace MISR_FRAME_COUNT_MASK with MISR_FRAME_COUNT as
frame_count is always set to the same value.
Fixes: 7b37523fb1d1
On 12/13/2023 1:30 PM, Jessica Zhang wrote:
Set the input_sel bit for encoders as it was missed in the initial
implementation.
Reported-by: Rob Clark
Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/39
Fixes: 91143873a05d ("drm/msm/dpu: Add MISR register support for interface")
Drop the enable and frame_count parameters from dpu_hw_setup_misr() as they
are always set to the same values.
In addition, replace MISR_FRAME_COUNT_MASK with MISR_FRAME_COUNT as
frame_count is always set to the same value.
Fixes: 7b37523fb1d1 ("drm/msm/dpu: Move MISR methods to dpu_hw_util")
This series drops the frame_count and enable parameters (as they're always
set to the same value). It also sets input_sel=0x1 for INTF.
---
Changes in v4:
- Moved comment about input_sel to outside of dpu_hw_setup_misr()
- Link to v3:
https://lore.kernel.org/r/20231213-encoder-fixup-v3-0
Set the input_sel bit for encoders as it was missed in the initial
implementation.
Reported-by: Rob Clark
Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/39
Fixes: 91143873a05d ("drm/msm/dpu: Add MISR register support for interface")
Signed-off-by: Jessica Zhang
---
On 12/13/2023 1:20 PM, Dmitry Baryshkov wrote:
On Wed, 13 Dec 2023 at 22:51, Jessica Zhang wrote:
Set the input_sel bit for encoders as it was missed in the initial
implementation.
Reported-by: Rob Clark
Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/39
Fixes: 91143873a05d
Drop the enable and frame_count parameters from dpu_hw_setup_misr() as they
are always set to the same values.
In addition, replace MISR_FRAME_COUNT_MASK with MISR_FRAME_COUNT as
frame_count is always set to the same value.
Fixes: 7b37523fb1d1 ("drm/msm/dpu: Move MISR methods to dpu_hw_util")
Set the input_sel bit for encoders as it was missed in the initial
implementation.
Reported-by: Rob Clark
Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/39
Fixes: 91143873a05d ("drm/msm/dpu: Add MISR register support for interface")
Signed-off-by: Jessica Zhang
---
This series drops the frame_count and enable parameters (as they're always
set to the same value). It also sets input_sel=0x1 for INTF.
---
Changes in v3:
- Changed input_sel to u8
- Link to v2:
https://lore.kernel.org/r/20231213-encoder-fixup-v2-0-b11a4ad35...@quicinc.com
Changes in v2
On Wed, 13 Dec 2023 at 22:51, Jessica Zhang wrote:
>
> Set the input_sel bit for encoders as it was missed in the initial
> implementation.
>
> Reported-by: Rob Clark
> Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/39
> Fixes: 91143873a05d ("drm/msm/dpu: Add MISR register support for
On 12/2/2023 4:32 PM, Dmitry Baryshkov wrote:
Enable WB2 hardware block, enabling writeback support on this platform.
Signed-off-by: Dmitry Baryshkov
---
.../drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 18 ++
1 file changed, 18 insertions(+)
diff --git
On 12/2/2023 4:32 PM, Dmitry Baryshkov wrote:
Enable WB2 hardware block, enabling writeback support on this platform.
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h| 18 ++
1 file changed, 18 insertions(+)
diff --git
On 12/2/2023 4:32 PM, Dmitry Baryshkov wrote:
Enable WB2 hardware block, enabling writeback support on this platform.
Signed-off-by: Dmitry Baryshkov
---
.../drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 18 ++
1 file changed, 18 insertions(+)
diff --git
On 12/11/2023 10:23 PM, Dmitry Baryshkov wrote:
On Tue, 12 Dec 2023 at 02:30, Abhinav Kumar wrote:
On 12/2/2023 4:31 PM, Dmitry Baryshkov wrote:
I was not able to test it on my own, this is a call for testing for the
owners of these platforms. The git version of modetest now fully
On 12/13/2023 1:00 PM, Abhinav Kumar wrote:
On 12/13/2023 12:51 PM, Jessica Zhang wrote:
Drop the enable and frame_count parameters from dpu_hw_setup_misr() as
they
are always set to the same values.
In addition, replace MISR_FRAME_COUNT_MASK with MISR_FRAME_COUNT as
frame_count is
On 12/13/2023 12:51 PM, Jessica Zhang wrote:
Set the input_sel bit for encoders as it was missed in the initial
implementation.
Reported-by: Rob Clark
Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/39
Fixes: 91143873a05d ("drm/msm/dpu: Add MISR register support for interface")
On 12/13/2023 12:51 PM, Jessica Zhang wrote:
Drop the enable and frame_count parameters from dpu_hw_setup_misr() as they
are always set to the same values.
In addition, replace MISR_FRAME_COUNT_MASK with MISR_FRAME_COUNT as
frame_count is always set to the same value.
Fixes: 7b37523fb1d1
Drop the enable and frame_count parameters from dpu_hw_setup_misr() as they
are always set to the same values.
In addition, replace MISR_FRAME_COUNT_MASK with MISR_FRAME_COUNT as
frame_count is always set to the same value.
Fixes: 7b37523fb1d1 ("drm/msm/dpu: Move MISR methods to dpu_hw_util")
Set the input_sel bit for encoders as it was missed in the initial
implementation.
Reported-by: Rob Clark
Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/39
Fixes: 91143873a05d ("drm/msm/dpu: Add MISR register support for interface")
Signed-off-by: Jessica Zhang
---
This series drops the frame_count and enable parameters (as they're always
set to the same value). It also sets input_sel=0x1 for INTF.
---
Changes in v2:
- Switched patch order
- Changed input_sel parameter from bool to u8
- Link to v1:
On 12/2/2023 11:54 AM, Dmitry Baryshkov wrote:
On 01/12/2023 23:29, Abhinav Kumar wrote:
On 11/30/2023 11:36 PM, Dmitry Baryshkov wrote:
On Fri, 1 Dec 2023 at 03:31, Jessica Zhang
wrote:
Set the input_sel bit for encoders as it was missed in the initial
implementation.
Reported-by:
At DSC V1.1 DCE (Display Compression Engine) contains a DSC encoder.
However, at DSC V1.2 DCE consists of two DSC encoders, one has an odd
index and another one has an even index. Each encoder can work
independently. But only two DSC encoders from same DCE can be paired
to work together to support
On 11/12/2023 10:50, Konrad Dybcio wrote:
On 11.12.2023 10:46, Dmitry Baryshkov wrote:
On Mon, 11 Dec 2023 at 11:33, Konrad Dybcio wrote:
On 10.12.2023 00:21, Dmitry Baryshkov wrote:
Expand Combo USB+DP QMP PHY device node with the OF ports required to
support USB-C / DisplayPort switching.
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