On Tue, Sep 26, 2023 at 08:24:41PM +0200, Konrad Dybcio wrote:
>
> The SMMUs on sc7280 are cache-coherent. APPS_SMMU is marked as such,
> mark the GPU one as well.
>
> Signed-off-by: Konrad Dybcio
Reviewed-by: Akhil P Oommen
-Akhil
> ---
> arch/arm64/boot/dts/qcom/s
On Tue, Sep 26, 2023 at 08:24:40PM +0200, Konrad Dybcio wrote:
>
> GPU_SMMU SID 1 is meant for Adreno LPAC (Low Priority Async Compute).
> On platforms that support it (in firmware), it is necessary to
> describe that link, or Adreno register access will hang the board.
>
> Add that and fix up th
On Tue, Sep 26, 2023 at 08:24:37PM +0200, Konrad Dybcio wrote:
>
> Some (many?) devices with A635 expect a ZAP shader to be loaded.
>
> Set the file name to allow for that.
>
> Signed-off-by: Konrad Dybcio
> ---
> drivers/gpu/drm/msm/adreno/adreno_device.c | 1 +
> 1 file changed, 1 insertion(
in code does just that (AND returns an
> invalid error, (int)UINT_MAX). Fix that by defaulting to speedbin 0
> (which is conveniently always bound to fuseval == 0).
Wish we documented somewhere that we should reserve BIT(0) for fuse
val=0 always and assume that would be the super SKU.
Reviewed
On Thu, Jul 13, 2023 at 03:06:36PM -0700, Rob Clark wrote:
>
> On Thu, Jul 13, 2023 at 2:39 PM Akhil P Oommen
> wrote:
> >
> > On Fri, Jul 07, 2023 at 06:45:42AM +0300, Dmitry Baryshkov wrote:
> > >
> > > On 07/07/2023 00:10, Rob Clark wrote:
> > &
On Thu, Jul 13, 2023 at 03:25:33PM -0700, Rob Clark wrote:
>
> On Thu, Jul 13, 2023 at 1:06 PM Akhil P Oommen
> wrote:
> >
> > On Thu, Jul 06, 2023 at 02:10:38PM -0700, Rob Clark wrote:
> > >
> > > From: Rob Clark
> > >
> > > It is be
On Fri, Jul 07, 2023 at 02:40:47AM +0200, Konrad Dybcio wrote:
>
> On 6.07.2023 23:10, Rob Clark wrote:
> > From: Rob Clark
> >
> > There are cases where there are differences due to SoC integration.
> > Such as cache-coherency support, and (in the next patch) e-fuse to
> > speedbin mappings.
>
On Fri, Jul 07, 2023 at 06:45:42AM +0300, Dmitry Baryshkov wrote:
>
> On 07/07/2023 00:10, Rob Clark wrote:
> > From: Rob Clark
> >
> > Since the revision becomes an opaque identifier with future GPUs, move
> > away from treating different ranges of bits as having a given meaning.
> > This means
On Fri, Jul 07, 2023 at 05:34:04AM +0300, Dmitry Baryshkov wrote:
>
> On 07/07/2023 00:10, Rob Clark wrote:
> > From: Rob Clark
> >
> > There are cases where there are differences due to SoC integration.
> > Such as cache-coherency support, and (in the next patch) e-fuse to
> > speedbin mappings
On Thu, Jul 06, 2023 at 02:10:38PM -0700, Rob Clark wrote:
>
> From: Rob Clark
>
> It is better to explicitly list it. With the move to opaque chip-id's
> for future devices, we should avoid trying to infer things like
> generation from the numerical value.
>
> Signed-off-by: Rob Clark
> ---
On Fri, Jul 07, 2023 at 01:22:56AM +0200, Konrad Dybcio wrote:
>
> On 6.07.2023 23:10, Rob Clark wrote:
> > From: Rob Clark
> >
> > Even in the ocmem case, the allocated ocmem buffer size should match the
> > requested size.
> >
> > Signed-off-by: Rob Clark
> > ---
> [...]
>
> > +
> > + WAR
On Fri, Jun 30, 2023 at 09:20:43AM -0700, Rob Clark wrote:
>
> From: Rob Clark
>
> The range is actually len+1.
>
> Signed-off-by: Rob Clark
Reviewed-by: Akhil P Oommen
-Akhil
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 4 ++--
> 1 file changed, 2
x27;ve already mapped it once in
>* submit_reloc()
>*/
> - if (WARN_ON(!ptr))
> + if (WARN_ON(IS_ERR(ptr)))
nit: can we make this IS_ERR_OR_NULL() check to retain the current
validation? A null is catastrophic here. Yeah, I see that the current
6XX_SP_LB_5_DATA, 0x200),
> - SHADER(A6XX_SP_CB_BINDLESS_DATA, 0x2000),
> + SHADER(A6XX_SP_CB_BINDLESS_DATA, 0x800),
> SHADER(A6XX_SP_CB_LEGACY_DATA, 0x280),
> SHADER(A6XX_SP_UAV_DATA, 0x80),
> SHADER(A6XX_SP_INST_TAG, 0x80),
> --
> 2.41.0
>
Reviewed-by: Akhil P Oommen
-Akhil
On Fri, Jul 07, 2023 at 08:27:18PM +0300, Dmitry Baryshkov wrote:
>
> On 07/07/2023 18:03, Jordan Crouse wrote:
> > On Thu, Jul 06, 2023 at 09:55:13PM +0300, Dmitry Baryshkov wrote:
> > >
> > > On 10/03/2023 00:20, Jordan Crouse wrote:
> > > > While booting with amd,imageon on a headless target t
On Sat, Jun 17, 2023 at 02:00:50AM +0200, Konrad Dybcio wrote:
>
> On 16.06.2023 19:54, Akhil P Oommen wrote:
> > On Thu, Jun 15, 2023 at 11:43:04PM +0200, Konrad Dybcio wrote:
> >>
> >> On 10.06.2023 00:06, Akhil P Oommen wrote:
> >>> On Mon, May 29, 202
On Thu, Jun 15, 2023 at 11:43:04PM +0200, Konrad Dybcio wrote:
>
> On 10.06.2023 00:06, Akhil P Oommen wrote:
> > On Mon, May 29, 2023 at 03:52:29PM +0200, Konrad Dybcio wrote:
> >>
> >> Some (particularly SMD_RPM, a.k.a non-RPMh) SoCs implement A6XX GPUs
> >
On Fri, Jun 16, 2023 at 02:28:15PM +0200, Juerg Haefliger wrote:
>
> Add missing MODULE_FIRMWARE macros and remove some for firmwares that
> the driver no longer references.
>
> Signed-off-by: Juerg Haefliger
> ---
> drivers/gpu/drm/msm/adreno/adreno_device.c | 23 ++
> 1 fi
On Thu, Jun 15, 2023 at 10:59:23PM +0200, Konrad Dybcio wrote:
>
> On 15.06.2023 22:11, Akhil P Oommen wrote:
> > On Thu, Jun 15, 2023 at 12:34:06PM +0200, Konrad Dybcio wrote:
> >>
> >> On 6.06.2023 19:18, Akhil P Oommen wrote:
> >>> On Mon, May 29, 202
On Thu, Jun 15, 2023 at 12:34:06PM +0200, Konrad Dybcio wrote:
>
> On 6.06.2023 19:18, Akhil P Oommen wrote:
> > On Mon, May 29, 2023 at 03:52:26PM +0200, Konrad Dybcio wrote:
> >>
> >> Introduce a6xx_gpu_sw_reset() in preparation for adding GMU wra
UINT_MAX;
> +}
> +
> static u32 a618_get_speed_bin(u32 fuse)
> {
> if (fuse == 0)
> @@ -2195,6 +2219,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct
> adreno_gpu *adreno_gpu, u3
> {
> u32 val = UINT_MAX;
>
> + if (adreno_is_a610(a
fuse values with
> of_machine_is_compatible(). Do just that to enable frequency limiting
> on these SoCs.
>
> Reviewed-by: Dmitry Baryshkov
> Signed-off-by: Konrad Dybcio
Reviewed-by: Akhil P Oommen
-Akhil
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 31 +++
plicit revision matching. Do so to allow differentiating
> between A619 and A619_holi.
>
> Reviewed-by: Dmitry Baryshkov
> Signed-off-by: Konrad Dybcio
Reviewed-by: Akhil P Oommen
-Akhil
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 18 +-
> drivers/
On Mon, May 29, 2023 at 03:52:34PM +0200, Konrad Dybcio wrote:
>
> The GPU can only be one at a time. Turn a series of ifs into if +
> elseifs to save some CPU cycles.
>
> Reviewed-by: Dmitry Baryshkov
> Signed-off-by: Konrad Dybcio
Reviewed-by: Akhil P Oommen
-Akhil
&g
A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30)
> | 0x3f);
> + else if (adreno_is_a610(adreno_gpu))
> gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30)
> | 0x3ffff);
> else
> gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30)
> | 0x1f);
Reviewed-by: Akhil P Oommen
-Akhil
>
> --
> 2.40.1
>
On Mon, May 29, 2023 at 03:52:32PM +0200, Konrad Dybcio wrote:
>
> A610 is one of (if not the) lowest-tier SKUs in the A6XX family. It
> features no GMU, as it's implemented solely on SoCs with SMD_RPM.
> What's more interesting is that it does not feature a VDDGX line
> either, being powered sole
On Mon, May 29, 2023 at 03:52:29PM +0200, Konrad Dybcio wrote:
>
> Some (particularly SMD_RPM, a.k.a non-RPMh) SoCs implement A6XX GPUs
> but don't implement the associated GMUs. This is due to the fact that
> the GMU directly pokes at RPMh. Sadly, this means we have to take care
> of enabling & s
| ubwc_mode);
> +
> + gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, hbb_hi << 4 |
> + min_acc_len << 3 | hbb_lo << 1 | ubwc_mode);
> +
> + gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, hbb_hi << 10 |
> + uavflagprd_inv << 4 | min_acc_len << 3 |
> + hbb_lo << 1 | ubwc_mode);
> +
> + gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, min_acc_len << 23 | hbb_lo <<
> 21);
> }
>
> static int a6xx_cp_init(struct msm_gpu *gpu)
>
Reviewed-by: Akhil P Oommen
-Akhil
> --
> 2.40.1
>
On Mon, May 29, 2023 at 03:52:27PM +0200, Konrad Dybcio wrote:
>
> Currently we're only deasserting REG_A6XX_RBBM_GBIF_HALT, but we also
> need REG_A6XX_GBIF_HALT to be set to 0.
>
> This is typically done automatically on successful GX collapse, but in
> case that fails, we should take care of i
On Mon, May 29, 2023 at 03:52:26PM +0200, Konrad Dybcio wrote:
>
> Introduce a6xx_gpu_sw_reset() in preparation for adding GMU wrapper
> GPUs and reuse it in a6xx_gmu_force_off().
>
> This helper, contrary to the original usage in GMU code paths, adds
> a write memory barrier which together with
On Mon, May 29, 2023 at 03:52:25PM +0200, Konrad Dybcio wrote:
>
> Unify the indentation and explain the cryptic 0xF value.
>
> Signed-off-by: Konrad Dybcio
Reviewed-by: Akhil P Oommen
-Akhil
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 9 +
> 1 file change
in almost nothing
> being executed properly. Extend the disablement to adreno_has_gmu_wrapper,
> as none of the GMU wrapper Adrenos that don't support yet seem to feature it.
>
> Signed-off-by: Konrad Dybcio
> ---
Reviewed-by: Akhil P Oommen
-Akhil
> drivers/gpu/drm/msm/ad
ve the function to a6xx_gpu.c, remove the static keyword and add a
> prototype in a6xx_gpu.h to accomodate for the move.
>
> Signed-off-by: Konrad Dybcio
Reviewed-by: Akhil P Oommen
-Akhil
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 37
> ---
>
also very convenient to move this to GMU-specific code, so that
> it does not have to be guarded by an if-condition to avoid calling it
> on GMU wrapper targets.
>
> Move the write to the aforementioned a6xx_gmu_force_off() to achieve
> that. No effective functional change.
Review
On Tue, May 30, 2023 at 08:35:14AM -0700, Bjorn Andersson wrote:
>
> On Mon, May 29, 2023 at 02:16:14PM +0530, Manivannan Sadhasivam wrote:
> > On Mon, May 29, 2023 at 09:38:59AM +0200, Konrad Dybcio wrote:
> > > On 28.05.2023 19:07, Manivannan Sadhasivam wrote:
> > > > On Tue, May 23, 2023 at 09:
On Mon, May 29, 2023 at 09:38:59AM +0200, Konrad Dybcio wrote:
>
>
>
> On 28.05.2023 19:07, Manivannan Sadhasivam wrote:
> > On Tue, May 23, 2023 at 09:59:53AM +0200, Konrad Dybcio wrote:
> >>
> >>
> >> On 23.05.2023 03:15, Bjorn Andersson wrote:
> >>> From: Bjorn Andersson
> >>>
> >>> Add Adre
On Wed, May 31, 2023 at 10:30:09PM +0200, Konrad Dybcio wrote:
>
>
>
> On 31.05.2023 05:09, Bjorn Andersson wrote:
> > From: Bjorn Andersson
> >
> > Introduce support for the Adreno A690, found in Qualcomm SC8280XP.
> >
> > Tested-by: Steev Klimaszewski
> > Reviewed-by: Konrad Dybcio
> > Si
On Mon, May 08, 2023 at 10:59:24AM +0200, Konrad Dybcio wrote:
>
>
> On 6.05.2023 16:46, Akhil P Oommen wrote:
> > On Fri, May 05, 2023 at 12:35:18PM +0200, Konrad Dybcio wrote:
> >>
> >>
> >> On 5.05.2023 10:46, Akhil P Oommen wrote:
> >>> O
On Sun, May 07, 2023 at 02:16:36AM +0530, Akhil P Oommen wrote:
> On Sat, May 06, 2023 at 08:16:21PM +0530, Akhil P Oommen wrote:
> > On Fri, May 05, 2023 at 12:35:18PM +0200, Konrad Dybcio wrote:
> > >
> > >
> > > On 5.05.2023 10:46, Akhil P Oommen wrote:
&
On Sat, May 06, 2023 at 08:16:21PM +0530, Akhil P Oommen wrote:
> On Fri, May 05, 2023 at 12:35:18PM +0200, Konrad Dybcio wrote:
> >
> >
> > On 5.05.2023 10:46, Akhil P Oommen wrote:
> > > On Thu, May 04, 2023 at 08:34:07AM +0200, Konrad Dybcio wrote:
> >
On Fri, May 05, 2023 at 12:35:18PM +0200, Konrad Dybcio wrote:
>
>
> On 5.05.2023 10:46, Akhil P Oommen wrote:
> > On Thu, May 04, 2023 at 08:34:07AM +0200, Konrad Dybcio wrote:
> >>
> >>
> >> On 3.05.2023 22:32, Akhil P Oommen wrote:
> >>> O
On Thu, May 04, 2023 at 08:34:07AM +0200, Konrad Dybcio wrote:
>
>
> On 3.05.2023 22:32, Akhil P Oommen wrote:
> > On Tue, May 02, 2023 at 11:40:26AM +0200, Konrad Dybcio wrote:
> >>
> >>
> >> On 2.05.2023 09:49, Akhil P Oommen wrote:
> >>> O
On Tue, May 02, 2023 at 11:40:26AM +0200, Konrad Dybcio wrote:
>
>
> On 2.05.2023 09:49, Akhil P Oommen wrote:
> > On Sat, Apr 01, 2023 at 01:54:43PM +0200, Konrad Dybcio wrote:
> >> Some (particularly SMD_RPM, a.k.a non-RPMh) SoCs implement A6XX GPUs
> >> but do
On Sat, Apr 01, 2023 at 01:54:43PM +0200, Konrad Dybcio wrote:
> Some (particularly SMD_RPM, a.k.a non-RPMh) SoCs implement A6XX GPUs
> but don't implement the associated GMUs. This is due to the fact that
> the GMU directly pokes at RPMh. Sadly, this means we have to take care
> of enabling & scal
On Fri, Mar 31, 2023 at 01:25:20AM +0200, Konrad Dybcio wrote:
> Some (particularly SMD_RPM, a.k.a non-RPMh) SoCs implement A6XX GPUs
> but don't implement the associated GMUs. This is due to the fact that
> the GMU directly pokes at RPMh. Sadly, this means we have to take care
> of enabling & scal
On 3/1/2023 2:14 AM, Akhil P Oommen wrote:
> On 3/1/2023 2:10 AM, Konrad Dybcio wrote:
>> On 28.02.2023 21:23, Akhil P Oommen wrote:
>>> On 2/23/2023 5:36 PM, Konrad Dybcio wrote:
>>>> Rename lower_bit to hbb_lo and explain what it signifies.
>>>> Ad
On 3/1/2023 2:10 AM, Konrad Dybcio wrote:
>
> On 28.02.2023 21:23, Akhil P Oommen wrote:
>> On 2/23/2023 5:36 PM, Konrad Dybcio wrote:
>>> Rename lower_bit to hbb_lo and explain what it signifies.
>>> Add explanations (wherever possible to other tunables).
>>&g
On 2/23/2023 5:36 PM, Konrad Dybcio wrote:
> Rename lower_bit to hbb_lo and explain what it signifies.
> Add explanations (wherever possible to other tunables).
>
> Sort the variable definition and assignment alphabetically.
Sorting based on decreasing order of line length is more readable, isn't i
On 1/26/2023 8:46 PM, Konrad Dybcio wrote:
> Port setting min_access_length, ubwc_mode and upper_bit from downstream.
> Values were validated using downstream device trees for SM8[123]50 and
> left default (as per downstream) elsewhere.
>
> Signed-off-by: Konrad Dybcio
> ---
> drivers/gpu/drm/msm
ne ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2)
>
> struct adreno_rev {
> uint8_t core;
> @@ -65,7 +63,7 @@ struct adreno_info {
> const char *name;
> const char *fw[ADRENO_FW_MAX];
> uint32_t gmem;
> - enum adreno_quirks quirks;
> +
ensure that cx gdsc has collapsed
before we turn it back ON.
Signed-off-by: Akhil P Oommen
Reviewed-by: Ulf Hansson
---
(no changes since v2)
Changes in v2:
- Select PM_GENERIC_DOMAINS from Kconfig
drivers/gpu/drm/msm/Kconfig | 1 +
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 15
ffectively reverts commit 1f6cca404918
("drm/msm/a6xx: Ensure CX collapse during gpu recovery").
Signed-off-by: Akhil P Oommen
Reviewed-by: Ulf Hansson
---
(no changes since v3)
Changes in v3:
- Updated commit msg (Philipp)
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4
drivers/g
0:3d6a000.gmuactive 0
Signed-off-by: Akhil P Oommen
Reviewed-by: Ulf Hansson
---
(no changes since v1)
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 31 +++
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 1 +
2 files changed, 28 insertions(+), 4 deletions(-)
Add support for the newly added 'synced_poweroff' genpd flag. This allows
some clients (like adreno gpu driver) to request gdsc driver to ensure
a votable gdsc (like gpucc cx gdsc) has collapsed at hardware.
Signed-off-by: Akhil P Oommen
Reviewed-by: Ulf Hansson
---
(no change
which requires that the
'gpucc cx gdsc' power domain should move to OFF state in hardware at
least once before turning in ON again to clear the internal state.
Signed-off-by: Ulf Hansson
Signed-off-by: Akhil P Oommen
Reviewed-by: Bjorn Andersson
---
(no changes since v4)
Changes in v4:
'wait (Stephen)
Changes in v2:
- Minor formatting fix
- Select PM_GENERIC_DOMAINS from Kconfig
Akhil P Oommen (4):
clk: qcom: gdsc: Support 'synced_poweroff' genpd flag
drm/msm/a6xx: Vote for cx gdsc from gpu driver
drm/msm/a6xx: Remove cx gdsc polling using 'reset&#x
On 12/29/2022 12:13 AM, Bjorn Andersson wrote:
> On Wed, Dec 21, 2022 at 10:43:59PM +0530, Akhil P Oommen wrote:
>> From: Ulf Hansson
>>
>> Some genpd providers doesn't ensure that it has turned off at hardware.
>> This is fine until the consumer really requires
lf Hansson wrote:
>>>>> On Wed, 7 Dec 2022 at 17:55, Bjorn Andersson wrote:
>>>>>> On Wed, Dec 07, 2022 at 05:00:51PM +0100, Ulf Hansson wrote:
>>>>>>> On Thu, 1 Dec 2022 at 23:57, Bjorn Andersson
>>>>>>> wrote:
>>>
On 12/21/2022 8:13 PM, Ulf Hansson wrote:
> On Tue, 20 Dec 2022 at 08:44, Akhil P Oommen wrote:
>> From: Ulf Hansson
>>
>> Some genpd providers doesn't ensure that it has turned off at hardware.
>> This is fine until the consumer really requires during some spe
ensure that cx gdsc has collapsed
before we turn it back ON.
Signed-off-by: Akhil P Oommen
---
(no changes since v2)
Changes in v2:
- Select PM_GENERIC_DOMAINS from Kconfig
drivers/gpu/drm/msm/Kconfig | 1 +
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 15 +++
drivers/gpu/drm
ffectively reverts commit 1f6cca404918
("drm/msm/a6xx: Ensure CX collapse during gpu recovery").
Signed-off-by: Akhil P Oommen
---
(no changes since v3)
Changes in v3:
- Updated commit msg (Philipp)
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4
drivers/gpu/drm/msm/msm_gpu.c |
Add support for the newly added 'synced_poweroff' genpd flag. This allows
some clients (like adreno gpu driver) to request gdsc driver to ensure
a votable gdsc (like gpucc cx gdsc) has collapsed at hardware.
Signed-off-by: Akhil P Oommen
---
(no changes since v3)
Changes in v3:
-
0:3d6a000.gmuactive 0
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 31 +++
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 1 +
2 files changed, 28 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/d
which requires that the
'gpucc cx gdsc' power domain should move to OFF state in hardware at
least once before turning in ON again to clear the internal state.
Signed-off-by: Ulf Hansson
Signed-off-by: Akhil P Oommen
---
Changes in v4:
- Update genpd function documentation (Ulf)
Changes
rmatting fix
- Select PM_GENERIC_DOMAINS from Kconfig
Akhil P Oommen (4):
clk: qcom: gdsc: Support 'synced_poweroff' genpd flag
drm/msm/a6xx: Vote for cx gdsc from gpu driver
drm/msm/a6xx: Remove cx gdsc polling using 'reset'
drm/msm/a6xx: Use genpd notifier to ensur
Since RoQ size differs between generations, calculate dynamically the
RoQ size while capturing coredump.
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 11 ++-
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h | 17 ++---
2
Ensure that we do drm_dev_put() when there is an early return in
msm_drm_init().
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
drivers/gpu/drm/msm/disp/msm_disp_snapshot.c | 3 +++
drivers/gpu/drm/msm/msm_drv.c| 11 +++
2 files changed, 10 insertions(+), 4
Update gpu coredump for a660/a650 family of gpus with the extra
information available.
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 18 +++
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 50 -
drivers
anced pm_runtime_enable in
adreno_gpu_{init, cleanup}")
Signed-off-by: Akhil P Oommen
---
Changes in v2:
- Added 'Fixes' tag (Dan Carpenter)
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.
ensure that cx gdsc has collapsed
before we turn it back ON.
Signed-off-by: Akhil P Oommen
---
(no changes since v2)
Changes in v2:
- Select PM_GENERIC_DOMAINS from Kconfig
drivers/gpu/drm/msm/Kconfig | 1 +
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 15 +++
drivers/gpu/drm
ffectively reverts commit 1f6cca404918
("drm/msm/a6xx: Ensure CX collapse during gpu recovery").
Signed-off-by: Akhil P Oommen
---
Changes in v3:
- Updated commit msg (Philipp)
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4
drivers/gpu/drm/msm/msm_gpu.c | 4
drivers/g
0:3d6a000.gmuactive 0
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 31 +++
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 1 +
2 files changed, 28 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/d
s rebased on top of linux-next (20221215) since the changes span
multiple drivers.
[1] https://patchwork.freedesktop.org/series/107507/
Changes in v3:
- Rename the var 'force_sync' to 'wait (Stephen)
Changes in v2:
- Minor formatting fix
- Select PM_GENERIC_DOMAINS from Kconfig
A
Add support for the newly added 'synced_poweroff' genpd flag. This allows
some clients (like adreno gpu driver) to request gdsc driver to ensure
a votable gdsc (like gpucc cx gdsc) has collapsed at hardware.
Signed-off-by: Akhil P Oommen
---
Changes in v3:
- Rename the var 'force
which requires that the
'gpucc cx gdsc' power domain should move to OFF state in hardware at
least once before turning in ON again to clear the internal state.
Signed-off-by: Ulf Hansson
Signed-off-by: Akhil P Oommen
---
(no changes since v2)
Changes in v2:
- Minor formatting fix
dri
As per the downstream driver, gx gbif halt is required only during
recovery sequence. So lets avoid it during regular rpm suspend.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 15 +--
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 7 +++
drivers/gpu/drm
0:3d6a000.gmuactive 0
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 31 +++
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 1 +
2 files changed, 28 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/d
ensure that cx gdsc has collapsed
before we turn it back ON.
Signed-off-by: Akhil P Oommen
---
Changes in v2:
- Select PM_GENERIC_DOMAINS from Kconfig
drivers/gpu/drm/msm/Kconfig | 1 +
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 15 +++
drivers/gpu/drm/msm/adreno/a6xx_gmu.h
-by: Akhil P Oommen
---
(no changes since v1)
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4
drivers/gpu/drm/msm/msm_gpu.c | 4
drivers/gpu/drm/msm/msm_gpu.h | 4
3 files changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/
Add support for the newly added 'synced_poweroff' genpd flag. This allows
some clients (like adreno gpu driver) to request gdsc driver to ensure
a votable gdsc (like gpucc cx gdsc) has collapsed at hardware.
Signed-off-by: Akhil P Oommen
---
(no changes since v1)
drivers/clk/qcom/g
s rebased on top of linux-next (20221215) since the changes span
multiple drivers.
[1] https://patchwork.freedesktop.org/series/107507/
Changes in v2:
- Minor formatting fix
- Select PM_GENERIC_DOMAINS from Kconfig
Akhil P Oommen (4):
clk: qcom: gdsc: Support 'synced_poweroff' genpd fl
which requires that the
'gpucc cx gdsc' power domain should move to OFF state in hardware at
least once before turning in ON again to clear the internal state.
Signed-off-by: Ulf Hansson
Signed-off-by: Akhil P Oommen
---
Changes in v2:
- Minor formatting fix
drivers/base/powe
ensure that cx gdsc has collapsed
before we turn it back ON.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 15 +++
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 6 ++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 11 +++
3 files changed, 32 insertions
0:3d6a000.gmuactive 0
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 31 +++
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 1 +
2 files changed, 28 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4
drivers/gpu/drm/msm/msm_gpu.c | 4
drivers/gpu/drm/msm/msm_gpu.h | 4
3 files changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_g
Add support for the newly added 'synced_poweroff' genpd flag. This allows
some clients (like adreno gpu driver) to request gdsc driver to ensure
a votable gdsc (like gpucc cx gdsc) has collapsed at hardware.
Signed-off-by: Akhil P Oommen
---
drivers/clk/qcom/gdsc.c | 11 ++---
which requires that the
'gpucc cx gdsc' power domain should move to OFF state in hardware at
least once before turning in ON again to clear the internal state.
Signed-off-by: Ulf Hansson
Signed-off-by: Akhil P Oommen
---
@Ulf, I took the liberty to cleanup and post your patch.
dri
s rebased on top of linux-next (20221215) since the changes span
multiple drivers.
[1] https://patchwork.freedesktop.org/series/107507/
Akhil P Oommen (4):
clk: qcom: gdsc: Support 'synced_poweroff' genpd flag
drm/msm/a6xx: Vote for cx gdsc from gpu driver
drm/msm/a6xx: Remove cx g
speed_bin(fuse);
>
> + if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev))
> + val = a640_get_speed_bin(fuse);
> +
> if (val == UINT_MAX) {
> DRM_DEV_ERROR(dev,
> "missing support for speed-bin: %u. Some OPPs may not
> be supported by hardware\n",
Reviewed-by: Akhil P Oommen
-Akhil.
On 12/9/2022 2:39 AM, Bjorn Andersson wrote:
> On Thu, Dec 08, 2022 at 08:54:39PM +0530, Akhil P Oommen wrote:
>> On 12/7/2022 9:16 PM, Ulf Hansson wrote:
>>> On Wed, 5 Oct 2022 at 11:08, Akhil P Oommen
>>> wrote:
>>>> Allow a consumer driver to
te:
>>>>> On Wed, Dec 07, 2022 at 05:00:51PM +0100, Ulf Hansson wrote:
>>>>>> On Thu, 1 Dec 2022 at 23:57, Bjorn Andersson
>>>>>> wrote:
>>>>>>> On Wed, Oct 05, 2022 at 02:36:58PM +0530, Akhil P Oommen wrote:
>>>>
On 12/7/2022 9:30 PM, Ulf Hansson wrote:
> On Thu, 1 Dec 2022 at 23:57, Bjorn Andersson wrote:
>> On Wed, Oct 05, 2022 at 02:36:58PM +0530, Akhil P Oommen wrote:
>> @Ulf, Akhil has a power-domain for a piece of hardware which may be
>> voted active by multiple different subs
On 12/8/2022 8:32 PM, Akhil P Oommen wrote:
> On 12/7/2022 9:15 PM, Ulf Hansson wrote:
>> On Wed, 5 Oct 2022 at 11:08, Akhil P Oommen wrote:
>>> Add a reset op compatible function to poll for gdsc collapse. This is
>>> required because:
>>> 1. We don'
On 12/7/2022 9:16 PM, Ulf Hansson wrote:
> On Wed, 5 Oct 2022 at 11:08, Akhil P Oommen wrote:
>> Allow a consumer driver to poll for cx gdsc collapse through Reset
>> framework.
> Would you mind extending this commit message, to allow us to better
> understand what part i
On 12/7/2022 9:15 PM, Ulf Hansson wrote:
> On Wed, 5 Oct 2022 at 11:08, Akhil P Oommen wrote:
>> Add a reset op compatible function to poll for gdsc collapse. This is
>> required because:
>> 1. We don't wait for it to turn OFF at hardware for VOTABLE GDSCs.
>>
On 12/8/2022 7:10 PM, Ulf Hansson wrote:
> On Wed, 7 Dec 2022 at 17:55, Bjorn Andersson wrote:
>> On Wed, Dec 07, 2022 at 05:00:51PM +0100, Ulf Hansson wrote:
>>> On Thu, 1 Dec 2022 at 23:57, Bjorn Andersson wrote:
>>>> On Wed, Oct 05, 2022 at 02:36:58PM +0530, A
On 12/5/2022 2:10 PM, Dan Carpenter wrote:
> On Sun, Dec 04, 2022 at 04:11:41AM +0530, Akhil P Oommen wrote:
>> Fix the below kernel panic due to null pointer access:
>> [ 18.504431] Unable to handle kernel NULL pointer dereference at virtual
>> address 0048
On 12/2/2022 12:30 PM, Akhil P Oommen wrote:
> On 12/2/2022 4:27 AM, Bjorn Andersson wrote:
>> On Wed, Oct 05, 2022 at 02:36:58PM +0530, Akhil P Oommen wrote:
>> @Ulf, Akhil has a power-domain for a piece of hardware which may be
>> voted active by multiple different subs
Since RoQ size differs between generations, calculate dynamically the
RoQ size while capturing coredump.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 11 ++-
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h | 17 ++---
2 files changed, 20
Update gpu coredump for a660/a650 family of gpus with the extra
information available.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 18 +++
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 50 -
drivers/gpu/drm/msm/adreno
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