f-by: Marc Gonzalez
Reviewed-by: Bryan O'Donoghue
Reviewed-by: Jeffrey Hugo
On Wed, Sep 8, 2021 at 2:26 AM Dmitry Baryshkov
wrote:
>
> Hi,
>
> On Tue, 7 Sept 2021 at 22:13, Jeffrey Hugo wrote:
> >
> > On Wed, Sep 1, 2021 at 12:11 PM AngeloGioacchino Del Regno
> > wrote:
> > >
> > > Bringup functionality for MSM8998 i
On Wed, Sep 1, 2021 at 12:11 PM AngeloGioacchino Del Regno
wrote:
>
> Bringup functionality for MSM8998 in the DPU, driver which is mostly
> the same as SDM845 (just a few variations).
>
> Signed-off-by: AngeloGioacchino Del Regno
>
I don't seem to see a cover letter for this series.
Eh,
On Tue, May 25, 2021 at 11:46 PM Vinod Koul wrote:
>
> Hello Jeff,
>
> On 21-05-21, 08:09, Jeffrey Hugo wrote:
> > On Fri, May 21, 2021 at 6:50 AM Vinod Koul wrote:
> > >
> > > Display Stream Compression (DSC) compresses the display stream in host
> &g
On Fri, May 21, 2021 at 6:50 AM Vinod Koul wrote:
>
> Display Stream Compression (DSC) compresses the display stream in host which
> is later decoded by panel. This series enables this for Qualcomm msm driver.
> This was tested on Google Pixel3 phone which use LGE SW43408 panel.
>
> The changes
On Mon, Jul 13, 2020 at 5:50 PM Doug Anderson wrote:
>
> Hi,
>
> On Mon, Jul 13, 2020 at 1:25 PM Rob Herring wrote:
> >
> > On Mon, Jul 13, 2020 at 9:08 AM Doug Anderson wrote:
> > >
> > > Hi,
> > >
> > > On Mon, Jul 13, 2020 at 7:11 AM Rob Herring wrote:
> > > >
> > > > On Fri, Jul 10, 2020
On Mon, Jul 13, 2020 at 8:11 AM Rob Herring wrote:
>
> On Fri, Jul 10, 2020 at 5:02 PM Douglas Anderson
> wrote:
> >
> > I found that if I ever had a little mistake in my kernel config,
> > or device tree, or graphics driver that my system would sit in a loop
> > at bootup trying again and
On Mon, Jun 15, 2020 at 4:51 PM wrote:
>
> On 2020-06-12 16:26, Stephen Boyd wrote:
>
> Thanks for reviews Stephen.
>
> > Quoting Tanmay Shah (2020-06-11 18:50:25)
> >> These patches add support for Display-Port driver on SnapDragon
> >> hardware. It adds
> >> DP driver and DP PLL driver files
On Mon, May 11, 2020 at 3:03 PM Konrad Dybcio wrote:
>
> >Is the "| 0" really adding value here?
>
> As far as I can see, it is present in every other config.
Ah, I forgot about that.
Nothing to see here.
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On Fri, May 1, 2020 at 2:52 PM Konrad Dybcio wrote:
>
> Signed-off-by: Konrad Dybcio
> ---
> drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 70
> 1 file changed, 70 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
>
On Tue, Mar 3, 2020 at 8:43 AM Jordan Crouse wrote:
>
> On Mon, Mar 02, 2020 at 09:49:06PM +0100, Sam Ravnborg wrote:
> > Hi Jordan.
> >
> > On Mon, Mar 02, 2020 at 11:23:43AM -0700, Jordan Crouse wrote:
> > > Convert display/msm/gmu.txt to display/msm/gmu.yaml and remove the old
> > > text
On Tue, Feb 11, 2020 at 5:28 PM Rob Clark wrote:
>
> On Tue, Feb 11, 2020 at 7:59 AM Jeffrey Hugo wrote:
> >
> > On Tue, Feb 11, 2020 at 8:44 AM Rob Clark wrote:
> > >
> > > On Mon, Feb 10, 2020 at 9:58 PM wrote:
> > > >
> > > > On 2
On Tue, Feb 11, 2020 at 8:44 AM Rob Clark wrote:
>
> On Mon, Feb 10, 2020 at 9:58 PM wrote:
> >
> > On 2020-02-07 19:40, Jeffrey Hugo wrote:
> > > On Fri, Feb 7, 2020 at 5:38 AM wrote:
> > >>
> > >> On 2020-02-06 20:29, Jeffrey Hugo wrote:
>
On Fri, Feb 7, 2020 at 5:38 AM wrote:
>
> On 2020-02-06 20:29, Jeffrey Hugo wrote:
> > On Thu, Feb 6, 2020 at 2:13 AM Harigovindan P
> > wrote:
> >>
> >> For a given byte clock, if VCO recalc value is exactly same as
> >> vco set rate value, vco_s
On Thu, Feb 6, 2020 at 2:13 AM Harigovindan P wrote:
>
> For a given byte clock, if VCO recalc value is exactly same as
> vco set rate value, vco_set_rate does not get called assuming
> VCO is already set to required value. But Due to GDSC toggle,
> VCO values are erased in the HW. To make sure
On Thu, Feb 6, 2020 at 1:52 AM Harigovindan P wrote:
>
> Save pll state before dsi host is powered off. Without this change
> some register values gets resetted.
The phy driver already does this. Why is the current implementation
insufficient?
>
> Signed-off-by: Harigovindan P
> ---
>
>
On Tue, Feb 4, 2020 at 7:15 AM Harigovindan P wrote:
>
> Updating bindings of dsi and dpu by adding and removing certain
> properties.
>
> Signed-off-by: Harigovindan P
> ---
>
> Changes in v1:
> - Adding "ahb" clock as a required property.
> - Adding "bus", "rot", "lut" as
On Mon, Dec 23, 2019 at 3:19 AM Harigovindan P wrote:
>
> Updating REG_DSI_LANE_CTRL register value by reading default
> register value and writing it back using bitwise OR with
> DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST. This works for all panels.
Why?
You explain what the code does, which I can
On Thu, Dec 12, 2019 at 7:40 PM Brian Masney wrote:
>
> Hi Jeffrey,
>
> On Tue, Dec 03, 2019 at 07:18:31AM -0700, Jeffrey Hugo wrote:
> > On Mon, Dec 2, 2019 at 6:40 PM Brian Masney wrote:
> > > On Wed, Nov 13, 2019 at 06:23:34AM -0500, Brian Masney wrote:
> >
On Mon, Dec 2, 2019 at 6:48 AM Chandan Uddaraju wrote:
>
> Add bindings for Snapdragon 845 DisplayPort and
> display-port PLL driver.
>
> Changes in V2:
> Provide details about sel-gpio
>
> Signed-off-by: Chandan Uddaraju
> ---
> .../devicetree/bindings/display/msm/dp.txt | 249
>
On Mon, Dec 2, 2019 at 6:40 PM Brian Masney wrote:
>
> Hi Jeffrey,
>
> On Wed, Nov 13, 2019 at 06:23:34AM -0500, Brian Masney wrote:
> > On Tue, Nov 12, 2019 at 08:38:27AM -0700, Jeffrey Hugo wrote:
> > > On Tue, Nov 12, 2019 at 3:49 AM Brian Masney
> &g
On Thu, Nov 14, 2019 at 10:47 AM Rob Clark wrote:
>
> On Thu, Nov 14, 2019 at 2:16 AM Harigovindan P
> wrote:
> >
> > Add DSI config changes to support DSI version.
> >
> > Signed-off-by: Harigovindan P
>
> Reviewed-by: Rob Clark
Can we fix the subject/commit text for this to indicate what
nal for command-mode panels.
>
> This fixes the error and gives us a counter for command-mode panels that
> we can use to implement async commit support for the MDP5 in a follow up
> patch.
>
> Signed-off-by: Brian Masney
> Suggested-by: Jeffrey Hugo
> ---
> drivers/gpu/drm
On Mon, Nov 11, 2019 at 4:38 AM Brian Masney wrote:
>
> On Sun, Nov 10, 2019 at 10:37:33AM -0700, Jeffrey Hugo wrote:
> > On Sun, Nov 10, 2019 at 6:53 AM Brian Masney wrote:
> > >
> > > On Fri, Nov 08, 2019 at 07:56:25AM -0700, Jeffrey Hugo wrote:
> > > T
On Sun, Nov 10, 2019 at 6:53 AM Brian Masney wrote:
>
> On Fri, Nov 08, 2019 at 07:56:25AM -0700, Jeffrey Hugo wrote:
> > On Thu, Nov 7, 2019 at 7:03 PM Rob Clark wrote:
> > >
> > > On Thu, Nov 7, 2019 at 9:40 AM Jeffrey Hugo
> > > wrote:
> > &
On Sat, Nov 9, 2019 at 5:02 AM Stephan Gerhold wrote:
>
> On Fri, Nov 08, 2019 at 08:47:08PM -0700, Jeffrey Hugo wrote:
> > On Fri, Nov 8, 2019 at 4:47 PM Stephan Gerhold wrote:
> > >
> > > On Fri, Nov 08, 2019 at 03:12:28PM -0700, Jeffrey Hugo wrote:
> >
On Fri, Nov 8, 2019 at 4:47 PM Stephan Gerhold wrote:
>
> On Fri, Nov 08, 2019 at 03:12:28PM -0700, Jeffrey Hugo wrote:
> > On Fri, Nov 8, 2019 at 2:29 PM Stephan Gerhold wrote:
> > >
> > > At the moment, the MSM DSI driver calls drm_panel_enable() rather e
On Fri, Nov 8, 2019 at 2:29 PM Stephan Gerhold wrote:
>
> At the moment, the MSM DSI driver calls drm_panel_enable() rather early
> from the DSI bridge pre_enable() function. At this point, the encoder
> (e.g. MDP5) is not enabled, so we have not started transmitting
> video data.
>
> However,
On Thu, Nov 7, 2019 at 7:03 PM Rob Clark wrote:
>
> On Thu, Nov 7, 2019 at 9:40 AM Jeffrey Hugo wrote:
> >
> > On Thu, Nov 7, 2019 at 9:17 AM Rob Clark wrote:
> > >
> > > On Thu, Nov 7, 2019 at 3:10 AM Brian Masney wrote:
> > > >
> > &
On Thu, Nov 7, 2019 at 9:17 AM Rob Clark wrote:
>
> On Thu, Nov 7, 2019 at 3:10 AM Brian Masney wrote:
> >
> > On Wed, Nov 06, 2019 at 08:58:59AM -0800, Rob Clark wrote:
> > > On Wed, Nov 6, 2019 at 8:47 AM Jeffrey Hugo
> > > wrote:
> > > >
On Wed, Nov 6, 2019 at 9:30 AM Rob Clark wrote:
>
> On Wed, Nov 6, 2019 at 1:13 AM Brian Masney wrote:
> >
> > On Tue, Nov 05, 2019 at 08:23:27AM -0800, Rob Clark wrote:
> > > On Tue, Nov 5, 2019 at 2:08 AM Brian Masney wrote:
> > > > The 'pp done time out' errors go away if I revert the
ot; property is optional and never present on
> i.MX5, turn the message into debug level instead.
>
> Signed-off-by: Fabio Estevam
Seems reasonable. Reviewed-by: Jeffrey Hugo
> ---
>
> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1
connector support)
Signed-off-by: Jeffrey Hugo
Reviewed-by: Sean Paul
---
v2:
-make a DEFINE for the delay
drivers/gpu/drm/msm/dsi/dsi_host.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index
On Thu, Oct 10, 2019 at 12:49 PM Sean Paul wrote:
>
> On Thu, Oct 10, 2019 at 2:45 PM Sean Paul wrote:
> >
> > On Wed, Oct 09, 2019 at 02:34:54PM -0700, Jeffrey Hugo wrote:
> > > On msm8998, vblank timeouts are observed because the DSI controller is not
> >
connector support)
Signed-off-by: Jeffrey Hugo
---
Rob et al, is it possible for this to go into a 5.4-rc?
drivers/gpu/drm/msm/dsi/dsi_host.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index
On Sun, Sep 22, 2019 at 8:16 AM wrote:
>
> From: "Angelo G. Del Regno"
>
> Some SoCs, like MSM8956/8976 (and APQ variants), do feature these
> clocks and we need to enable them in order to get the hardware to
> properly work.
>
> Signed-off-by: Angelo G. Del Regno
I don't see these clocks
> drivers/gpu/drm/msm/dsi/dsi_cfg.c:172:1: warning:
> ‘static’ is not at beginning of declaration [-Wold-style-declaration]
>
> Signed-off-by: Krzysztof Wilczynski
Seems fine to me.
Reviewed-by: Jeffrey Hugo
___
Freedreno
to see if that has an iommu reference, and if not, use the parent
device instead. This should handle all the various iommu designs for
mdp5 supported systems.
Signed-off-by: Jeffrey Hugo
---
v2: It turns out there isn't a universal way to get the iommu device, so
check to see if its
On Mon, Jul 1, 2019 at 1:55 PM Rob Clark wrote:
>
> On Mon, Jul 1, 2019 at 10:41 AM Jeffrey Hugo wrote:
> >
> > When assigning a mixer, we will iterate through the entire list looking for
> > a suitable match. This results in selecting the last match. We should
>
On Wed, Jul 3, 2019 at 6:25 AM Rob Clark wrote:
>
> On Tue, Jul 2, 2019 at 9:08 PM Bjorn Andersson
> wrote:
> >
> > On Mon 01 Jul 10:39 PDT 2019, Jeffrey Hugo wrote:
> >
> > > Creating the msm gem address space requires a reference to the dev where
>
On Tue, Jul 2, 2019 at 2:30 PM Jeffrey Hugo wrote:
>
> On Sun, Jun 30, 2019 at 7:16 AM Rob Clark wrote:
> > --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> > +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> > @@ -1824,6 +1824,20 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi)
nc__);
pr_err() doesn't seem right for a probe defer condition. pr_dbg?
> + return -EPROBE_DEFER;
> + }
> +
> +
Tested-by: Jeffrey Hugo
Reviewed-by: Jeffrey Hugo
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https://lists.freedesktop.org/mailman/listinfo/freedreno
On Mon, Jul 1, 2019 at 1:45 PM Rob Clark wrote:
>
> On Mon, Jul 1, 2019 at 10:39 AM Jeffrey Hugo wrote:
> >
> > Creating the msm gem address space requires a reference to the dev where
> > the iommu is located. The driver currently assumes this is the same as
> &
On 7/1/2019 12:58 PM, Rob Clark wrote:
On Mon, Jul 1, 2019 at 11:37 AM Jeffrey Hugo wrote:
On 6/30/2019 9:01 AM, Rob Clark wrote:
From: Rob Clark
Do an extra enable/disable cycle at init, to get the clks into disabled
state in case bootloader left them enabled.
In case they were already
On 6/30/2019 9:01 AM, Rob Clark wrote:
From: Rob Clark
Request the enable gpio ASIS to avoid disabling bridge during probe, if
already enabled. And if already enabled, defer enabling runpm until
attach to avoid cutting off the power to the bridge.
Once we get to attach, we know panel and drm
On Sun, Jun 30, 2019 at 9:03 AM Rob Clark wrote:
>
> From: Rob Clark
>
> Prep work for the following patch.
>
> Signed-off-by: Rob Clark
Reviewed-by: Jeffrey Hugo
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Freedreno@lists.fre
> kernel, the driver will most likely built as a module, and not probed
> until we get to userspace (after late_initcall)
>
> Signed-off-by: Rob Clark
Reviewed-by: Jeffrey Hugo
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http
after
> userspace starts, in a typical distro kernel), we don't want to kill
> the clocks and power domains that are used by the display before
> userspace starts.
>
> Signed-off-by: Rob Clark
Seems sane to me. I'm curious what Stephen Boyd thinks.
I'll try to give it
Add support for MDP5 version v3.0 found on msm8998.
Signed-off-by: Jeffrey Hugo
---
8998 support could probably be MDP5 or DPU. This MDP5 support works,
but may not support all of the features that 8998 supports. However,
DPU seems to only support 845 (MDP v4.0) with fundamental assumptions
to the proper device.
Signed-off-by: Jeffrey Hugo
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
index 4a60f5fca6b0..1347a5223918 100644
t;0xc4>;
What does this number represent? It is supposed to be defined by the
display_or_bridge_device, not a specific panel.
Its the specific FW/bootloader defined panel id, that matches the
above defined panel-id property.
We also need to consider how the DSI case with panels as children of
t
Signed-off-by: Jeffrey Hugo
---
drivers/gpu/drm/msm/msm_fbdev.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_fbdev.c b/drivers/gpu/drm/msm/msm_fbdev.c
index 2429d5e6ce9f..e3836c7725a6 100644
--- a/drivers/gpu/drm/msm/msm_fbdev.c
+++ b/drivers/gpu/drm/msm
, but it's status is disabled.
Fix this by checking the node's status before adding it to the match list.
Fixes: dc3ea265b856 ("drm/msm: Drop the gpu binding")
Signed-off-by: Jeffrey Hugo
---
drivers/gpu/drm/msm/msm_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
case, updated commit msg from Georgi.
> v3: split out icc setup into it's own function, and rework logic
> slightly so no interconnect paths is not fatal.
>
> Signed-off-by: Georgi Djakov
> Signed-off-by: Rob Clark
Looks good to me.
Reviewed-By: Jeffrey Hugo
_
On Tue, Jun 18, 2019 at 2:25 PM Rob Clark wrote:
>
> From: Georgi Djakov
>
> The interconnect API provides an interface for consumer drivers to
> express their bandwidth needs in the SoC. This data is aggregated
> and the on-chip interconnect hardware is configured to the most
> appropriate
The A540 is a derivative of the A530, and is found in the MSM8998 SoC.
Signed-off-by: Jeffrey Hugo
---
v3:
-Adjusted MERCIU for A540 for best performance.
drivers/gpu/drm/msm/adreno/a5xx.xml.h | 28
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 26 +++-
drivers/gpu/drm/msm
On Fri, May 31, 2019 at 4:09 PM Jordan Crouse wrote:
>
> Before loading the zap shader we should ensure that the reserved memory
> region is big enough to hold the loaded file.
>
> Signed-off-by: Jordan Crouse
Reviewed-by: Jeffrey Hugo
> ---
>
> drivers/gpu/drm/msm
m_crtc_set_max_vblank_count().
>
> This change was tested on a LG Nexus 5 (hammerhead) phone.
>
> Signed-off-by: Brian Masney
> Suggested-by: Jeffrey Hugo
Reviewed-by: Jeffrey Hugo
> ---
> drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 16 +++-
> drivers/gpu/drm/msm/d
The DSI controller on the MSM8998 SoC is a 6G v2.0.0 controller which is
very similar to the v2.0.1 of SDM845.
Signed-off-by: Jeffrey Hugo
---
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 21 +
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
2 files changed, 22 insertions(+)
diff --git
The MSM8998 dsi phy is 10nm v3.0.0 like SDM845, however there appear to
be minor differences such as the address space location.
Signed-off-by: Jeffrey Hugo
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 +
drivers/gpu/drm/msm/dsi/phy
The v3.0.0 10nm phy has two different implementations between MSM8998 and
SDM845, which require different timings calculations. Unfortunately, the
hardware designers did not choose to revise the version to account for this
delta so implement a quirk instead.
Signed-off-by: Jeffrey Hugo
The DSI phy on MSM8998 is a 10nm design like SDM845, however it has some
slightly different quirks which need to be handled by drivers. Provide
a separate compatible to assist in handling the specifics.
Signed-off-by: Jeffrey Hugo
---
Documentation/devicetree/bindings/display/msm/dsi.txt | 1
.
Jeffrey Hugo (4):
dt-bindings: msm/dsi: Add 10nm phy for msm8998 compatible
drm/msm/dsi: Add support for MSM8998 10nm dsi phy
drm/msm/dsi: Add old timings quirk for 10nm phy
drm/msm/dsi: Add support for MSM8998 DSI controller
.../devicetree/bindings/display/msm/dsi.txt | 1 +
drivers/gpu/drm
On 5/29/2019 1:30 PM, Brian Masney wrote:
On Wed, May 29, 2019 at 08:41:31AM -0600, Jeffrey Hugo wrote:
On Wed, May 29, 2019 at 4:28 AM Brian Masney wrote:
On Tue, May 28, 2019 at 08:53:49PM -0600, Jeffrey Hugo wrote:
On Tue, May 28, 2019 at 8:46 PM Brian Masney wrote:
On Tue, May 28
The A540 is a derivative of the A530, and is found in the MSM8998 SoC.
Signed-off-by: Jeffrey Hugo
---
drivers/gpu/drm/msm/adreno/a5xx.xml.h | 28
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 21 ++
drivers/gpu/drm/msm/adreno/a5xx_power.c| 76
---
rnndb/adreno/a5xx.xml | 1 +
1 file changed, 1 insertion(+)
diff --git a/rnndb/adreno/a5xx.xml b/rnndb/adreno/a5xx.xml
index ae654eeb..16203512 100644
--- a/rnndb/adreno/a5xx.xml
+++ b/rnndb/adreno/a5xx.xml
@@ -1523,6 +1523,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/
-Stripped extranious magic number comment
Jeffrey Hugo (1):
drm/msm/adreno: Add A540 support
drivers/gpu/drm/msm/adreno/a5xx.xml.h | 28
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 21 ++
drivers/gpu/drm/msm/adreno/a5xx_power.c| 76 +-
drivers/gpu/drm/msm
On Tue, May 28, 2019 at 8:15 PM Rob Clark wrote:
>
> On Tue, May 28, 2019 at 6:17 PM Brian Masney wrote:
> >
> > On Tue, May 28, 2019 at 03:46:14PM +0200, Linus Walleij wrote:
> > > On Thu, May 9, 2019 at 4:04 AM Brian Masney wrote:
> > >
> > > > Here is a patch series that adds initial display
On Tue, May 28, 2019 at 7:37 PM Brian Masney wrote:
>
> On Tue, May 28, 2019 at 07:32:14PM -0600, Jeffrey Hugo wrote:
> > On Tue, May 28, 2019 at 7:17 PM Brian Masney wrote:
> > >
> > > On Tue, May 28, 2019 at 03:46:14PM +0200, Linus Walleij wrote:
> > >
On Tue, May 28, 2019 at 7:17 PM Brian Masney wrote:
>
> On Tue, May 28, 2019 at 03:46:14PM +0200, Linus Walleij wrote:
> > On Thu, May 9, 2019 at 4:04 AM Brian Masney wrote:
> >
> > > Here is a patch series that adds initial display support for the LG
> > > Nexus 5 (hammerhead) phone. It's not
On Tue, May 28, 2019 at 2:45 PM Jordan Crouse wrote:
>
> On Tue, May 28, 2019 at 10:06:12AM -0700, Jeffrey Hugo wrote:
> > The A540 is a derivative of the A530, and is found in the MSM8998 SoC.
> >
> > Signed-off-by: Jeffrey Hugo
> > ---
> > drivers/gpu
module)
Signed-off-by: Jeffrey Hugo
Reviewed-by: Bjorn Andersson
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
index ea8f7d7daf7f..52e23780fce1
module)
Signed-off-by: Jeffrey Hugo
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
index ea8f7d7daf7f..52e23780fce1 100644
--- a/drivers/gpu/drm/msm
t, GFP_KERNEL);
if (!local)
return -ENOMEM;
Isn't msm_clk_bulk_get a duplication of devm_clk_bulk_get_all() ?
Surely it would be better to just use that instead?
--
Jeffrey Hugo
Qualcomm Datacenter Technologies as an affiliate of Qualcomm
Technologies, Inc.
Qualcomm
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