Re: [Freedreno] [PATCH 1/2] drm/msm: dpu: Only check flush register against pending flushes

2018-10-03 Thread Sean Paul
On Tue, Oct 02, 2018 at 06:14:38PM -0700, Jeykumar Sankaran wrote: > On 2018-10-01 13:29, Sean Paul wrote: > > On Wed, Sep 26, 2018 at 11:51:35AM -0700, Jeykumar Sankaran wrote: > > > On 2018-09-19 11:56, Sean Paul wrote: > > > > From: Sean Paul > > > > > > > > There exists a case where a flush

Re: [Freedreno] [PATCH 1/2] drm/msm: dpu: Only check flush register against pending flushes

2018-10-02 Thread Jeykumar Sankaran
On 2018-10-01 13:29, Sean Paul wrote: On Wed, Sep 26, 2018 at 11:51:35AM -0700, Jeykumar Sankaran wrote: On 2018-09-19 11:56, Sean Paul wrote: > From: Sean Paul > > There exists a case where a flush of a plane/dma may have been triggered > & started from an async commit. If that plane/dma is

Re: [Freedreno] [PATCH 1/2] drm/msm: dpu: Only check flush register against pending flushes

2018-10-01 Thread Sean Paul
On Wed, Sep 26, 2018 at 11:51:35AM -0700, Jeykumar Sankaran wrote: > On 2018-09-19 11:56, Sean Paul wrote: > > From: Sean Paul > > > > There exists a case where a flush of a plane/dma may have been triggered > > & started from an async commit. If that plane/dma is subsequently > > disabled > >

[Freedreno] [PATCH 1/2] drm/msm: dpu: Only check flush register against pending flushes

2018-09-19 Thread Sean Paul
From: Sean Paul There exists a case where a flush of a plane/dma may have been triggered & started from an async commit. If that plane/dma is subsequently disabled by the next commit, the flush register will continue to hold the flush bit for the disabled plane. Since the bit remains active,