Hi Angelo,
On 2021-01-20 16:34, AngeloGioacchino Del Regno wrote:
Il 11/01/21 13:04, Sai Prakash Ranjan ha scritto:
A6XX GPUs have support for last level cache(LLC) also known
as system cache and need to set the bus attributes to
use it. Currently we use a generic adreno iommu address space
On 2021-01-20 21:48, Rob Clark wrote:
On Mon, Jan 11, 2021 at 4:04 AM Sai Prakash Ranjan
wrote:
A6XX GPUs have support for last level cache(LLC) also known
as system cache and need to set the bus attributes to
use it. Currently we use a generic adreno iommu address space
implementation which
On Wed, Jan 20, 2021 at 3:04 AM AngeloGioacchino Del Regno
wrote:
>
> Il 11/01/21 13:04, Sai Prakash Ranjan ha scritto:
> > A6XX GPUs have support for last level cache(LLC) also known
> > as system cache and need to set the bus attributes to
> > use it. Currently we use a generic adreno iommu
On Mon, Jan 11, 2021 at 4:04 AM Sai Prakash Ranjan
wrote:
>
> A6XX GPUs have support for last level cache(LLC) also known
> as system cache and need to set the bus attributes to
> use it. Currently we use a generic adreno iommu address space
> implementation which are also used by older GPU
Il 11/01/21 13:04, Sai Prakash Ranjan ha scritto:
A6XX GPUs have support for last level cache(LLC) also known
as system cache and need to set the bus attributes to
use it. Currently we use a generic adreno iommu address space
implementation which are also used by older GPU generations
which do
A6XX GPUs have support for last level cache(LLC) also known
as system cache and need to set the bus attributes to
use it. Currently we use a generic adreno iommu address space
implementation which are also used by older GPU generations
which do not have LLC and might introduce issues accidentally
