[Freedreno] [PATCH 03/12] drm/msm: gpu Add new gpu register read/write functions

Add some new functions to manipulate GPU registers. gpu_read64 and gpu_write64 can read/write a 64 bit value to two 32 bit registers. For 4XX and older these are normally perfcounter registers, but future targets will use 64 bit addressing so there will be many more spots where a 64 bit read and

[Freedreno] [PATCH 01/12] drm/msm: gpu: Cut down the list of "generic" registers to the ones we use

There are very few register accesses in the common code. Cut down the list of common registers to just those that are used. This saves const space and saves us the effort of maintaining registers for A3XX and A4XX that don't exist or are unused. Signed-off-by: Jordan Crouse

[Freedreno] [PATCH 11/12] drm/msm: Add a quick and dirty PIL loader

In order to switch the GPU out of secure mode on most systems we need to load a zap shader into memory and get it authenticated and into the secure world. All the bits and pieces to do the load are scattered throughout the kernel, but we need to bring everything together. Add a semi-custom

[Freedreno] [PATCH 06/12] drm/msm: Remove 'src_clk' from adreno configuration

The adreno code inherited a silly workaround from downstream from the bad old days before decent clock control. grp_clk[0] (named 'src_clk') doesn't actually exist - it was used as a proxy for whatever the core clock actually was (usually 'core_clk'). All targets should be able to correctly

[Freedreno] [PATCH 09/12] drm/msm: gpu: Add support for the GPMU

Most 5XX targets have GPMU (Graphics Power Management Unit) that handles a lot of the heavy lifting for power management including thermal and limits management and dynamic power collapse. While the GPMU itself is optional, it is usually nessesary to hit aggressive power targets. The GPMU

[Freedreno] [PATCH 2/7] freedreno/a4xx: use new shader linkage helper

Signed-off-by: Rob Clark --- src/gallium/drivers/freedreno/a4xx/fd4_program.c | 43 +--- 1 file changed, 16 insertions(+), 27 deletions(-) diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_program.c b/src/gallium/drivers/freedreno/a4xx/fd4_program.c

[Freedreno] [PATCH 4/7] freedreno/ir3: don't offset inloc by 8

On a3xx/a4xx, the SP_VS_VPC_DST_REG.OUTLOCn is offset by 8, so we used to add this offset into fs->inputs[n].inloc. But a5xx drops this extra offset-by-8. So instead make inloc zero based and add the offset when we emit OUTLOCn values (for the gen's that need the offset). Signed-off-by: Rob

[Freedreno] [PATCH 5/7] freedreno: make gmem tile size alignment configurable

a5xx seems to prefer 64 pixel alignment, in at least some cases. Make this configurable per generation. Signed-off-by: Rob Clark --- src/gallium/drivers/freedreno/freedreno_gmem.c | 18 ++ src/gallium/drivers/freedreno/freedreno_screen.c | 6 ++

[Freedreno] [PATCH 0/7] freedreno: initial a5xx support

So, I've been working with Jordan's initial RFC patches for the kernel side support for adreno 5xx[1] on the dragonboard 820c. At this point I have the basics working.. (ie. a reasonable chunk of glmark2 working). There are ofc bugs to fix, and I've started to run through deqp (since that is

[Freedreno] [PATCH 00/12] Adreno A5XX support

All, here is initial kernel support for the Adreno A5XX family of GPUs found on the QTI Snapdragon 820 and 821 among others. This stack turns on the A5XX hardware and initializes the GPMU (Graphics Power Management Unit) which is a microcontroller to assist with more independent power management.

[Freedreno] [PATCH 08/12] drm/msm: gpu: Add A5XX target support

Add support for the A5XX family of Adreno GPUs. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 823 + drivers/gpu/drm/msm/adreno/a5xx_gpu.h | 37 ++

[Freedreno] [PATCH 04/12] drm/msm: Add adreno_gpu_write64()

Add a new generic function to write a "64" bit value. This isn't actually a 64 bit operation, it just writes the upper and lower 32 bit of a 64 bit value to a specified LO and HI register. If a particular target doesn't support one of the registers it can mark that register as SKIP and

[Freedreno] [PATCH 12/12] drm/msm: gpu: Use the zap shader on 5XX if we can

The A5XX GPU powers on in "secure" mode. In secure mode the GPU can only render to buffers that are marked as secure and inaccessible to the kernel and user through a series of hardware protections. In practice secure mode is used to draw things like a UI on a secure video frame. In order to

[Freedreno] [PATCH 07/12] drm/msm: Disable interrupts during init

Disable the interrupt during the init sequence to avoid having interrupts fired for errors and other things that we are not ready to handle while initializing. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/adreno_device.c | 4

[Freedreno] [PATCH 05/12] drm/msm: gpu: Add OUT_TYPE4 and OUT_TYPE7

Add helper functions for TYPE4 and TYPE7 ME opcodes that replace TYPE0 and TYPE3 starting with the A5XX targets. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 30 ++ 1 file changed, 30 insertions(+) diff --git

[Freedreno] [PATCH 10/12] firmware: qcom_scm: Add qcom_scm_gpu_zap_resume()

Add an interface to trigger the remote processor to reinitialize the GPU zap shader on power-up. Signed-off-by: Jordan Crouse --- drivers/firmware/qcom_scm-32.c | 5 + drivers/firmware/qcom_scm-64.c | 15 +++ drivers/firmware/qcom_scm.c| 6 ++