This patch adds a bit of infrastructure to give the different Adreno
targets the flexibility to setup the submitqueues per their needs.
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/msm_gpu.h | 7 +++
drivers/gpu/drm/msm/msm_submitqueue.c | 15
This patch follows Jordan's recent "drm/msm: Add A6XX device support"
patch series and adds preemption support. Preemption allows the GPU to switch
to a higher priority ringbuffer when one is ready, thereby improving user
experience. A6xx hardware supports various preemption levels, each with
This patch simply increases the number of available ringbuffers,
therefore enabling preemption.
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
This patch adds the following two opcodes:
CP_SET_MARKER opcode is a way to tell CP the current mode of GPU
operation(useful if preemption is in use).
CP_SET_PSEUDO_REG opcode will instruct CP to set a bunch of internal
CP registers, again useful for the preemption save/restore sequence.
On Sat, Feb 24, 2018 at 09:52:27AM +0100, Pavel Machek wrote:
> Hi!
>
> > > diff --git a/drivers/soc/imx/gpc.c b/drivers/soc/imx/gpc.c
> > > index 53f7275..cfb42f5 100644
> > > --- a/drivers/soc/imx/gpc.c
> > > +++ b/drivers/soc/imx/gpc.c
> > > @@ -348,7 +348,7 @@ static int