Re: [Freedreno] [DPU PATCH 11/11] drm/msm: Remove dpu input fences

2018-03-02 Thread Jeykumar Sankaran 

On 2018-02-28 11:19, Sean Paul wrote:

These are already provided by drm atomic core.

In conjunction with the output fences removed earlier, this obsoletes
dpu_fence, and it can be entirely removed as well.

Change-Id: Ida4924a09c455d7a84bfee569bd0d2fb436418de
Signed-off-by: Sean Paul 


Reviewed-by: Jeykumar Sankaran 


---
 drivers/gpu/drm/msm/Makefile  |   1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c  |  84 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_fence.c | 404 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_fence.h | 190 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 104 --
 drivers/gpu/drm/msm/msm_drv.h |   4 +-
 6 files changed, 1 insertion(+), 786 deletions(-)
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_fence.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_fence.h

diff --git a/drivers/gpu/drm/msm/Makefile 
b/drivers/gpu/drm/msm/Makefile

index 2fb9ba11df19..b47ef5267e19 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -55,7 +55,6 @@ msm-y := \
disp/dpu1/dpu_encoder.o \
disp/dpu1/dpu_encoder_phys_cmd.o \
disp/dpu1/dpu_encoder_phys_vid.o \
-   disp/dpu1/dpu_fence.o \
disp/dpu1/dpu_formats.o \
disp/dpu1/dpu_hw_ad4.o \
disp/dpu1/dpu_hw_blk.o \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 2d44989ade7a..8dd986e476bd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -64,16 +64,6 @@ static struct dpu_crtc_custom_events custom_events[] 
=

{
{DRM_EVENT_IDLE_NOTIFY, dpu_crtc_idle_interrupt_handler}
 };

-/* default input fence timeout, in ms */
-#define DPU_CRTC_INPUT_FENCE_TIMEOUT1
-
-/*
- * The default input fence timeout is 2 seconds while max allowed
- * range is 10 seconds. Any value above 10 seconds adds glitches 
beyond

- * tolerance limit.
- */
-#define DPU_CRTC_MAX_INPUT_FENCE_TIMEOUT 1
-
 /* layer mixer index on dpu_crtc */
 #define LEFT_MIXER 0
 #define RIGHT_MIXER 1
@@ -1946,21 +1936,6 @@ static void _dpu_crtc_set_idle_timeout(struct
drm_crtc *crtc, u64 val)
}
 }

-/**
- * _dpu_crtc_set_input_fence_timeout - update ns version of in fence
timeout
- * @cstate: Pointer to dpu crtc state
- */
-static void _dpu_crtc_set_input_fence_timeout(struct dpu_crtc_state
*cstate)
-{
-   if (!cstate) {
-   DPU_ERROR("invalid cstate\n");
-   return;
-   }
-   cstate->input_fence_timeout_ns =
-   dpu_crtc_get_property(cstate,
CRTC_PROP_INPUT_FENCE_TIMEOUT);
-   cstate->input_fence_timeout_ns *= NSEC_PER_MSEC;
-}
-
 /**
  * _dpu_crtc_set_dim_layer_v1 - copy dim layer settings from userspace
  * @cstate:  Pointer to dpu crtc state
@@ -2385,53 +2360,6 @@ static int 
_dpu_crtc_check_dest_scaler_data(struct

drm_crtc *crtc,
return ret;
 }

-/**
- * _dpu_crtc_wait_for_fences - wait for incoming framebuffer sync 
fences

- * @crtc: Pointer to CRTC object
- */
-static void _dpu_crtc_wait_for_fences(struct drm_crtc *crtc)
-{
-   struct drm_plane *plane = NULL;
-   uint32_t wait_ms = 1;
-   ktime_t kt_end, kt_wait;
-   int rc = 0;
-
-   DPU_DEBUG("\n");
-
-   if (!crtc || !crtc->state) {
-   DPU_ERROR("invalid crtc/state %pK\n", crtc);
-   return;
-   }
-
-   /* use monotonic timer to limit total fence wait time */
-   kt_end = ktime_add_ns(ktime_get(),
-   to_dpu_crtc_state(crtc->state)->input_fence_timeout_ns);
-
-   /*
-* Wait for fences sequentially, as all of them need to be
signalled
-* before we can proceed.
-*
-* Limit total wait time to INPUT_FENCE_TIMEOUT, but still call
-* dpu_plane_wait_input_fence with wait_ms == 0 after the timeout
so
-* that each plane can check its fence status and react
appropriately
-* if its fence has timed out. Call input fence wait multiple
times if
-* fence wait is interrupted due to interrupt call.
-*/
-   DPU_ATRACE_BEGIN("plane_wait_input_fence");
-   drm_atomic_crtc_for_each_plane(plane, crtc) {
-   do {
-   kt_wait = ktime_sub(kt_end, ktime_get());
-   if (ktime_compare(kt_wait, ktime_set(0, 0)) >= 0)
-   wait_ms = ktime_to_ms(kt_wait);
-   else
-   wait_ms = 0;
-
-   rc = dpu_plane_wait_input_fence(plane, wait_ms);
-   } while (wait_ms && rc == -ERESTARTSYS);
-   }
-   DPU_ATRACE_END("plane_wait_input_fence");
-}
-
 static void _dpu_crtc_setup_mixer_for_encoder(
struct drm_crtc *crtc,
struct drm_encoder *enc)
@@ -2716,9 +2644,6 @@ static void dpu_crtc_atomic_flush(struct drm_crtc
*crtc,
drm_atomic_crtc_for_each_plane(plane,

Re: [Freedreno] [DPU PATCH 04/11] drm/msm: Move implicit sync fence handling to prepare_fb

2018-03-02 Thread jsanka 

On 2018-02-28 11:18, Sean Paul wrote:
This is another piece that can be moved out of atomic to facilitate 
using

the atomic helpers.

Change-Id: I6dc3c4e5df508942bbc378c73a44e46e511b8469
Signed-off-by: Sean Paul 


Reviewed-by: Jeykumar Sankaran 


---
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c |  8 
 drivers/gpu/drm/msm/msm_atomic.c  | 13 -
 2 files changed, 8 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 834dcc0bfefd..29e72b39fd72 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -2720,6 +2720,8 @@ static int dpu_plane_prepare_fb(struct drm_plane
*plane,
struct dpu_plane_rot_state *new_rstate;
struct dpu_hw_fmt_layout layout;
struct msm_gem_address_space *aspace;
+   struct msm_gem_object *msm_obj;
+   struct dma_fence *fence;
int ret;

if (!new_state->fb)
@@ -2761,6 +2763,12 @@ static int dpu_plane_prepare_fb(struct drm_plane
*plane,
return ret;
}

+   /* To support implicit sync, set a fence on the plane if
appropriate */
+   msm_obj = to_msm_bo(msm_framebuffer_bo(fb, 0));
+   fence = reservation_object_get_excl_rcu(msm_obj->resv);
+   if (fence)
+   drm_atomic_set_fence_for_plane(new_state, fence);
+
return 0;
 }

diff --git a/drivers/gpu/drm/msm/msm_atomic.c
b/drivers/gpu/drm/msm/msm_atomic.c
index eb2ccda5da0f..3a18bd3dc215 100644
--- a/drivers/gpu/drm/msm/msm_atomic.c
+++ b/drivers/gpu/drm/msm/msm_atomic.c
@@ -282,19 +282,6 @@ int msm_atomic_commit(struct drm_device *dev,
for_each_new_crtc_in_state(state, crtc, crtc_state, i)
c->crtc_mask |= drm_crtc_mask(crtc);

-   /*
-* Figure out what fence to wait for:
-*/
-   for_each_oldnew_plane_in_state(state, plane, old_plane_state,
new_plane_state, i) {
-   if ((new_plane_state->fb != old_plane_state->fb) &&
new_plane_state->fb) {
-   struct drm_gem_object *obj =
msm_framebuffer_bo(new_plane_state->fb, 0);
-   struct msm_gem_object *msm_obj = to_msm_bo(obj);
-   struct dma_fence *fence =
reservation_object_get_excl_rcu(msm_obj->resv);
-
-   drm_atomic_set_fence_for_plane(new_plane_state,
fence);
-   }
-   }
-
/*
 * Wait for pending updates on any of the same crtc's and then
 * mark our set of crtc's as busy:

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[Freedreno] [PATCH 1/2] dt-bindings: Document qcom,adreno-gmu

2018-03-02 Thread Jordan Crouse 
Document the device tree bindings for the Adreno GMU device
available on Adreno a6xx targets.

Change-Id: I3cfd5fb35ab0045e39905ff12393006e60f1a124
Signed-off-by: Jordan Crouse 
---
 .../devicetree/bindings/display/msm/gmu.txt| 54 ++
 .../devicetree/bindings/display/msm/gpu.txt| 10 +++-
 2 files changed, 62 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txt

diff --git a/Documentation/devicetree/bindings/display/msm/gmu.txt 
b/Documentation/devicetree/bindings/display/msm/gmu.txt
new file mode 100644
index ..f65bb49fff36
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/gmu.txt
@@ -0,0 +1,54 @@
+Qualcomm adreno/snapdragon GMU (Graphics management unit)
+
+The GMU is a programmable power controller for the GPU. the CPU controls the
+GMU which in turn handles power controls for the GPU.
+
+Required properties:
+- compatible:
+  * "qcom,adreno-gmu"
+- reg: Physical base address and length of the GMU registers.
+- reg-names: Matching names for the register regions
+  * "gmu"
+  * "gmu_pdc"
+- interrupts: The interrupt signals from the GMU.
+- interrupt-names: Matching names for the interrupts
+  * "hfi"
+  * "gmu"
+- clocks: phandles to the device clocks
+- clock-names: Matching names for the clocks
+   * "gmu"
+   * "cxo"
+   * "axi"
+   * "mnoc"
+- power-domains: should be <_gpucc GPU_CX_GDSC>
+- iommus: phandle to the adreno iommu
+- operating-points-v2: phandle to the OPP operating points
+
+Example:
+
+/ {
+   ...
+
+   gmu: gmu@506a000 {
+   compatible="qcom,adreno-gmu";
+
+   reg = <0x506a000 0x3>,
+   <0xb20 0x30>;
+   reg-names = "gmu", "gmu_pdc";
+
+   interrupts = ,
+   ;
+   interrupt-names = "hfi", "gmu";
+
+   clocks = <_gpucc GPU_CC_CX_GMU_CLK>,
+   <_gpucc GPU_CC_CXO_CLK>,
+   <_gcc GCC_DDRSS_GPU_AXI_CLK>,
+   <_gcc GCC_GPU_MEMNOC_GFX_CLK>;
+   clock-names = "gmu", "cxo", "axi", "memnoc";
+
+   power-domains = <_gpucc GPU_CX_GDSC>;
+   iommus = <_smmu 5>;
+
+   i   operating-points-v2 = <_opp_table>;
+   };
+};
diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt 
b/Documentation/devicetree/bindings/display/msm/gpu.txt
index 43fac0fe09bb..0e207498edd3 100644
--- a/Documentation/devicetree/bindings/display/msm/gpu.txt
+++ b/Documentation/devicetree/bindings/display/msm/gpu.txt
@@ -8,12 +8,18 @@ Required properties:
   with the chip-id.
 - reg: Physical base address and length of the controller's registers.
 - interrupts: The interrupt signal from the gpu.
-- clocks: device clocks
+
+Optional properties.
+- clocks: device clocks. Required for a3xx, a4xx and a5xx targets. a6xx and
+  newer with a GMU attached do not have direct clock control from the CPU and
+  do not need to provide clock properties.
   See ../clocks/clock-bindings.txt for details.
-- clock-names: the following clocks are required:
+- clock-names: the following clocks can be provided:
   * "core"
   * "iface"
   * "mem_iface"
+- gmu: For a6xx and newer targets a phandle to the GMU device that will
+  control the power for the GPU
 
 Example:
 
-- 
2.16.1

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[Freedreno] [PATCH 2/2] arm64: dts: sdm845: Support GPU/GMU

2018-03-02 Thread Jordan Crouse 
Add the nodes and other bits to describe the Adreno GPU and GMU
devices.

Change-Id: Ibf4dc0ebb0ac03d8b6b8e65747e142c440e70b0a
Signed-off-by: Jordan Crouse 
---
 arch/arm64/boot/dts/qcom/sdm845.dtsi | 120 +++
 1 file changed, 120 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi 
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 7b5c16eb63b7..cc6d367ee55e 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -312,5 +312,125 @@
status = "disabled";
};
};
+
+   adreno_smmu: arm,smmu-adreno@504 {
+   compatible = "qcom,msm8996-smmu-v2";
+   reg = <0x504 0x1>;
+   #iommu-cells = <1>;
+   #global-interrupts = <2>;
+   interrupts = ,
+,
+,
+,
+,
+,
+,
+,
+,
+;
+   clocks = <_gcc GCC_GPU_MEMNOC_GFX_CLK>,
+<_gcc GCC_GPU_CFG_AHB_CLK>;
+   clock-names = "bus", "iface";
+
+   power-domains = <_gpucc GPU_CX_GDSC>;
+   };
+
+   gpu_opp_table: adreno-opp-table {
+   compatible = "operating-points-v2";
+
+   opp-71000 {
+   opp-hz = /bits/ 64 <71000>;
+   qcom,arc-level = <416>;
+   };
+
+   opp-67500 {
+   opp-hz = /bits/ 64 <67500>;
+   qcom,arc-level = <384>;
+   };
+
+   opp-59600 {
+   opp-hz = /bits/ 64 <59600>;
+   qcom,arc-level = <320>;
+   };
+
+   opp-52000 {
+   opp-hz = /bits/ 64 <52000>;
+   qcom,arc-level = <256>;
+   };
+
+   opp-41400 {
+   opp-hz = /bits/ 64 <41400>;
+   qcom,arc-level = <192>;
+   };
+
+   opp-34200 {
+   opp-hz = /bits/ 64 <34200>;
+   qcom,arc-level = <128>;
+   };
+
+   opp-25700 {
+   opp-hz = /bits/ 64 <25700>;
+   qcom,arc-level = <64>;
+   };
+   };
+
+   gpu@500 {
+   compatible = "qcom,adreno-630.2", "qcom,adreno";
+   #stream-id-cells = <16>;
+
+   reg = <0x500 0x4>;
+   reg-names = "kgsl_3d0_reg_memory";
+
+   /*
+* Look ma, no clocks! The GPU clocks and power are
+* controlled entirely by the GMU
+*/
+
+   interrupts = ;
+   interrupt-names = "kgsl_3d0_irq";
+
+   iommus = <_smmu 0>;
+
+   operating-points-v2 = <_opp_table>;
+
+   gmu = <>;
+   };
+
+   gmu_opp_table: adreno-gmu-opp-table {
+   compatible = "operating-points-v2";
+
+   opp-4 {
+   opp-hz = /bits/ 64 <4>;
+   qcom,arc-level = <128>;
+   };
+
+   opp-2 {
+   opp-hz = /bits/ 64 <2>;
+   qcom,arc-level = <48>;
+   };
+   };
+
+   gmu: gmu@506a000 {
+   compatible="qcom,adreno-gmu";
+
+   reg = <0x506a000 0x3>,
+ <0xb20 0x30>;
+   reg-names = "gmu", "gmu_pdc";
+
+   interrupts = ,
+;
+   interrupt-names = "hfi", "gmu";
+
+   clocks = <_gpucc GPU_CC_CX_GMU_CLK>,
+<_gpucc GPU_CC_CXO_CLK>,
+<_gcc GCC_DDRSS_GPU_AXI_CLK>,
+<_gcc GCC_GPU_MEMNOC_GFX_CLK>;
+   clock-names = "gmu", "cxo", "axi", "memnoc";
+
+   power-domains = <_gpucc

[Freedreno] [PATCH 0/2] arm64: dts: Add sdm845 GPU/GMU and SMMU

2018-03-02 Thread Jordan Crouse 
Building on the sdm845 changes from Rajendra and SMMU changes from Vivek this
is an initial stab at the DT nodes for the sdm845 GPU and GMU (graphics
management unit) which is responsible for the direct power control of the GPU
including the companion arm-smmu-v2 compatible SMMU.

Please refer to https://patchwork.freedesktop.org/series/37428/ for the driver
code.

Jordan Crouse (2):
  dt-bindings: Document qcom,adreno-gmu
  arm64: dts: sdm845: Support GPU/GMU

 .../devicetree/bindings/display/msm/gmu.txt|  54 ++
 .../devicetree/bindings/display/msm/gpu.txt|  10 +-
 arch/arm64/boot/dts/qcom/sdm845.dtsi   | 120 +
 3 files changed, 182 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txt

-- 
2.16.1

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[Freedreno] [PATCH 1/3] PM / OPP: Add dev_pm_opp_get_np()

2018-03-02 Thread Jordan Crouse 
Add a function to return the device node associated with a
specific opp which will facilitate detailing with custom
properties in client drivers.

Signed-off-by: Jordan Crouse 
---
 drivers/opp/of.c   | 20 
 include/linux/pm_opp.h |  6 ++
 2 files changed, 26 insertions(+)

diff --git a/drivers/opp/of.c b/drivers/opp/of.c
index cb716aa2f44b..5695e7c1d091 100644
--- a/drivers/opp/of.c
+++ b/drivers/opp/of.c
@@ -235,6 +235,26 @@ static int opp_parse_supplies(struct dev_pm_opp *opp, 
struct device *dev,
return ret;
 }
 
+/**
+ * dev_pm_opp_get_np() - Get the device tree node corresponding to an opp
+ * @opp:   opp for which the node should be returned for
+ *
+ * If applicable return the device tree node for the corresponding opp so that
+ * the client can decode "custom" target specific properties.
+ *
+ * Return: A pointer to the device tree or NULL if it doesn't exist
+ */
+struct device_node *dev_pm_opp_get_np(struct dev_pm_opp *opp)
+{
+   if (IS_ERR_OR_NULL(opp)) {
+   pr_err("%s: Invalid parameters\n", __func__);
+   return NULL;
+   }
+
+   return opp->np;
+}
+EXPORT_SYMBOL_GPL(dev_pm_opp_get_np);
+
 /**
  * dev_pm_opp_of_remove_table() - Free OPP table entries created from static DT
  *   entries
diff --git a/include/linux/pm_opp.h b/include/linux/pm_opp.h
index 6c2d2e88f066..a38423137db2 100644
--- a/include/linux/pm_opp.h
+++ b/include/linux/pm_opp.h
@@ -308,6 +308,7 @@ int dev_pm_opp_of_cpumask_add_table(const struct cpumask 
*cpumask);
 void dev_pm_opp_of_cpumask_remove_table(const struct cpumask *cpumask);
 int dev_pm_opp_of_get_sharing_cpus(struct device *cpu_dev, struct cpumask 
*cpumask);
 struct device_node *dev_pm_opp_of_get_opp_desc_node(struct device *dev);
+struct device_node *dev_pm_opp_get_np(struct dev_pm_opp *opp);
 #else
 static inline int dev_pm_opp_of_add_table(struct device *dev)
 {
@@ -336,6 +337,11 @@ static inline struct device_node 
*dev_pm_opp_of_get_opp_desc_node(struct device
 {
return NULL;
 }
+
+static inline struct device_node *dev_pm_opp_get_np(struct dev_pm_opp *opp)
+{
+   return NULL;
+}
 #endif
 
 #endif /* __LINUX_OPP_H__ */
-- 
2.16.1

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[Freedreno] [PATCH 2/3] drm/msm: Add generated headers for A6XX

2018-03-02 Thread Jordan Crouse 
From: Sharat Masetty 

Add initial register headers for A6XX targets.

Change-Id: If7b37634aed55c8e05ac26465d628205b6130f09
Signed-off-by: Sharat Masetty 
Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/adreno/a6xx.xml.h | 1600 +
 drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h |  382 +++
 2 files changed, 1982 insertions(+)
 create mode 100644 drivers/gpu/drm/msm/adreno/a6xx.xml.h
 create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h

diff --git a/drivers/gpu/drm/msm/adreno/a6xx.xml.h 
b/drivers/gpu/drm/msm/adreno/a6xx.xml.h
new file mode 100644
index ..17d12414f347
--- /dev/null
+++ b/drivers/gpu/drm/msm/adreno/a6xx.xml.h
@@ -0,0 +1,1600 @@
+#ifndef A6XX_XML
+#define A6XX_XML
+
+/* Autogenerated file, DO NOT EDIT manually!
+
+This file was generated by the rules-ng-ng headergen tool in this git 
repository:
+http://github.com/freedreno/envytools/
+git clone https://github.com/freedreno/envytools.git
+
+The rules-ng-ng source files this header was generated from are:
+- /local3/projects/drm/envytools/rnndb//adreno.xml   (501 
bytes, from 2017-11-20 17:36:01)
+- /local3/projects/drm/envytools/rnndb//freedreno_copyright.xml  (   1572 
bytes, from 2016-10-24 21:12:27)
+- /local3/projects/drm/envytools/rnndb//adreno/a2xx.xml  (  32901 
bytes, from 2016-10-24 21:12:27)
+- /local3/projects/drm/envytools/rnndb//adreno/adreno_common.xml (  11792 
bytes, from 2017-11-17 23:22:22)
+- /local3/projects/drm/envytools/rnndb//adreno/adreno_pm4.xml(  17205 
bytes, from 2017-11-17 23:22:22)
+- /local3/projects/drm/envytools/rnndb//adreno/a3xx.xml  (  83693 
bytes, from 2017-11-17 23:22:22)
+- /local3/projects/drm/envytools/rnndb//adreno/a4xx.xml  ( 110372 
bytes, from 2017-11-17 23:22:22)
+- /local3/projects/drm/envytools/rnndb//adreno/a5xx.xml  (  66793 
bytes, from 2017-11-17 23:22:22)
+- /local3/projects/drm/envytools/rnndb//adreno/a6xx.xml  (  44551 
bytes, from 2017-11-20 19:30:19)
+- /local3/projects/drm/envytools/rnndb//adreno/a6xx_gmu.xml  (  10431 
bytes, from 2017-11-20 17:59:44)
+- /local3/projects/drm/envytools/rnndb//adreno/ocmem.xml (   1773 
bytes, from 2016-10-24 21:12:27)
+
+Copyright (C) 2013-2017 by the following authors:
+- Rob Clark  (robclark)
+- Ilia Mirkin  (imirkin)
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial
+portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+
+enum a6xx_cp_perfcounter_select {
+   PERF_CP_ALWAYS_COUNT = 0,
+};
+
+enum a6xx_event_write {
+   PC_CCU_INVALIDATE_DEPTH = 24,
+   PC_CCU_INVALIDATE_COLOR = 25,
+};
+
+#define A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x0001
+#define A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR  0x0002
+#define A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW   0x0040
+#define A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR0x0080
+#define A6XX_RBBM_INT_0_MASK_CP_SW 0x0100
+#define A6XX_RBBM_INT_0_MASK_CP_HW_ERROR   0x0200
+#define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x0400
+#define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x0800
+#define A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x1000
+#define A6XX_RBBM_INT_0_MASK_CP_IB20x2000
+#define A6XX_RBBM_INT_0_MASK_CP_IB10x4000
+#define A6XX_RBBM_INT_0_MASK_CP_RB 0x8000
+#define A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x0002
+#define A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x0004
+#define A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x0010
+#define A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x0040
+#define A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT

[Freedreno] [v3 PATCH 0/3] Add support for Adreno a6xx

2018-03-02 Thread Jordan Crouse 
a6xx GPU support for drm/msm - follow along here:
https://patchwork.freedesktop.org/series/37428/

Per suggestions from various folks for the associated device tree changes for
the sdm845 GPU (coming immediately after this) add a new opp function to query
the device tree node for a specific opp so that we can parse out platform
specific properties. For the GPU/GMU the device specific property is
qcom,arc-level which is a lookup value for the cmd-db table. Thanks Stephen
Boyd for the suggestion.

[v3: Add dev_pm_opp_np() and use it to get the per-opp rpmh index. Change the
reg-names and interrupt-names to reflect current standards without the "reg" or
"irq" suffix.  Fix additional bugs in the code that constructs the rpmh votes
for the GMU]

[v2: Addressed comments from Lucas Stach, added pm_runtime_get_supplier calls
for accesses to the GMU IOMMU, moved to SPDX headers for the new files]

Jordan Crouse (2):
  PM / OPP: Add dev_pm_opp_get_np()
  drm/msm: Add A6XX device support

Sharat Masetty (1):
  drm/msm: Add generated headers for A6XX

 drivers/gpu/drm/msm/Makefile   |3 +
 drivers/gpu/drm/msm/adreno/a6xx.xml.h  | 1600 
 drivers/gpu/drm/msm/adreno/a6xx_gmu.c  | 1226 +
 drivers/gpu/drm/msm/adreno/a6xx_gmu.h  |  162 +++
 drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h  |  382 +++
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c  |  809 ++
 drivers/gpu/drm/msm/adreno/a6xx_gpu.h  |   60 ++
 drivers/gpu/drm/msm/adreno/a6xx_hfi.c  |  435 
 drivers/gpu/drm/msm/adreno/a6xx_hfi.h  |  127 +++
 drivers/gpu/drm/msm/adreno/adreno_device.c |   12 +
 drivers/gpu/drm/msm/adreno/adreno_gpu.c|2 +-
 drivers/gpu/drm/msm/adreno/adreno_gpu.h|5 +-
 drivers/gpu/drm/msm/msm_gpu.c  |2 +-
 drivers/opp/of.c   |   20 +
 include/linux/pm_opp.h |6 +
 15 files changed, 4848 insertions(+), 3 deletions(-)
 create mode 100644 drivers/gpu/drm/msm/adreno/a6xx.xml.h
 create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_gmu.c
 create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_gmu.h
 create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h
 create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_gpu.c
 create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_gpu.h
 create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_hfi.c
 create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_hfi.h

-- 
2.16.1

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[Freedreno] [PATCH 3/3] drm/msm: Add A6XX device support

2018-03-02 Thread Jordan Crouse 
Add support for the A6XX family of Adreno GPUs. The biggest addition
is the GMU (Graphics Management Unit) which takes over most of the
power management of the GPU itself but in a ironic twist of fate
needs a goodly amount of management itself.  Add support for the
A6XX core code, the GMU and the HFI (hardware firmware interface)
queue that the CPU uses to communicate with the GMU.

Change-Id: Icb2b80fa0d3bf4bdb0b82e9807360c19cb45dae6
Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/Makefile   |3 +
 drivers/gpu/drm/msm/adreno/a6xx_gmu.c  | 1226 
 drivers/gpu/drm/msm/adreno/a6xx_gmu.h  |  162 
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c  |  809 ++
 drivers/gpu/drm/msm/adreno/a6xx_gpu.h  |   60 ++
 drivers/gpu/drm/msm/adreno/a6xx_hfi.c  |  435 ++
 drivers/gpu/drm/msm/adreno/a6xx_hfi.h  |  127 +++
 drivers/gpu/drm/msm/adreno/adreno_device.c |   12 +
 drivers/gpu/drm/msm/adreno/adreno_gpu.c|2 +-
 drivers/gpu/drm/msm/adreno/adreno_gpu.h|5 +-
 drivers/gpu/drm/msm/msm_gpu.c  |2 +-
 11 files changed, 2840 insertions(+), 3 deletions(-)
 create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_gmu.c
 create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_gmu.h
 create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_gpu.c
 create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_gpu.h
 create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_hfi.c
 create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_hfi.h

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index cd40c050b2d7..4affc665c0de 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -10,6 +10,9 @@ msm-y := \
adreno/a5xx_gpu.o \
adreno/a5xx_power.o \
adreno/a5xx_preempt.o \
+   adreno/a6xx_gpu.o \
+   adreno/a6xx_gmu.o \
+   adreno/a6xx_hfi.o \
hdmi/hdmi.o \
hdmi/hdmi_audio.o \
hdmi/hdmi_bridge.o \
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c 
b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
new file mode 100644
index ..3d0a46c49526
--- /dev/null
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -0,0 +1,1226 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. */
+
+#include 
+#include 
+#include 
+#include 
+
+#include "a6xx_gpu.h"
+#include "a6xx_gmu.xml.h"
+
+static irqreturn_t a6xx_gmu_irq(int irq, void *data)
+{
+   struct a6xx_gmu *gmu = data;
+   u32 status;
+
+   status = gmu_read(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS);
+   gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status);
+
+   if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE) {
+   dev_err_ratelimited(gmu->dev, "GMU watchdog expired\n");
+
+   /* Temporary until we can recover safely */
+   BUG();
+   }
+
+   if (status &  A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR)
+   dev_err_ratelimited(gmu->dev, "GMU AHB bus error\n");
+
+   if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR)
+   dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n",
+   gmu_read(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS));
+
+   return IRQ_HANDLED;
+}
+
+static irqreturn_t a6xx_hfi_irq(int irq, void *data)
+{
+   struct a6xx_gmu *gmu = data;
+   u32 status;
+
+   status = gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO);
+   gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, status);
+
+   if (status & A6XX_GMU_GMU2HOST_INTR_INFO_MSGQ)
+   tasklet_schedule(>hfi_tasklet);
+
+   if (status & A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT) {
+   dev_err_ratelimited(gmu->dev, "GMU firmware fault\n");
+
+   /* Temporary until we can recover safely */
+   BUG();
+   }
+
+   return IRQ_HANDLED;
+}
+
+/* Check to see if the GX rail is still powered */
+static bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu)
+{
+   u32 val  = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS);
+
+   return !(val &
+   (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF |
+   A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF));
+}
+
+#define GX_OFF_MASK \
+   (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF | \
+A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF)
+
+static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *gmu)
+{
+   u32 val;
+   int local = gmu->idle_level;
+
+   /* SPTP and IFPC both report as IFPC */
+   if (gmu->idle_level == GMU_IDLE_STATE_SPTP)
+   local = GMU_IDLE_STATE_IFPC;
+
+   val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE);
+
+   if (val == local) {
+   if (gmu->idle_level != GMU_IDLE_STATE_IFPC ||
+   !a6xx_gmu_gx_is_on(gmu))
+   return true;
+   }
+
+   return false;

Re: [Freedreno] [DPU PATCH] drm/mipi: Remove Qualcomm-specific dsi packet header format

2018-03-02 Thread abhinavk 

On 2018-02-23 13:34, abhin...@codeaurora.org wrote:

Alright, found it

https://cgit.freedesktop.org/~seanpaul/dpu-staging/commit/?h=mtp-testing=34906195473f9e04601c49a45e3fedce0132eb7e

Thanks

Abhinav


Reviewed-by: Abhinav Kumar 

On 2018-02-23 07:06, Sean Paul wrote:
On Thu, Feb 22, 2018 at 9:28 PM, Abhinav Kumar  
wrote:
Looks good. Can you point us to the fix done in the dsi-staging 
driver.




All of the downstream changes are in the mtp-testing branch of the
dpu-staging tree. The on-list patches are in the for-next-staging, and
the patches which have been reviewed on list will go to the for-next
branch.

Sean



Thanks

Abhinav

-Original Message-
From: Rob Clark [mailto:robdcl...@gmail.com]
Sent: Thursday, February 22, 2018 11:49 AM
To: Sean Paul 
Cc: freedreno ; linux-arm-msm 
; Kristian H. Kristensen 
; Jeykumar Sankaran ; 
Abhinav Kumar 
Subject: Re: [DPU PATCH] drm/mipi: Remove Qualcomm-specific dsi 
packet header format


On Thu, Feb 22, 2018 at 12:37 PM, Sean Paul  
wrote:

msm/dsi already formats the packet header correctly, so this breaks
every driver except for the downstream dsi-staging driver (which 
I've

submitted a patch for).

Signed-off-by: Sean Paul 


Reviewed-by: Rob Clark 


---
 drivers/gpu/drm/drm_mipi_dsi.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/drm_mipi_dsi.c
b/drivers/gpu/drm/drm_mipi_dsi.c index 688c8a82ba37..4b47226b90d4
100644
--- a/drivers/gpu/drm/drm_mipi_dsi.c
+++ b/drivers/gpu/drm/drm_mipi_dsi.c
@@ -454,7 +454,7 @@ int mipi_dsi_create_packet(struct 
mipi_dsi_packet *packet,

return -EINVAL;

memset(packet, 0, sizeof(*packet));
-   packet->header[2] = ((msg->channel & 0x3) << 6) | (msg->type 
& 0x3f);
+   packet->header[0] = ((msg->channel & 0x3) << 6) | (msg->type 
&

+ 0x3f);

/* TODO: compute ECC if hardware support is not available */

@@ -466,16 +466,16 @@ int mipi_dsi_create_packet(struct 
mipi_dsi_packet *packet,

 * and 2.
 */
if (mipi_dsi_packet_format_is_long(msg->type)) {
-   packet->header[0] = (msg->tx_len >> 0) & 0xff;
-   packet->header[1] = (msg->tx_len >> 8) & 0xff;
+   packet->header[1] = (msg->tx_len >> 0) & 0xff;
+   packet->header[2] = (msg->tx_len >> 8) & 0xff;

packet->payload_length = msg->tx_len;
packet->payload = msg->tx_buf;
} else {
const u8 *tx = msg->tx_buf;

-   packet->header[0] = (msg->tx_len > 0) ? tx[0] : 0;
-   packet->header[1] = (msg->tx_len > 1) ? tx[1] : 0;
+   packet->header[1] = (msg->tx_len > 0) ? tx[0] : 0;
+   packet->header[2] = (msg->tx_len > 1) ? tx[1] : 0;
}

packet->size = sizeof(packet->header) +
packet->payload_length;
--
2.16.1.291.g4437f3f132-goog


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Re: [Freedreno] [DPU PATCH] drm: Remove unused drm_connector fields.

2018-03-02 Thread abhinavk 

On 2018-03-02 12:17, abhin...@codeaurora.org wrote:

On 2018-03-02 12:06, jsa...@codeaurora.org wrote:

On 2018-02-26 08:49, Sean Paul wrote:

They're not used, so let's get rid of them.

Signed-off-by: Sean Paul 


Reviewed-by: Jeykumar Sankaran 

Reviewed-by: Abhinav Kumar 



---
 include/drm/drm_connector.h | 19 ---
 1 file changed, 19 deletions(-)

diff --git a/include/drm/drm_connector.h 
b/include/drm/drm_connector.h

index 9d9d5405ebfd..ed38df4ac204 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -754,15 +754,6 @@ struct drm_cmdline_mode {
  * @audio_latency: audio latency info from ELD, if found
  * @null_edid_counter: track sinks that give us all zeros for the 
EDID

  * @bad_edid_counter: track sinks that give us an EDID with invalid
checksum
- * @pt_scan_info: PT scan info obtained from the VCDB of EDID
- * @it_scan_info: IT scan info obtained from the VCDB of EDID
- * @ce_scan_info: CE scan info obtained from the VCDB of EDID
- * @hdr_eotf: Electro optical transfer function obtained from HDR 
block

- * @hdr_metadata_type_one: Metadata type one obtained from HDR block
- * @hdr_max_luminance: desired max luminance obtained from HDR block
- * @hdr_avg_luminance: desired avg luminance obtained from HDR block
- * @hdr_min_luminance: desired min luminance obtained from HDR block
- * @hdr_supported: does the sink support HDR content
  * @edid_corrupt: indicates whether the last read EDID was corrupt
  * @debugfs_entry: debugfs directory for this connector
  * @has_tile: is this connector connected to a tiled monitor
@@ -943,16 +934,6 @@ struct drm_connector {
int null_edid_counter; /* needed to workaround some HW bugs where
we get all 0s */
unsigned bad_edid_counter;

-   u8 pt_scan_info;
-   u8 it_scan_info;
-   u8 ce_scan_info;
-   u32 hdr_eotf;
-   bool hdr_metadata_type_one;
-   u32 hdr_max_luminance;
-   u32 hdr_avg_luminance;
-   u32 hdr_min_luminance;
-   bool hdr_supported;
-
/* Flag for raw EDID header corruption - used in Displayport
 * compliance testing - * Displayport Link CTS Core 1.2 rev1.1
4.2.2.6
 */

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Re: [Freedreno] [DPU PATCH] drm: Remove unused drm_connector fields.

2018-03-02 Thread abhinavk 

On 2018-03-02 12:06, jsa...@codeaurora.org wrote:

On 2018-02-26 08:49, Sean Paul wrote:

They're not used, so let's get rid of them.

Signed-off-by: Sean Paul 


Reviewed-by: Jeykumar Sankaran 


---
 include/drm/drm_connector.h | 19 ---
 1 file changed, 19 deletions(-)

diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 9d9d5405ebfd..ed38df4ac204 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -754,15 +754,6 @@ struct drm_cmdline_mode {
  * @audio_latency: audio latency info from ELD, if found
  * @null_edid_counter: track sinks that give us all zeros for the 
EDID

  * @bad_edid_counter: track sinks that give us an EDID with invalid
checksum
- * @pt_scan_info: PT scan info obtained from the VCDB of EDID
- * @it_scan_info: IT scan info obtained from the VCDB of EDID
- * @ce_scan_info: CE scan info obtained from the VCDB of EDID
- * @hdr_eotf: Electro optical transfer function obtained from HDR 
block

- * @hdr_metadata_type_one: Metadata type one obtained from HDR block
- * @hdr_max_luminance: desired max luminance obtained from HDR block
- * @hdr_avg_luminance: desired avg luminance obtained from HDR block
- * @hdr_min_luminance: desired min luminance obtained from HDR block
- * @hdr_supported: does the sink support HDR content
  * @edid_corrupt: indicates whether the last read EDID was corrupt
  * @debugfs_entry: debugfs directory for this connector
  * @has_tile: is this connector connected to a tiled monitor
@@ -943,16 +934,6 @@ struct drm_connector {
int null_edid_counter; /* needed to workaround some HW bugs where
we get all 0s */
unsigned bad_edid_counter;

-   u8 pt_scan_info;
-   u8 it_scan_info;
-   u8 ce_scan_info;
-   u32 hdr_eotf;
-   bool hdr_metadata_type_one;
-   u32 hdr_max_luminance;
-   u32 hdr_avg_luminance;
-   u32 hdr_min_luminance;
-   bool hdr_supported;
-
/* Flag for raw EDID header corruption - used in Displayport
 * compliance testing - * Displayport Link CTS Core 1.2 rev1.1
4.2.2.6
 */

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Re: [Freedreno] [DPU PATCH] drm: Remove unused drm_connector fields.

2018-03-02 Thread jsanka 

On 2018-02-26 08:49, Sean Paul wrote:

They're not used, so let's get rid of them.

Signed-off-by: Sean Paul 


Reviewed-by: Jeykumar Sankaran 


---
 include/drm/drm_connector.h | 19 ---
 1 file changed, 19 deletions(-)

diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 9d9d5405ebfd..ed38df4ac204 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -754,15 +754,6 @@ struct drm_cmdline_mode {
  * @audio_latency: audio latency info from ELD, if found
  * @null_edid_counter: track sinks that give us all zeros for the EDID
  * @bad_edid_counter: track sinks that give us an EDID with invalid
checksum
- * @pt_scan_info: PT scan info obtained from the VCDB of EDID
- * @it_scan_info: IT scan info obtained from the VCDB of EDID
- * @ce_scan_info: CE scan info obtained from the VCDB of EDID
- * @hdr_eotf: Electro optical transfer function obtained from HDR 
block

- * @hdr_metadata_type_one: Metadata type one obtained from HDR block
- * @hdr_max_luminance: desired max luminance obtained from HDR block
- * @hdr_avg_luminance: desired avg luminance obtained from HDR block
- * @hdr_min_luminance: desired min luminance obtained from HDR block
- * @hdr_supported: does the sink support HDR content
  * @edid_corrupt: indicates whether the last read EDID was corrupt
  * @debugfs_entry: debugfs directory for this connector
  * @has_tile: is this connector connected to a tiled monitor
@@ -943,16 +934,6 @@ struct drm_connector {
int null_edid_counter; /* needed to workaround some HW bugs where
we get all 0s */
unsigned bad_edid_counter;

-   u8 pt_scan_info;
-   u8 it_scan_info;
-   u8 ce_scan_info;
-   u32 hdr_eotf;
-   bool hdr_metadata_type_one;
-   u32 hdr_max_luminance;
-   u32 hdr_avg_luminance;
-   u32 hdr_min_luminance;
-   bool hdr_supported;
-
/* Flag for raw EDID header corruption - used in Displayport
 * compliance testing - * Displayport Link CTS Core 1.2 rev1.1
4.2.2.6
 */

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Re: [Freedreno] [DPU PATCH] drm/msm: Remove secure fb/plane support from dpu

2018-03-02 Thread jsanka 

On 2018-02-21 13:42, Sean Paul wrote:

We need to have a discussion about how to introduce this in a way that
it can be leveraged by other platforms/userspaces. For now, remove
support since we don't need it yet.

Signed-off-by: Sean Paul 


Reviewed-by: Jeykumar Sankaran 


---
 drivers/gpu/drm/drm_framebuffer.c |  3 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c  | 16 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h  | 43 ---
 .../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c   | 11 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_rot.c|  1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_rot.h|  2 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c   | 30 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h   | 21 +++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c |  3 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h |  1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c   |  8 +---
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h   | 15 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 41 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h |  1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_wb.c| 10 -
 drivers/gpu/drm/msm/msm_drv.h |  3 --
 include/uapi/drm/dpu_drm.h| 42 --
 include/uapi/drm/drm_mode.h   |  1 -
 18 files changed, 9 insertions(+), 243 deletions(-)

diff --git a/drivers/gpu/drm/drm_framebuffer.c
b/drivers/gpu/drm/drm_framebuffer.c
index 8222ff7d3e93..5a13ff29f4f0 100644
--- a/drivers/gpu/drm/drm_framebuffer.c
+++ b/drivers/gpu/drm/drm_framebuffer.c
@@ -268,8 +268,7 @@ drm_internal_framebuffer_create(struct drm_device
*dev,
struct drm_framebuffer *fb;
int ret;

-   if (r->flags & ~(DRM_MODE_FB_INTERLACED | DRM_MODE_FB_MODIFIERS |
-   DRM_MODE_FB_SECURE)) {
+   if (r->flags & ~(DRM_MODE_FB_INTERLACED | DRM_MODE_FB_MODIFIERS))
{
DRM_DEBUG_KMS("bad framebuffer flags 0x%08x\n", r->flags);
return ERR_PTR(-EINVAL);
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index df6cbeb15cf5..3cdf1e3d9d96 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -39,13 +39,6 @@
 #include "dpu_core_perf.h"
 #include "dpu_trace.h"

-/* defines for secure channel call */
-#define SEC_SID_CNT   2
-#define SEC_SID_MASK_00x80881
-#define SEC_SID_MASK_10x80C81
-#define MEM_PROTECT_SD_CTRL_SWITCH 0x18
-#define MDP_DEVICE_ID0x1A
-
 struct dpu_crtc_irq_info {
struct dpu_irq_callback irq;
u32 event;
@@ -3994,10 +3987,6 @@ static void dpu_crtc_install_properties(struct
drm_crtc *crtc,
struct drm_device *dev;
struct dpu_kms_info *info;
struct dpu_kms *dpu_kms;
-   static const struct drm_prop_enum_list e_secure_level[] = {
-   {DPU_DRM_SEC_NON_SEC, "sec_and_non_sec"},
-   {DPU_DRM_SEC_ONLY, "sec_only"},
-   };

DPU_DEBUG("\n");

@@ -4080,11 +4069,6 @@ static void dpu_crtc_install_properties(struct
drm_crtc *crtc,
msm_property_install_volatile_range(_crtc->property_info,
"dpu_drm_roi_v1", 0x0, 0, ~0, 0, CRTC_PROP_ROI_V1);

-   msm_property_install_enum(_crtc->property_info,
"security_level",
-   0x0, 0, e_secure_level,
-   ARRAY_SIZE(e_secure_level),
-   CRTC_PROP_SECURITY_LEVEL);
-
dpu_kms_info_reset(info);

if (catalog->has_dim_layer) {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index 17d21fff3f0a..b63df243be33 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -51,20 +51,14 @@ enum dpu_crtc_client_type {
  * enum dpu_crtc_smmu_state:   smmu state
  * @ATTACHED:   all the context banks are attached.
  * @DETACHED:   all the context banks are detached.
- * @DETACHED_SEC:   secure context bank is detached.
  * @ATTACH_ALL_REQ: transient state of attaching context banks.
  * @DETACH_ALL_REQ: transient state of detaching context banks.
- * @DETACH_SEC_REQ: tranisent state of secure context bank is
detached
- * @ATTACH_SEC_REQ: transient state of attaching secure context bank.
  */
 enum dpu_crtc_smmu_state {
ATTACHED = 0,
DETACHED,
-   DETACHED_SEC,
ATTACH_ALL_REQ,
DETACH_ALL_REQ,
-   DETACH_SEC_REQ,
-   ATTACH_SEC_REQ,
 };

 /**
@@ -621,41 +615,4 @@ void dpu_crtc_res_put(struct drm_crtc_state 
*state,

u32 type, u64 tag);
 void dpu_crtc_get_crtc_roi(struct drm_crtc_state *state,
const struct dpu_rect **crtc_roi);

-/** dpu_crt_get_secure_level - retrieve the secure level from the give
state
- * object, this is used to determine the secure state of the crtc
- * @crtc :

Re: [Freedreno] [PATCH 02/14] iommu/arm-smmu: Add support for TTBR1

2018-03-02 Thread Jordan Crouse 
On Fri, Mar 02, 2018 at 05:57:21PM +, Robin Murphy wrote:
> On 21/02/18 22:59, Jordan Crouse wrote:
> >Allow a SMMU device to opt into allocating a TTBR1 pagetable.
> >
> >The size of the TTBR1 region will be the same as
> >the TTBR0 size with the sign extension bit set on the highest
> >bit in the region unless the upstream size is 49 bits and then
> >the sign-extension bit will be set on the 49th bit.
> 
> Um, isn't the 49th bit still "the highest bit" if the address size
> is 49 bits? ;)

Indeed. :)

> >The map/unmap operations will automatically use the appropriate
> >pagetable based on the specified iova and the existing mask.
> >
> >Signed-off-by: Jordan Crouse 
> >---
> >  drivers/iommu/arm-smmu-regs.h  |   2 -
> >  drivers/iommu/arm-smmu.c   |  22 --
> >  drivers/iommu/io-pgtable-arm.c | 160 
> > -
> >  drivers/iommu/io-pgtable-arm.h |  20 ++
> >  drivers/iommu/io-pgtable.h |  16 -
> >  5 files changed, 192 insertions(+), 28 deletions(-)
> >
> >diff --git a/drivers/iommu/arm-smmu-regs.h b/drivers/iommu/arm-smmu-regs.h
> >index a1226e4ab5f8..0ce85d5b22e9 100644
> >--- a/drivers/iommu/arm-smmu-regs.h
> >+++ b/drivers/iommu/arm-smmu-regs.h
> >@@ -193,8 +193,6 @@ enum arm_smmu_s2cr_privcfg {
> >  #define RESUME_RETRY   (0 << 0)
> >  #define RESUME_TERMINATE   (1 << 0)
> >-#define TTBCR2_SEP_SHIFT15
> >-#define TTBCR2_SEP_UPSTREAM (0x7 << TTBCR2_SEP_SHIFT)
> >  #define TTBCR2_AS  (1 << 4)
> >  #define TTBRn_ASID_SHIFT   48
> >diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
> >index 69e7c60792a8..ebfa59b59622 100644
> >--- a/drivers/iommu/arm-smmu.c
> >+++ b/drivers/iommu/arm-smmu.c
> >@@ -248,6 +248,7 @@ struct arm_smmu_domain {
> > enum arm_smmu_domain_stage  stage;
> > struct mutexinit_mutex; /* Protects smmu pointer */
> > spinlock_t  cb_lock; /* Serialises ATS1* ops and 
> > TLB syncs */
> >+u32 attributes;
> > struct iommu_domain domain;
> >  };
> >@@ -598,7 +599,6 @@ static void arm_smmu_init_context_bank(struct 
> >arm_smmu_domain *smmu_domain,
> > } else {
> > cb->tcr[0] = pgtbl_cfg->arm_lpae_s1_cfg.tcr;
> > cb->tcr[1] = pgtbl_cfg->arm_lpae_s1_cfg.tcr >> 32;
> >-cb->tcr[1] |= TTBCR2_SEP_UPSTREAM;
> > if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64)
> > cb->tcr[1] |= TTBCR2_AS;
> > }
> >@@ -729,6 +729,9 @@ static int arm_smmu_init_domain_context(struct 
> >iommu_domain *domain,
> > enum io_pgtable_fmt fmt;
> > struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
> > struct arm_smmu_cfg *cfg = _domain->cfg;
> >+unsigned int quirks =
> >+smmu_domain->attributes & (1 << DOMAIN_ATTR_ENABLE_TTBR1) ?
> >+IO_PGTABLE_QUIRK_ARM_TTBR1 : 0;
> > mutex_lock(_domain->init_mutex);
> > if (smmu_domain->smmu)
> >@@ -852,7 +855,11 @@ static int arm_smmu_init_domain_context(struct 
> >iommu_domain *domain,
> > else
> > cfg->asid = cfg->cbndx + smmu->cavium_id_base;
> >+if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK)
> >+quirks |= IO_PGTABLE_QUIRK_NO_DMA;
> >+
> > pgtbl_cfg = (struct io_pgtable_cfg) {
> >+.quirks = quirks,
> > .pgsize_bitmap  = smmu->pgsize_bitmap,
> > .ias= ias,
> > .oas= oas,
> >@@ -860,9 +867,6 @@ static int arm_smmu_init_domain_context(struct 
> >iommu_domain *domain,
> > .iommu_dev  = smmu->dev,
> > };
> >-if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK)
> >-pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_NO_DMA;
> >-
> > smmu_domain->smmu = smmu;
> > pgtbl_ops = alloc_io_pgtable_ops(fmt, _cfg, smmu_domain);
> > if (!pgtbl_ops) {
> >@@ -1477,6 +1481,10 @@ static int arm_smmu_domain_get_attr(struct 
> >iommu_domain *domain,
> > case DOMAIN_ATTR_NESTING:
> > *(int *)data = (smmu_domain->stage == ARM_SMMU_DOMAIN_NESTED);
> > return 0;
> >+case DOMAIN_ATTR_ENABLE_TTBR1:
> >+*((int *)data) = !!(smmu_domain->attributes
> >+& (1 << DOMAIN_ATTR_ENABLE_TTBR1));
> >+return 0;
> > default:
> > return -ENODEV;
> > }
> >@@ -1505,6 +1513,12 @@ static int arm_smmu_domain_set_attr(struct 
> >iommu_domain *domain,
> > else
> > smmu_domain->stage = ARM_SMMU_DOMAIN_S1;
> >+break;
> >+case DOMAIN_ATTR_ENABLE_TTBR1:
> >+if (*((int *)data))
> >+smmu_domain->attributes |=
> >+1 << DOMAIN_ATTR_ENABLE_TTBR1;
> >+ret = 0;
> > break;
> > default:
> > ret = -ENODEV;
> >diff --git

Re: [Freedreno] [PATCH 02/14] iommu/arm-smmu: Add support for TTBR1

2018-03-02 Thread Robin Murphy 

On 21/02/18 22:59, Jordan Crouse wrote:

Allow a SMMU device to opt into allocating a TTBR1 pagetable.

The size of the TTBR1 region will be the same as
the TTBR0 size with the sign extension bit set on the highest
bit in the region unless the upstream size is 49 bits and then
the sign-extension bit will be set on the 49th bit.


Um, isn't the 49th bit still "the highest bit" if the address size is 49 
bits? ;)



The map/unmap operations will automatically use the appropriate
pagetable based on the specified iova and the existing mask.

Signed-off-by: Jordan Crouse 
---
  drivers/iommu/arm-smmu-regs.h  |   2 -
  drivers/iommu/arm-smmu.c   |  22 --
  drivers/iommu/io-pgtable-arm.c | 160 -
  drivers/iommu/io-pgtable-arm.h |  20 ++
  drivers/iommu/io-pgtable.h |  16 -
  5 files changed, 192 insertions(+), 28 deletions(-)

diff --git a/drivers/iommu/arm-smmu-regs.h b/drivers/iommu/arm-smmu-regs.h
index a1226e4ab5f8..0ce85d5b22e9 100644
--- a/drivers/iommu/arm-smmu-regs.h
+++ b/drivers/iommu/arm-smmu-regs.h
@@ -193,8 +193,6 @@ enum arm_smmu_s2cr_privcfg {
  #define RESUME_RETRY  (0 << 0)
  #define RESUME_TERMINATE  (1 << 0)
  
-#define TTBCR2_SEP_SHIFT		15

-#define TTBCR2_SEP_UPSTREAM(0x7 << TTBCR2_SEP_SHIFT)
  #define TTBCR2_AS (1 << 4)
  
  #define TTBRn_ASID_SHIFT		48

diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 69e7c60792a8..ebfa59b59622 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -248,6 +248,7 @@ struct arm_smmu_domain {
enum arm_smmu_domain_stage  stage;
struct mutexinit_mutex; /* Protects smmu pointer */
spinlock_t  cb_lock; /* Serialises ATS1* ops and 
TLB syncs */
+   u32 attributes;
struct iommu_domain domain;
  };
  
@@ -598,7 +599,6 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,

} else {
cb->tcr[0] = pgtbl_cfg->arm_lpae_s1_cfg.tcr;
cb->tcr[1] = pgtbl_cfg->arm_lpae_s1_cfg.tcr >> 32;
-   cb->tcr[1] |= TTBCR2_SEP_UPSTREAM;
if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64)
cb->tcr[1] |= TTBCR2_AS;
}
@@ -729,6 +729,9 @@ static int arm_smmu_init_domain_context(struct iommu_domain 
*domain,
enum io_pgtable_fmt fmt;
struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
struct arm_smmu_cfg *cfg = _domain->cfg;
+   unsigned int quirks =
+   smmu_domain->attributes & (1 << DOMAIN_ATTR_ENABLE_TTBR1) ?
+   IO_PGTABLE_QUIRK_ARM_TTBR1 : 0;
  
  	mutex_lock(_domain->init_mutex);

if (smmu_domain->smmu)
@@ -852,7 +855,11 @@ static int arm_smmu_init_domain_context(struct 
iommu_domain *domain,
else
cfg->asid = cfg->cbndx + smmu->cavium_id_base;
  
+	if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK)

+   quirks |= IO_PGTABLE_QUIRK_NO_DMA;
+
pgtbl_cfg = (struct io_pgtable_cfg) {
+   .quirks = quirks,
.pgsize_bitmap  = smmu->pgsize_bitmap,
.ias= ias,
.oas= oas,
@@ -860,9 +867,6 @@ static int arm_smmu_init_domain_context(struct iommu_domain 
*domain,
.iommu_dev  = smmu->dev,
};
  
-	if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK)

-   pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_NO_DMA;
-
smmu_domain->smmu = smmu;
pgtbl_ops = alloc_io_pgtable_ops(fmt, _cfg, smmu_domain);
if (!pgtbl_ops) {
@@ -1477,6 +1481,10 @@ static int arm_smmu_domain_get_attr(struct iommu_domain 
*domain,
case DOMAIN_ATTR_NESTING:
*(int *)data = (smmu_domain->stage == ARM_SMMU_DOMAIN_NESTED);
return 0;
+   case DOMAIN_ATTR_ENABLE_TTBR1:
+   *((int *)data) = !!(smmu_domain->attributes
+   & (1 << DOMAIN_ATTR_ENABLE_TTBR1));
+   return 0;
default:
return -ENODEV;
}
@@ -1505,6 +1513,12 @@ static int arm_smmu_domain_set_attr(struct iommu_domain 
*domain,
else
smmu_domain->stage = ARM_SMMU_DOMAIN_S1;
  
+		break;

+   case DOMAIN_ATTR_ENABLE_TTBR1:
+   if (*((int *)data))
+   smmu_domain->attributes |=
+   1 << DOMAIN_ATTR_ENABLE_TTBR1;
+   ret = 0;
break;
default:
ret = -ENODEV;
diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
index fff0b6ba0a69..1bd0045f2cb7 100644
--- a/drivers/iommu/io-pgtable-arm.c
+++ b/drivers/iommu/io-pgtable-arm.c
@@ -152,7 +152,7 @@ struct arm_lpae_io_pgtable {
unsigned long

Re: [Freedreno] [DPU PATCH v3 2/2] drm/msm: remove partial update support

2018-03-02 Thread Sean Paul 
On Thu, Mar 01, 2018 at 04:52:35PM -0800, Jeykumar Sankaran wrote:
> Implementation of partial update in DPU DRM is heavily
> dependent on custom properties and dsi hooks. Removing the
> support for now. We may need to revisit the support in the
> future.
> 
> changes since v1:
>   - get away with unwanted parameter validation
>   - code style fixes
>   - remove header file definitions for partial update
> 
> changes since v2:
>   - remove compilation flag for DPU_AD4.
> 
> Signed-off-by: Jeykumar Sankaran 

Thanks for the revised patches. I've applied them to both for-next and
mtp-testing staging branches. I had some trouble applying this patch cleanly, I
resolved the conflicts for this one, but  probably a good idea to update your
local branch.

Sean

> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c | 139 +--
>  drivers/gpu/drm/msm/disp/dpu1/dpu_connector.h |   7 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c  | 544 
> +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h  |  18 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c   | 277 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h   |   8 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms_utils.c |  42 --
>  drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c |  13 -
>  drivers/gpu/drm/msm/msm_drv.h |  56 ---
>  9 files changed, 87 insertions(+), 1017 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
> index 57b8627..c5e6c53 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
> @@ -424,8 +424,7 @@ int dpu_connector_pre_kickoff(struct drm_connector 
> *connector)
>  {
>   struct dpu_connector *c_conn;
>   struct dpu_connector_state *c_state;
> - struct msm_display_kickoff_params params;
> - int idx, rc;
> + int idx, rc = 0;
>  
>   if (!connector) {
>   DPU_ERROR("invalid argument\n");
> @@ -462,15 +461,8 @@ int dpu_connector_pre_kickoff(struct drm_connector 
> *connector)
>   }
>   }
>  
> - if (!c_conn->ops.pre_kickoff)
> - return 0;
> -
> - params.rois = _state->rois;
> -
>   DPU_EVT32_VERBOSE(connector->base.id);
>  
> - rc = c_conn->ops.pre_kickoff(connector, c_conn->display, );
> -
>   return rc;
>  }
>  
> @@ -645,122 +637,6 @@ static void dpu_connector_atomic_reset(struct 
> drm_connector *connector)
>   return _state->base;
>  }
>  
> -static int _dpu_connector_roi_v1_check_roi(
> - struct dpu_connector *c_conn,
> - struct drm_clip_rect *roi_conn,
> - const struct msm_roi_caps *caps)
> -{
> - const struct msm_roi_alignment *align = >align;
> - int w = roi_conn->x2 - roi_conn->x1;
> - int h = roi_conn->y2 - roi_conn->y1;
> -
> - if (w <= 0 || h <= 0) {
> - DPU_ERROR_CONN(c_conn, "invalid conn roi w %d h %d\n", w, h);
> - return -EINVAL;
> - }
> -
> - if (w < align->min_width || w % align->width_pix_align) {
> - DPU_ERROR_CONN(c_conn,
> - "invalid conn roi width %d min %d align %d\n",
> - w, align->min_width, align->width_pix_align);
> - return -EINVAL;
> - }
> -
> - if (h < align->min_height || h % align->height_pix_align) {
> - DPU_ERROR_CONN(c_conn,
> - "invalid conn roi height %d min %d align %d\n",
> - h, align->min_height, align->height_pix_align);
> - return -EINVAL;
> - }
> -
> - if (roi_conn->x1 % align->xstart_pix_align) {
> - DPU_ERROR_CONN(c_conn, "invalid conn roi x1 %d align %d\n",
> - roi_conn->x1, align->xstart_pix_align);
> - return -EINVAL;
> - }
> -
> - if (roi_conn->y1 % align->ystart_pix_align) {
> - DPU_ERROR_CONN(c_conn, "invalid conn roi y1 %d align %d\n",
> - roi_conn->y1, align->ystart_pix_align);
> - return -EINVAL;
> - }
> -
> - return 0;
> -}
> -
> -static int _dpu_connector_set_roi_v1(
> - struct dpu_connector *c_conn,
> - struct dpu_connector_state *c_state,
> - void *usr_ptr)
> -{
> - struct dpu_drm_roi_v1 roi_v1;
> - struct msm_display_info display_info;
> - struct msm_roi_caps *caps;
> - int i, rc;
> -
> - if (!c_conn || !c_state) {
> - DPU_ERROR("invalid args\n");
> - return -EINVAL;
> - }
> -
> - rc = dpu_connector_get_info(_conn->base, _info);
> - if (rc) {
> - DPU_ERROR_CONN(c_conn, "display get info error: %d\n", rc);
> - return rc;
> - }
> -
> - caps = _info.roi_caps;
> - if (!caps->enabled) {
> - DPU_ERROR_CONN(c_conn, "display roi capability is disabled\n");
> - return

Re: [Freedreno] [PATCH 04/14] iommu: sva: Add support for pasid allocation

2018-03-02 Thread Jordan Crouse 
On Fri, Mar 02, 2018 at 12:27:58PM +, Jean-Philippe Brucker wrote:
> On 21/02/18 22:59, Jordan Crouse wrote:
> [...]
> > +int iommu_sva_alloc_pasid(struct iommu_domain *domain, struct device *dev)
> > +{
> > +   int ret, pasid;
> > +   struct io_pasid *io_pasid;
> > +
> > +   if (!domain->ops->pasid_alloc || !domain->ops->pasid_free)
> > +   return -ENODEV;
> > +
> > +   io_pasid = kzalloc(sizeof(*io_pasid), GFP_KERNEL);
> > +   if (!io_pasid)
> > +   return -ENOMEM;
> > +
> > +   io_pasid->domain = domain;
> > +   io_pasid->base.type = IO_TYPE_PASID;
> > +
> > +   idr_preload(GFP_KERNEL);
> > +   spin_lock(_sva_lock);
> > +   pasid = idr_alloc_cyclic(_pasid_idr, _pasid->base,
> > +   1, (1 << 31), GFP_ATOMIC);
> 
> To be usable by other IOMMUs, this should restrict the PASID range to what
> the IOMMU and the device support like io_mm_alloc(). In your case 31 bits,
> but with PCI PASID it depends on the PASID capability and the SMMU
> SubstreamID range.
> 
> For this reason I think device drivers should call iommu_sva_device_init()
> once, even for the alloc_pasid() API. For SMMUv2 I guess it will be a NOP,
> but other IOMMUs will allocate PASID tables and enable features in the
> device. In addition, knowing that all users of the API call
> iommu_sva_device_init()/shutdown() could allow us to allocate and enable
> stuff lazily in the future.
> 
> It would also allow a given device driver to use both
> iommu_sva_pasid_alloc() and iommu_sva_bind() at the same time. So that the
> driver can assigns contexts to userspace and still use some of them for
> management.

No problem.

> [...]
> > +int iommu_sva_map(int pasid, unsigned long iova,
> > + phys_addr_t paddr, size_t size, int prot)
> 
> It would be nice to factor iommu_map(), since this logic for map, map_sg
> and unmap should be the same regardless of the PASID argument.
> 
> For example
> - iommu_sva_map(domain, pasid, ...)
> - iommu_map(domain, ...)
> 
> both call
> - __iommu_map(domain, pasid, ...)
> 
> which calls either
> - ops->map(domain, ...)
> - ops->sva_map(domain, pasid, ...)

Agree.  I was kind of annoyed at the code duplication - this would be a good way
to handle it.

> [...]
> > @@ -347,6 +353,15 @@ struct iommu_ops {
> > int (*page_response)(struct iommu_domain *domain, struct device *dev,
> >  struct page_response_msg *msg);
> >  
> > +   int (*pasid_alloc)(struct iommu_domain *domain, struct device *dev,
> > +   int pasid);
> > +   int (*sva_map)(struct iommu_domain *domain, int pasid,
> > +  unsigned long iova, phys_addr_t paddr, size_t size,
> > +  int prot);
> > +   size_t (*sva_unmap)(struct iommu_domain *domain, int pasid,
> > +   unsigned long iova, size_t size);
> > +   void (*pasid_free)(struct iommu_domain *domain, int pasid);
> > +
> 
> Hmm, now IOMMU has the following ops:
> 
> * mm_alloc(): allocates a shared mm structure
> * mm_attach(): writes the entry in the PASID table
> * mm_detach(): removes the entry from the PASID table and invalidates it
> * mm_free(): free shared mm
> * pasid_alloc(): allocates a pasid structure (which I usually call
> "private mm") and write the entry in the PASID table (or call
> install_pasid() for SMMUv2)
> * pasid_free(): remove from the PASID table (or call remove_pasid()) and
> free the pasid structure.
> 
> Splitting mm_alloc and mm_attach is necessary because the io_mm in my case
> can be shared between devices (allocated once, attached multiple times).
> In your case a PASID is private to one device so only one callback is
> needed. However mm_alloc+mm_attach will do roughly the same as
> pasid_alloc, so to reduce redundancy in iommu_ops, maybe we could reuse
> mm_alloc and mm_attach for the private PASID case?

Okay - let me bang on it and see what we can clean up.  Thanks for the review.

Jordan

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Re: [Freedreno] [PATCH 03/14] iommu: Create a base struct for io_mm

2018-03-02 Thread Jordan Crouse 
On Fri, Mar 02, 2018 at 12:25:48PM +, Jean-Philippe Brucker wrote:
> Hi Jordan,
> 
> Thank you for this, SMMUv3 and virtio-iommu need these SVA patches as well.
> 
> On 21/02/18 22:59, Jordan Crouse wrote:
> [...]> diff --git a/include/linux/iommu.h b/include/linux/iommu.h
> > index e2c49e583d8d..e998389cf195 100644
> > --- a/include/linux/iommu.h
> > +++ b/include/linux/iommu.h
> > @@ -110,8 +110,17 @@ struct iommu_domain {
> > struct list_head mm_list;
> >  };
> >  
> > +enum iommu_io_type {
> > +   IO_TYPE_MM,
> > +};
> > +
> > +struct io_base {
> > +   int type;
> > +   int pasid;
> > +};
> 
> "io_base" is a bit vague. I'm bad at naming so my opinion doesn't hold
> much water, but I'd rather this be something like "io_mm_base". When I
> initially toyed with the idea I intended to keep io_mm as parent structure
> and have "private" and "shared" sub-structures. Even if private PASIDs
> don't rely on the kernel mm subsystem, this structure would still
> represent an I/O mm of sorts, with a pgd and pgtable info.

I'm also bad at naming but I don't mind changing it. io_mm_base seems okay to me
unless somebody has a better idea. I also like the terms "private" and
"shared". I'm going to start adopting those where it makes sense.

Jordan
> 
> > +
> >  struct io_mm {
> > -   int pasid;
> > +   struct io_base  base;
> > struct list_headdevices;
> > struct kref kref;
> >  #if defined(CONFIG_MMU_NOTIFIER)
> > 
> 

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Re: [Freedreno] [DPU PATCH 06/11] drm/msm: Remove msm_commit/kthread, use atomic helper commit

2018-03-02 Thread Sean Paul 
On Thu, Mar 01, 2018 at 07:37:10PM -0500, Rob Clark wrote:
> On Thu, Mar 1, 2018 at 3:37 PM,   wrote:
> > On 2018-03-01 07:27, Sean Paul wrote:
> >>
> >> On Wed, Feb 28, 2018 at 08:07:00PM -0800, jsa...@codeaurora.org wrote:
> >>>
> >>> On 2018-02-28 11:19, Sean Paul wrote:
> >>> > Moving further towards switching fully to the the atomic helpers, this
> >>> > patch removes the hand-rolled kthread nonblock commit code and uses
> >>
> >> the
> >>>
> >>> > atomic helpers commit_work model.
> >>> >
> >>> > There's still a lot of copypasta here, but it's still needed to
> >>> > facilitate the swap_state and prepare_fence private functions. These
> >>> > will be sorted out in a follow-on patch.
> >>> >
> >>> > Change-Id: I9fcba27824ba63d3fab96cb2bc194bfa6f3475b7
> >>> > Signed-off-by: Sean Paul 
> >>> > ---
> >>> >  drivers/gpu/drm/msm/msm_atomic.c | 199
> >>
> >> ++-
> >>>
> >>> >  drivers/gpu/drm/msm/msm_drv.c|   1 -
> >>> >  drivers/gpu/drm/msm/msm_drv.h|   4 -
> >>> >  3 files changed, 35 insertions(+), 169 deletions(-)
> >>> >
> >>> > diff --git a/drivers/gpu/drm/msm/msm_atomic.c
> >>> > b/drivers/gpu/drm/msm/msm_atomic.c
> >>> > index 3a18bd3dc215..7e54eb65d096 100644
> >>> > --- a/drivers/gpu/drm/msm/msm_atomic.c
> >>> > +++ b/drivers/gpu/drm/msm/msm_atomic.c
> >>> > @@ -21,51 +21,6 @@
> >>> >  #include "msm_gem.h"
> >>> >  #include "msm_fence.h"
> >>> >
> >>> > -struct msm_commit {
> >>> > - struct drm_device *dev;
> >>> > - struct drm_atomic_state *state;
> >>> > - uint32_t crtc_mask;
> >>> > - bool nonblock;
> >>> > - struct kthread_work commit_work;
> >>> > -};
> >>> > -
> >>> > -/* block until specified crtcs are no longer pending update, and
> >>> > - * atomically mark them as pending update
> >>> > - */
> >>> > -static int start_atomic(struct msm_drm_private *priv, uint32_t
> >>> > crtc_mask)
> >>> > -{
> >>> > - int ret;
> >>> > -
> >>> > - spin_lock(>pending_crtcs_event.lock);
> >>> > - ret = wait_event_interruptible_locked(priv->pending_crtcs_event,
> >>> > - !(priv->pending_crtcs & crtc_mask));
> >>> > - if (ret == 0) {
> >>> > - DBG("start: %08x", crtc_mask);
> >>> > - priv->pending_crtcs |= crtc_mask;
> >>> > - }
> >>> > - spin_unlock(>pending_crtcs_event.lock);
> >>> > -
> >>> > - return ret;
> >>> > -}
> >>> > -
> >>> > -/* clear specified crtcs (no longer pending update)
> >>> > - */
> >>> > -static void end_atomic(struct msm_drm_private *priv, uint32_t
> >>> > crtc_mask)
> >>> > -{
> >>> > - spin_lock(>pending_crtcs_event.lock);
> >>> > - DBG("end: %08x", crtc_mask);
> >>> > - priv->pending_crtcs &= ~crtc_mask;
> >>> > - wake_up_all_locked(>pending_crtcs_event);
> >>> > - spin_unlock(>pending_crtcs_event.lock);
> >>> > -}
> >>> > -
> >>> > -static void commit_destroy(struct msm_commit *c)
> >>> > -{
> >>> > - end_atomic(c->dev->dev_private, c->crtc_mask);
> >>> > - if (c->nonblock)
> >>> > - kfree(c);
> >>> > -}
> >>> > -
> >>> >  static void msm_atomic_wait_for_commit_done(
> >>> >   struct drm_device *dev,
> >>> >   struct drm_atomic_state *old_state)
> >>> > @@ -118,6 +73,10 @@ static void msm_atomic_commit_tail(struct
> >>> > drm_atomic_state *state)
> >>> >
> >>> >   msm_atomic_wait_for_commit_done(dev, state);
> >>> >
> >>> > + drm_atomic_helper_commit_hw_done(state);
> >>> > +
> >>> > + drm_atomic_helper_wait_for_vblanks(dev, state);
> >>> > +
> >>> >   drm_atomic_helper_cleanup_planes(dev, state);
> >>> >
> >>> >   kms->funcs->complete_commit(kms, state);
> >>> > @@ -126,109 +85,25 @@ static void msm_atomic_commit_tail(struct
> >>> > drm_atomic_state *state)
> >>> >  /* The (potentially) asynchronous part of the commit.  At this point
> >>> >   * nothing can fail short of armageddon.
> >>> >   */
> >>> > -static void complete_commit(struct msm_commit *c)
> >>> > +static void commit_tail(struct drm_atomic_state *state)
> >>> >  {
> >>> > - struct drm_atomic_state *state = c->state;
> >>> > - struct drm_device *dev = state->dev;
> >>> > + drm_atomic_helper_wait_for_fences(state->dev, state, false);
> >>> >
> >>> > - drm_atomic_helper_wait_for_fences(dev, state, false);
> >>> > + drm_atomic_helper_wait_for_dependencies(state);
> >>> >
> >>> >   msm_atomic_commit_tail(state);
> >>> >
> >>> > - drm_atomic_state_put(state);
> >>> > -}
> >>> > -
> >>> > -static void _msm_drm_commit_work_cb(struct kthread_work *work)
> >>> > -{
> >>> > - struct msm_commit *commit =  NULL;
> >>> > -
> >>> > - if (!work) {
> >>> > - DRM_ERROR("%s: Invalid commit work data!\n", __func__);
> >>> > - return;
> >>> > - }
> >>> > -
> >>> > - commit = container_of(work, struct msm_commit, commit_work);
> >>> > -
> >>> > - complete_commit(commit);
> >>> > -
> >>> > -

Re: [Freedreno] [PATCH 01/14] iommu: Add DOMAIN_ATTR_ENABLE_TTBR1

2018-03-02 Thread Robin Murphy 

On 21/02/18 22:59, Jordan Crouse wrote:

Add a new domain attribute to enable the TTBR1 pagetable for drivers
and devices that support it.  This will enabled using a TTBR1 (otherwise
known as a "global" or "system" pagetable for devices that support a split
pagetable scheme for switching pagetables quickly and safely.


TTBR1 is very much an Arm VMSA-specific term; if the concept of a split 
address space is useful in general, is it worth trying to frame it in 
general terms? AFAICS other IOMMU drivers could achieve the same effect 
fairly straightforwardly by simply copying the top-level "global" 
entries across whenever they switch "private" tables.


FWIW even for SMMU there could potentially be cases with Arm Ltd. IP 
where the SoC vendor implements a stage-2-only configuration in their 
media subsystem, because they care most about minimising area and 
stage-1-only isn't an option.


Robin.


Signed-off-by: Jordan Crouse 
---
  include/linux/iommu.h | 1 +
  1 file changed, 1 insertion(+)

diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index 641aaf0f1b81..e2c49e583d8d 100644
--- a/include/linux/iommu.h
+++ b/include/linux/iommu.h
@@ -153,6 +153,7 @@ enum iommu_attr {
DOMAIN_ATTR_FSL_PAMU_ENABLE,
DOMAIN_ATTR_FSL_PAMUV1,
DOMAIN_ATTR_NESTING,/* two stages of translation */
+   DOMAIN_ATTR_ENABLE_TTBR1,
DOMAIN_ATTR_MAX,
  };
  


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Re: [Freedreno] [PATCH 11/14] drm/msm: Add support for iommu-sva PASIDs

2018-03-02 Thread Jean-Philippe Brucker 
On 21/02/18 22:59, Jordan Crouse wrote:
[...]> +static int install_pasid_cb(int pasid, u64 ttbr, u32 asid, void *data)
> +{
> + struct pasid_entry *entry = kzalloc(sizeof(*entry), GFP_KERNEL);
> +
> + if (!entry)
> + return -ENOMEM;
> +
> + entry->pasid = pasid;
> + entry->ttbr = ttbr;
> + entry->asid = asid;
> +
> + /* FIXME: Assume that we'll never have a pasid conflict? */

I think a conflict would be a bug on the IOMMU side. Users should not have
to check this. Then again, I have a few WARNs on the SMMUv3 context table
code that uncovered nasty bugs during development.

Thanks,
Jean
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Re: [Freedreno] [PATCH 04/14] iommu: sva: Add support for pasid allocation

2018-03-02 Thread Jean-Philippe Brucker 
On 21/02/18 22:59, Jordan Crouse wrote:
[...]
> +int iommu_sva_alloc_pasid(struct iommu_domain *domain, struct device *dev)
> +{
> + int ret, pasid;
> + struct io_pasid *io_pasid;
> +
> + if (!domain->ops->pasid_alloc || !domain->ops->pasid_free)
> + return -ENODEV;
> +
> + io_pasid = kzalloc(sizeof(*io_pasid), GFP_KERNEL);
> + if (!io_pasid)
> + return -ENOMEM;
> +
> + io_pasid->domain = domain;
> + io_pasid->base.type = IO_TYPE_PASID;
> +
> + idr_preload(GFP_KERNEL);
> + spin_lock(_sva_lock);
> + pasid = idr_alloc_cyclic(_pasid_idr, _pasid->base,
> + 1, (1 << 31), GFP_ATOMIC);

To be usable by other IOMMUs, this should restrict the PASID range to what
the IOMMU and the device support like io_mm_alloc(). In your case 31 bits,
but with PCI PASID it depends on the PASID capability and the SMMU
SubstreamID range.

For this reason I think device drivers should call iommu_sva_device_init()
once, even for the alloc_pasid() API. For SMMUv2 I guess it will be a NOP,
but other IOMMUs will allocate PASID tables and enable features in the
device. In addition, knowing that all users of the API call
iommu_sva_device_init()/shutdown() could allow us to allocate and enable
stuff lazily in the future.

It would also allow a given device driver to use both
iommu_sva_pasid_alloc() and iommu_sva_bind() at the same time. So that the
driver can assigns contexts to userspace and still use some of them for
management.

[...]
> +int iommu_sva_map(int pasid, unsigned long iova,
> +   phys_addr_t paddr, size_t size, int prot)

It would be nice to factor iommu_map(), since this logic for map, map_sg
and unmap should be the same regardless of the PASID argument.

For example
- iommu_sva_map(domain, pasid, ...)
- iommu_map(domain, ...)

both call
- __iommu_map(domain, pasid, ...)

which calls either
- ops->map(domain, ...)
- ops->sva_map(domain, pasid, ...)

[...]
> @@ -347,6 +353,15 @@ struct iommu_ops {
>   int (*page_response)(struct iommu_domain *domain, struct device *dev,
>struct page_response_msg *msg);
>  
> + int (*pasid_alloc)(struct iommu_domain *domain, struct device *dev,
> + int pasid);
> + int (*sva_map)(struct iommu_domain *domain, int pasid,
> +unsigned long iova, phys_addr_t paddr, size_t size,
> +int prot);
> + size_t (*sva_unmap)(struct iommu_domain *domain, int pasid,
> + unsigned long iova, size_t size);
> + void (*pasid_free)(struct iommu_domain *domain, int pasid);
> +

Hmm, now IOMMU has the following ops:

* mm_alloc(): allocates a shared mm structure
* mm_attach(): writes the entry in the PASID table
* mm_detach(): removes the entry from the PASID table and invalidates it
* mm_free(): free shared mm
* pasid_alloc(): allocates a pasid structure (which I usually call
"private mm") and write the entry in the PASID table (or call
install_pasid() for SMMUv2)
* pasid_free(): remove from the PASID table (or call remove_pasid()) and
free the pasid structure.

Splitting mm_alloc and mm_attach is necessary because the io_mm in my case
can be shared between devices (allocated once, attached multiple times).
In your case a PASID is private to one device so only one callback is
needed. However mm_alloc+mm_attach will do roughly the same as
pasid_alloc, so to reduce redundancy in iommu_ops, maybe we could reuse
mm_alloc and mm_attach for the private PASID case?

Thanks,
Jean
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Re: [Freedreno] [PATCH 03/14] iommu: Create a base struct for io_mm

2018-03-02 Thread Jean-Philippe Brucker 
Hi Jordan,

Thank you for this, SMMUv3 and virtio-iommu need these SVA patches as well.

On 21/02/18 22:59, Jordan Crouse wrote:
[...]> diff --git a/include/linux/iommu.h b/include/linux/iommu.h
> index e2c49e583d8d..e998389cf195 100644
> --- a/include/linux/iommu.h
> +++ b/include/linux/iommu.h
> @@ -110,8 +110,17 @@ struct iommu_domain {
>   struct list_head mm_list;
>  };
>  
> +enum iommu_io_type {
> + IO_TYPE_MM,
> +};
> +
> +struct io_base {
> + int type;
> + int pasid;
> +};

"io_base" is a bit vague. I'm bad at naming so my opinion doesn't hold
much water, but I'd rather this be something like "io_mm_base". When I
initially toyed with the idea I intended to keep io_mm as parent structure
and have "private" and "shared" sub-structures. Even if private PASIDs
don't rely on the kernel mm subsystem, this structure would still
represent an I/O mm of sorts, with a pgd and pgtable info.

Thanks,
Jean

> +
>  struct io_mm {
> - int pasid;
> + struct io_base  base;
>   struct list_headdevices;
>   struct kref kref;
>  #if defined(CONFIG_MMU_NOTIFIER)
> 

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[Freedreno] [PATCH] rnndb/adreno: Add more PM4 opcodes

2018-03-02 Thread Sharat Masetty 
Add CP_SECURE_MODE and CP_SET_PSEUDO_REG opcodes needed for A6xx
hardware features.

Signed-off-by: Sharat Masetty 
---
 rnndb/adreno/adreno_pm4.xml | 5 +
 1 file changed, 5 insertions(+)

diff --git a/rnndb/adreno/adreno_pm4.xml b/rnndb/adreno/adreno_pm4.xml
index 3621f07..c1a82da 100644
--- a/rnndb/adreno/adreno_pm4.xml
+++ b/rnndb/adreno/adreno_pm4.xml
@@ -288,6 +288,11 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ 
rules-ng.xsd">



+   
+   Tells CP the current mode of GPU operation
+   
+   Instruct CP to set a few inernal CP registers
+