[Freedreno] [DPU PATCH v3 2/6] drm/msm: remove support for ping pong split topology

2018-05-25 Thread Jeykumar Sankaran 
ping pong split topology was meant for low end soc's which
doesn't have enough layer mixers to support split panels.
Considering how uncommon the topology is for current chipset's and
also to simply the driver programming, striping off the support
for SDM845.

changes in v2:
- none
changes in v3:
- none

Reviewed-by: Sean Paul 
Signed-off-by: Jeykumar Sankaran 
Signed-off-by: Sean Paul 
Signed-off-by: Rajesh Yadav 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c  |   2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   |  19 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 179 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |   5 -
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c   | 110 +
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   |  21 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |   5 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |   2 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c |  33 
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h |  11 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h   |   4 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c |  37 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h |   2 -
 13 files changed, 15 insertions(+), 415 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
index 5f3efe5..a89392e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
@@ -38,8 +38,8 @@
{DPU_RM_TOPOLOGY_SINGLEPIPE,"dpu_singlepipe"},
{DPU_RM_TOPOLOGY_DUALPIPE,  "dpu_dualpipe"},
{DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE,  "dpu_dualpipemerge"},
-   {DPU_RM_TOPOLOGY_PPSPLIT,   "dpu_ppsplit"},
 };
+
 static const struct drm_prop_enum_list e_topology_control[] = {
{DPU_RM_TOPCTL_RESERVE_LOCK,"reserve_lock"},
{DPU_RM_TOPCTL_RESERVE_CLEAR,   "reserve_clear"},
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 24d1582..d571af2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -1914,23 +1914,6 @@ static void _dpu_crtc_setup_mixers(struct drm_crtc *crtc)
mutex_unlock(_crtc->crtc_lock);
 }
 
-static void _dpu_crtc_setup_is_ppsplit(struct drm_crtc_state *state)
-{
-   int i;
-   struct dpu_crtc_state *cstate;
-
-   cstate = to_dpu_crtc_state(state);
-
-   cstate->is_ppsplit = false;
-   for (i = 0; i < cstate->num_connectors; i++) {
-   struct drm_connector *conn = cstate->connectors[i];
-
-   if (dpu_connector_get_topology_name(conn) ==
-   DPU_RM_TOPOLOGY_PPSPLIT)
-   cstate->is_ppsplit = true;
-   }
-}
-
 static void _dpu_crtc_setup_lm_bounds(struct drm_crtc *crtc,
struct drm_crtc_state *state)
 {
@@ -1993,7 +1976,6 @@ static void dpu_crtc_atomic_begin(struct drm_crtc *crtc,
 
if (!dpu_crtc->num_mixers) {
_dpu_crtc_setup_mixers(crtc);
-   _dpu_crtc_setup_is_ppsplit(crtc->state);
_dpu_crtc_setup_lm_bounds(crtc, crtc->state);
}
 
@@ -2899,7 +2881,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
 
mixer_width = dpu_crtc_get_mixer_width(dpu_crtc, cstate, mode);
 
-   _dpu_crtc_setup_is_ppsplit(state);
_dpu_crtc_setup_lm_bounds(crtc, state);
 
 /* get plane state for all drm planes associated with crtc state */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 151889b..d04095b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -545,7 +545,6 @@ void dpu_encoder_helper_split_config(
struct dpu_encoder_virt *dpu_enc;
struct split_pipe_cfg cfg = { 0 };
struct dpu_hw_mdp *hw_mdptop;
-   enum dpu_rm_topology_name topology;
struct msm_display_info *disp_info;
 
if (!phys_enc || !phys_enc->hw_mdptop || !phys_enc->parent) {
@@ -569,8 +568,6 @@ void dpu_encoder_helper_split_config(
if (phys_enc->split_role == ENC_ROLE_SOLO) {
if (hw_mdptop->ops.setup_split_pipe)
hw_mdptop->ops.setup_split_pipe(hw_mdptop, );
-   if (hw_mdptop->ops.setup_pp_split)
-   hw_mdptop->ops.setup_pp_split(hw_mdptop, );
return;
}
 
@@ -582,29 +579,11 @@ void dpu_encoder_helper_split_config(
phys_enc->ops.needs_single_flush(phys_enc))
cfg.split_flush_en = true;
 
-   topology = dpu_connector_get_topology_name(phys_enc->connector);
-   if (topology == DPU_RM_TOPOLOGY_PPSPLIT)
-   cfg.pp_split_slave =

[Freedreno] [DPU PATCH v3 3/6] drm/msm: remove panel autorefresh support for SDM845

2018-05-25 Thread Jeykumar Sankaran 
Remove autorefresh support for smart panels in SDM845 for now.
It needs more discussion to figure out the user space
communication to set preference for the feature.

changes in v2:
- none
changes in v3:
- none

Reviewed-by: Sean Paul 
Signed-off-by: Jeykumar Sankaran 
Signed-off-by: Sean Paul 
Signed-off-by: Rajesh Yadav 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c  |   7 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c|  37 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |  20 --
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c   | 298 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c|  41 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h|  18 --
 6 files changed, 11 insertions(+), 410 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
index a89392e..969919f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
@@ -24,9 +24,6 @@
 
 #define BL_NODE_NAME_SIZE 32
 
-/* Autorefresh will occur after FRAME_CNT frames. Large values are unlikely */
-#define AUTOREFRESH_MAX_FRAME_CNT 6
-
 #define DPU_DEBUG_CONN(c, fmt, ...) DPU_DEBUG("conn%d " fmt,\
(c) ? (c)->base.base.id : -1, ##__VA_ARGS__)
 
@@ -1127,10 +1124,6 @@ struct drm_connector *dpu_connector_init(struct 
drm_device *dev,
CONNECTOR_PROP_AD_BL_SCALE);
 #endif
 
-   msm_property_install_range(_conn->property_info, "autorefresh",
-   0x0, 0, AUTOREFRESH_MAX_FRAME_CNT, 0,
-   CONNECTOR_PROP_AUTOREFRESH);
-
/* enum/bitmask properties */
msm_property_install_enum(_conn->property_info, "topology_name",
DRM_MODE_PROP_IMMUTABLE, 0, e_topology_name,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index d04095b..3854410 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -813,7 +813,6 @@ static void _dpu_encoder_resource_control_helper(struct 
drm_encoder *drm_enc,
 static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
u32 sw_event)
 {
-   bool autorefresh_enabled = false;
unsigned int lp, idle_timeout;
struct dpu_encoder_virt *dpu_enc;
struct msm_drm_private *priv;
@@ -920,13 +919,6 @@ static int dpu_encoder_resource_control(struct drm_encoder 
*drm_enc,
return 0;
}
 
-   /* schedule delayed off work if autorefresh is disabled */
-   if (dpu_enc->cur_master &&
-   dpu_enc->cur_master->ops.is_autorefresh_enabled)
-   autorefresh_enabled =
-   dpu_enc->cur_master->ops.is_autorefresh_enabled(
-   dpu_enc->cur_master);
-
/* set idle timeout based on master connector's lp value */
if (dpu_enc->cur_master)
lp = dpu_connector_get_lp(
@@ -939,13 +931,12 @@ static int dpu_encoder_resource_control(struct 
drm_encoder *drm_enc,
else
idle_timeout = dpu_enc->idle_timeout;
 
-   if (!autorefresh_enabled)
-   kthread_queue_delayed_work(
-   _thread->worker,
-   _enc->delayed_off_work,
-   msecs_to_jiffies(idle_timeout));
+   kthread_queue_delayed_work(
+   _thread->worker,
+   _enc->delayed_off_work,
+   msecs_to_jiffies(idle_timeout));
+
DPU_EVT32(DRMID(drm_enc), sw_event, dpu_enc->rc_state,
-   autorefresh_enabled,
idle_timeout, DPU_EVTLOG_FUNC_CASE2);
DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work scheduled\n",
sw_event);
@@ -1988,7 +1979,6 @@ static void dpu_encoder_vsync_event_handler(struct 
timer_list *t)
struct drm_encoder *drm_enc = _enc->base;
struct msm_drm_private *priv;
struct msm_drm_thread *event_thread;
-   bool autorefresh_enabled = false;
 
if (!drm_enc->dev || !drm_enc->dev->dev_private ||
!drm_enc->crtc) {
@@ -2009,22 +1999,7 @@ static void dpu_encoder_vsync_event_handler(struct 
timer_list *t)
return;
}
 
-   if (dpu_enc->cur_master &&
-   dpu_enc->cur_master->ops.is_autorefresh_enabled)
-   autorefresh_enabled =
-   dpu_enc->cur_master->ops.is_autorefresh_enabled(
-   dpu_enc->cur_master);
-
-   /*
-* Queue work to update

[Freedreno] [DPU PATCH v3 5/6] drm/msm: hook up DPU with upstream DSI

2018-05-25 Thread Jeykumar Sankaran 
Switch DPU from dsi-staging to upstream dsi driver. To make
the switch atomic, this change includes:
- remove dpu connector layers
- clean up dpu connector dependencies in encoder/crtc
- compile out writeback and display port drivers
- compile out dsi-staging driver (separate patch submitted to
  remove the driver)
- adapt upstream device hierarchy

changes in v2:
- remove files not applicable upstream (Sean Paul)
- remove compiled out non-dsi display init (Sean Paul)
- split unrelated changes into separate patch set (Sean Paul)
changes in v3:
- fix compilation warning
- compile out dsi staging

Signed-off-by: Jeykumar Sankaran 
Signed-off-by: Sean Paul 
Signed-off-by: Rajesh Yadav 
---
 drivers/gpu/drm/msm/Makefile   |   22 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c  | 1185 
 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.h  |  555 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   |9 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c|  179 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h|   10 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |8 +-
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   |6 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c|  488 +---
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h|6 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c |   56 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h |   11 +
 drivers/gpu/drm/msm/dpu_dbg.c  |3 -
 drivers/gpu/drm/msm/msm_drv.c  |   47 +-
 drivers/gpu/drm/msm/msm_drv.h  |   39 -
 15 files changed, 159 insertions(+), 2465 deletions(-)
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.h

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index d947f2a..d7558ed 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -1,7 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 ccflags-y := -Idrivers/gpu/drm/msm
 ccflags-y += -Idrivers/gpu/drm/msm/disp/dpu1
-ccflags-y += -Idrivers/gpu/drm/msm/dsi-staging
 ccflags-$(CONFIG_DRM_MSM_DSI) += -Idrivers/gpu/drm/msm/dsi
 
 msm-y := \
@@ -48,7 +47,6 @@ msm-y := \
disp/mdp5/mdp5_plane.o \
disp/mdp5/mdp5_smp.o \
disp/dpu1/dpu_color_processing.o \
-   disp/dpu1/dpu_connector.o \
disp/dpu1/dpu_core_irq.o \
disp/dpu1/dpu_core_perf.o \
disp/dpu1/dpu_crtc.o \
@@ -141,26 +139,6 @@ msm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \
dsi/phy/dsi_phy.o \
disp/mdp5/mdp5_cmd_encoder.o
 
-msm-$(CONFIG_DRM_MSM_DSI_STAGING) += dsi-staging/dsi_phy.o \
-   dsi-staging/dsi_pwr.o \
-   dsi-staging/dsi_phy.o \
-   dsi-staging/dsi_phy_hw_v2_0.o \
-   dsi-staging/dsi_phy_hw_v3_0.o \
-   dsi-staging/dsi_phy_timing_calc.o \
-   dsi-staging/dsi_phy_timing_v2_0.o \
-   dsi-staging/dsi_phy_timing_v3_0.o \
-   dsi-staging/dsi_ctrl_hw_cmn.o \
-   dsi-staging/dsi_ctrl_hw_1_4.o \
-   dsi-staging/dsi_ctrl_hw_2_0.o \
-   dsi-staging/dsi_ctrl_hw_2_2.o \
-   dsi-staging/dsi_ctrl.o \
-   dsi-staging/dsi_catalog.o \
-   dsi-staging/dsi_drm.o \
-   dsi-staging/dsi_display.o \
-   dsi-staging/dsi_panel.o \
-   dsi-staging/dsi_clk_manager.o \
-   dsi-staging/dsi_display_test.o
-
 msm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/phy/dsi_phy_28nm.o
 msm-$(CONFIG_DRM_MSM_DSI_20NM_PHY) += dsi/phy/dsi_phy_20nm.o
 msm-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += dsi/phy/dsi_phy_28nm_8960.o
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
deleted file mode 100644
index 969919f..000
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
+++ /dev/null
@@ -1,1185 +0,0 @@
-/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#define

[Freedreno] [DPU PATCH v3 1/6] drm/msm: remove display stream compression(DSC) support for SM845

2018-05-25 Thread Jeykumar Sankaran 
Upstream DSI driver doesn't support DSC panels yet. Remove
the support for compression from DPU for now.

changes in v2:
- indents and unrelated change clean up (Sean Paul)
- fix compilation dependency in dsi-staging
changes in v3:
- none

Signed-off-by: Jeykumar Sankaran 
Signed-off-by: Sean Paul 
Signed-off-by: Rajesh Yadav 
---
 drivers/gpu/drm/msm/Makefile   |   1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c  |   4 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 476 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h|  14 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |   7 +-
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c   |   1 -
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   |   7 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |  25 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |  16 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 252 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h | 100 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h|  17 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c|  48 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h|  22 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c |  13 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h |   7 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c |  55 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h |   8 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_wb.c |   2 -
 drivers/gpu/drm/msm/dsi-staging/dsi_drm.c  |   7 -
 drivers/gpu/drm/msm/msm_drv.h  |  16 -
 21 files changed, 5 insertions(+), 1093 deletions(-)
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index a458b36..d947f2a 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -64,7 +64,6 @@ msm-y := \
disp/dpu1/dpu_hw_color_processing_v1_7.o \
disp/dpu1/dpu_hw_ctl.o \
disp/dpu1/dpu_hw_ds.o \
-   disp/dpu1/dpu_hw_dsc.o \
disp/dpu1/dpu_hw_dspp.o \
disp/dpu1/dpu_hw_interrupts.o \
disp/dpu1/dpu_hw_intf.o \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
index a57495f..5f3efe5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
@@ -36,12 +36,8 @@
 static const struct drm_prop_enum_list e_topology_name[] = {
{DPU_RM_TOPOLOGY_NONE,  "dpu_none"},
{DPU_RM_TOPOLOGY_SINGLEPIPE,"dpu_singlepipe"},
-   {DPU_RM_TOPOLOGY_SINGLEPIPE_DSC,"dpu_singlepipe_dsc"},
{DPU_RM_TOPOLOGY_DUALPIPE,  "dpu_dualpipe"},
-   {DPU_RM_TOPOLOGY_DUALPIPE_DSC,  "dpu_dualpipe_dsc"},
{DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE,  "dpu_dualpipemerge"},
-   {DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC,  "dpu_dualpipemerge_dsc"},
-   {DPU_RM_TOPOLOGY_DUALPIPE_DSCMERGE, "dpu_dualpipe_dscmerge"},
{DPU_RM_TOPOLOGY_PPSPLIT,   "dpu_ppsplit"},
 };
 static const struct drm_prop_enum_list e_topology_control[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 198c618..151889b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -32,7 +32,6 @@
 #include "dpu_formats.h"
 #include "dpu_encoder_phys.h"
 #include "dpu_power_handle.h"
-#include "dpu_hw_dsc.h"
 #include "dpu_crtc.h"
 #include "dpu_trace.h"
 #include "dpu_core_irq.h"
@@ -152,7 +151,6 @@ enum dpu_enc_rc_states {
  * Only valid after enable. Cleared as disable.
  * @hw_pp  Handle to the pingpong blocks used for the display. No.
  * pingpong blocks can be different than num_phys_encs.
- * @hw_dsc:Array of DSC block handles used for the display.
  * @intfs_swapped  Whether or not the phys_enc interfaces have been swapped
  * for partial update right-only cases, such as pingpong
  * split where virtual pingpong does not generate IRQs
@@ -199,7 +197,6 @@ struct dpu_encoder_virt {
struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
struct dpu_encoder_phys *cur_master;
struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
-   struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
 
bool intfs_swapped;
 
@@ -234,21 +231,6 @@ struct dpu_encoder_virt {
 
 #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
 
-bool dpu_encoder_is_dsc_enabled(struct drm_encoder *drm_enc)
-
-{
-   struct dpu_encoder_virt *dpu_enc;
-   struct msm_compression_info *comp_info;
-
-   if (!drm_enc)
-   return

[Freedreno] [DPU PATCH v3 4/6] drm/msm: strip down custom event ioctl's

2018-05-25 Thread Jeykumar Sankaran 
Remove custom ioctl support in SDM845 which allows
user space to register/unregister for hw events.

changes in v2:
- none
changes in v3:
- none

Reviewed-by: Sean Paul 
Signed-off-by: Jeykumar Sankaran 
Signed-off-by: Sean Paul 
Signed-off-by: Rajesh Yadav 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 218 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h |   1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c  |  31 -
 drivers/gpu/drm/msm/msm_drv.c| 201 
 drivers/gpu/drm/msm/msm_kms.h|   2 -
 5 files changed, 1 insertion(+), 452 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index d571af2..c0e8035 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -39,31 +39,6 @@
 #include "dpu_core_perf.h"
 #include "dpu_trace.h"
 
-struct dpu_crtc_irq_info {
-   struct dpu_irq_callback irq;
-   u32 event;
-   int (*func)(struct drm_crtc *crtc, bool en,
-   struct dpu_irq_callback *irq);
-   struct list_head list;
-};
-
-struct dpu_crtc_custom_events {
-   u32 event;
-   int (*func)(struct drm_crtc *crtc, bool en,
-   struct dpu_irq_callback *irq);
-};
-
-static int dpu_crtc_power_interrupt_handler(struct drm_crtc *crtc_drm,
-   bool en, struct dpu_irq_callback *ad_irq);
-static int dpu_crtc_idle_interrupt_handler(struct drm_crtc *crtc_drm,
-   bool en, struct dpu_irq_callback *idle_irq);
-
-static struct dpu_crtc_custom_events custom_events[] = {
-   {DRM_EVENT_AD_BACKLIGHT, dpu_cp_ad_interrupt},
-   {DRM_EVENT_CRTC_POWER, dpu_crtc_power_interrupt_handler},
-   {DRM_EVENT_IDLE_NOTIFY, dpu_crtc_idle_interrupt_handler}
-};
-
 /* layer mixer index on dpu_crtc */
 #define LEFT_MIXER 0
 #define RIGHT_MIXER 1
@@ -2455,9 +2430,6 @@ static void dpu_crtc_handle_power_event(u32 event_type, 
void *arg)
struct drm_encoder *encoder;
struct dpu_crtc_mixer *m;
u32 i, misr_status;
-   unsigned long flags;
-   struct dpu_crtc_irq_info *node = NULL;
-   int ret = 0;
 
if (!crtc) {
DPU_ERROR("invalid crtc\n");
@@ -2479,17 +2451,6 @@ static void dpu_crtc_handle_power_event(u32 event_type, 
void *arg)
dpu_encoder_virt_restore(encoder);
}
 
-   spin_lock_irqsave(_crtc->spin_lock, flags);
-   list_for_each_entry(node, _crtc->user_event_list, list) {
-   ret = 0;
-   if (node->func)
-   ret = node->func(crtc, true, >irq);
-   if (ret)
-   DPU_ERROR("%s failed to enable event %x\n",
-   dpu_crtc->name, node->event);
-   }
-   spin_unlock_irqrestore(_crtc->spin_lock, flags);
-
dpu_cp_crtc_post_ipc(crtc);
 
for (i = 0; i < dpu_crtc->num_mixers; ++i) {
@@ -2514,18 +2475,6 @@ static void dpu_crtc_handle_power_event(u32 event_type, 
void *arg)
dpu_crtc->misr_data[i];
}
 
-   spin_lock_irqsave(_crtc->spin_lock, flags);
-   node = NULL;
-   list_for_each_entry(node, _crtc->user_event_list, list) {
-   ret = 0;
-   if (node->func)
-   ret = node->func(crtc, false, >irq);
-   if (ret)
-   DPU_ERROR("%s failed to disable event %x\n",
-   dpu_crtc->name, node->event);
-   }
-   spin_unlock_irqrestore(_crtc->spin_lock, flags);
-
dpu_cp_crtc_pre_ipc(crtc);
break;
case DPU_POWER_EVENT_POST_DISABLE:
@@ -2553,8 +2502,6 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
struct drm_display_mode *mode;
struct drm_encoder *encoder;
struct msm_drm_private *priv;
-   unsigned long flags;
-   struct dpu_crtc_irq_info *node = NULL;
struct drm_event event;
u32 power_on;
int ret;
@@ -2614,17 +2561,6 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
atomic_set(_crtc->frame_pending, 0);
}
 
-   spin_lock_irqsave(_crtc->spin_lock, flags);
-   list_for_each_entry(node, _crtc->user_event_list, list) {
-   ret = 0;
-   if (node->func)
-   ret = node->func(crtc, false, >irq);
-   if (ret)
-   DPU_ERROR("%s failed to disable event %x\n",
-   dpu_crtc->name, node->event);
-   }
-   spin_unlock_irqrestore(_crtc->spin_lock,

[Freedreno] [PATCH v2 10/13] drm/msm: Stop updating plane->fb/crtc

2018-05-25 Thread Ville Syrjala 
From: Ville Syrjälä 

We want to get rid of plane->fb/crtc on atomic drivers. Stop setting
them.

v2: Catch a few more cases

Cc: Rob Clark 
Cc: linux-arm-...@vger.kernel.org
Cc: freedreno@lists.freedesktop.org
Signed-off-by: Ville Syrjälä 
Reviewed-by: Maarten Lankhorst  #v1
Reviewed-by: Daniel Vetter 
---
 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c  | 1 -
 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c | 2 --
 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c  | 1 -
 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 2 --
 4 files changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c 
b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
index 20f9e5de5f19..457c29dba4a1 100644
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
@@ -665,7 +665,6 @@ struct drm_crtc *mdp4_crtc_init(struct drm_device *dev,
drm_crtc_init_with_planes(dev, crtc, plane, NULL, _crtc_funcs,
  NULL);
drm_crtc_helper_add(crtc, _crtc_helper_funcs);
-   plane->crtc = crtc;
 
return crtc;
 }
diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c 
b/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
index 7a1ad3af08e3..782b1e27f040 100644
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
@@ -182,8 +182,6 @@ static void mdp4_plane_set_scanout(struct drm_plane *plane,
msm_framebuffer_iova(fb, kms->aspace, 2));
mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP3_BASE(pipe),
msm_framebuffer_iova(fb, kms->aspace, 3));
-
-   plane->fb = fb;
 }
 
 static void mdp4_write_csc_config(struct mdp4_kms *mdp4_kms,
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
index 76b96081916f..efedcac6e641 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
@@ -1198,7 +1198,6 @@ struct drm_crtc *mdp5_crtc_init(struct drm_device *dev,
"unref cursor", unref_cursor_worker);
 
drm_crtc_helper_add(crtc, _crtc_helper_funcs);
-   plane->crtc = crtc;
 
return crtc;
 }
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
index f2361f79fdce..6826aa10f3ac 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
@@ -1043,8 +1043,6 @@ static int mdp5_plane_mode_set(struct drm_plane *plane,
 src_img_w, src_img_h,
 src_x + src_w, src_y, src_w, src_h);
 
-   plane->fb = fb;
-
return ret;
 }
 
-- 
2.16.1

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[Freedreno] [PATCH v2 00/13] drm: Eliminate plane->fb/crtc usage for atomic drivers

2018-05-25 Thread Ville Syrjala 
From: Ville Syrjälä 

Here are again the last (?) bits of eliminating the plane->fb/crtc
usage for atomic drivers. I've pushed everything else (thanks to
everyone who reviewed them). 

Deepak said he'd tested the vmwgfx stuff, so I think it should be
safe to land. Just missing a bit of review...

Cc: Alex Deucher 
Cc: amd-...@lists.freedesktop.org
Cc: "Christian König" 
Cc: Daniel Vetter 
Cc: David Airlie 
Cc: "David (ChunMing) Zhou" 
Cc: Deepak Rawat 
Cc: Eric Anholt 
Cc: freedreno@lists.freedesktop.org
Cc: Gerd Hoffmann 
Cc: Harry Wentland 
Cc: Inki Dae 
Cc: Joonyoung Shim 
Cc: Kyungmin Park 
Cc: linux-arm-...@vger.kernel.org
Cc: Rob Clark 
Cc: Seung-Woo Kim 
Cc: Sinclair Yeh 
Cc: Thomas Hellstrom 
Cc: virtualizat...@lists.linux-foundation.org
Cc: VMware Graphics 

Ville Syrjälä (13):
  drm/vmwgfx: Stop using plane->fb in vmw_kms_atomic_check_modeset()
  drm/vmwgfx: Stop using plane->fb in vmw_kms_helper_dirty()
  drm/vmwgfx: Stop using plane->fb in vmw_kms_update_implicit_fb()
  drm/vmwgfx: Stop updating plane->fb
  drm/vmwgfx: Stop using plane->fb in atomic_enable()
  drm/vmwgfx: Stop messing about with plane->fb/old_fb/crtc
  drm/amdgpu/dc: Stop updating plane->fb
  drm/i915: Stop updating plane->fb/crtc
  drm/exynos: Stop updating plane->crtc
  drm/msm: Stop updating plane->fb/crtc
  drm/virtio: Stop updating plane->crtc
  drm/vc4: Stop updating plane->fb/crtc
  drm: Stop updating plane->crtc/fb/old_fb on atomic drivers

 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  2 -
 drivers/gpu/drm/drm_atomic.c  | 55 +++
 drivers/gpu/drm/drm_atomic_helper.c   | 15 +--
 drivers/gpu/drm/drm_crtc.c|  8 +++-
 drivers/gpu/drm/drm_fb_helper.c   |  7 ---
 drivers/gpu/drm/drm_framebuffer.c |  5 ---
 drivers/gpu/drm/drm_plane.c   | 14 +++---
 drivers/gpu/drm/drm_plane_helper.c|  4 +-
 drivers/gpu/drm/exynos/exynos_drm_plane.c |  2 -
 drivers/gpu/drm/i915/intel_atomic_plane.c | 12 -
 drivers/gpu/drm/i915/intel_display.c  |  7 ++-
 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c |  1 -
 drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c|  2 -
 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c |  1 -
 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c|  2 -
 drivers/gpu/drm/vc4/vc4_crtc.c|  3 --
 drivers/gpu/drm/virtio/virtgpu_display.c  |  2 -
 drivers/gpu/drm/vmwgfx/vmwgfx_fb.c| 24 --
 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c   | 24 +++---
 drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c  |  2 -
 drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c  |  5 +--
 include/drm/drm_atomic.h  |  3 --
 22 files changed, 46 insertions(+), 154 deletions(-)

-- 
2.16.1
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Re: [Freedreno] [PATCH 3/3] drm/msm: re-factor devfreq code

2018-05-25 Thread Jordan Crouse 
On Fri, May 25, 2018 at 04:00:46PM +0530, Sharat Masetty wrote:
> devfreq framework requires the drivers to provide busy time estimations.
> The GPU driver relies on the hardware performance counters for the busy time
> estimations, but different hardware revisions have counters which can be
> sourced from different clocks. So the busy time estimation will be target
> dependent.  Additionally on targets where the clocks are completely controlled
> by the on chip microcontroller, fetching and setting the current GPU frequency
> will be different. This patch aims to embrace these differences by 
> re-factoring
> the devfreq code a bit.
> 
> Signed-off-by: Sharat Masetty 
> ---
>  drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 15 +++
>  drivers/gpu/drm/msm/msm_gpu.c | 23 ++-
>  drivers/gpu/drm/msm/msm_gpu.h |  4 +++-
>  3 files changed, 28 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c 
> b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> index d39400e..a35a840 100644
> --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> @@ -1219,12 +1219,19 @@ static struct msm_ringbuffer *a5xx_active_ring(struct 
> msm_gpu *gpu)
>   return a5xx_gpu->cur_ring;
>  }
>  
> -static int a5xx_gpu_busy(struct msm_gpu *gpu, uint64_t *value)
> +static u64 a5xx_gpu_busy(struct msm_gpu *gpu)
>  {
> - *value = gpu_read64(gpu, REG_A5XX_RBBM_PERFCTR_RBBM_0_LO,
> - REG_A5XX_RBBM_PERFCTR_RBBM_0_HI);
> + u64 busy_cycles, busy_time;
>  
> - return 0;
> + busy_cycles = gpu_read64(gpu, REG_A5XX_RBBM_PERFCTR_RBBM_0_LO,
> + REG_A5XX_RBBM_PERFCTR_RBBM_0_HI);
> +
> + busy_time = (busy_cycles - gpu->devfreq.busy_cycles) /
> + (clk_get_rate(gpu->core_clk) / 100);
> +
> + gpu->devfreq.busy_cycles = busy_cycles;
> +
> + return busy_time;
>  }
>  
>  static const struct adreno_gpu_funcs funcs = {
> diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
> index d8d4fc9..f437ee8 100644
> --- a/drivers/gpu/drm/msm/msm_gpu.c
> +++ b/drivers/gpu/drm/msm/msm_gpu.c
> @@ -40,7 +40,11 @@ static int msm_devfreq_target(struct device *dev, unsigned 
> long *freq,
>   if (IS_ERR(opp))
>   return PTR_ERR(opp);
>  
> - clk_set_rate(gpu->core_clk, *freq);
> + if (gpu->funcs->gpu_set_freq)
> + gpu->funcs->gpu_set_freq(gpu, (u64)*freq);
> + else
> + clk_set_rate(gpu->core_clk, *freq);
> +
>   dev_pm_opp_put(opp);
>  
>   return 0;
> @@ -50,16 +54,14 @@ static int msm_devfreq_get_dev_status(struct device *dev,
>   struct devfreq_dev_status *status)
>  {
>   struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev));
> - u64 cycles;
> - u32 freq = ((u32) status->current_frequency) / 100;
>   ktime_t time;
>  
> - status->current_frequency = (unsigned long) clk_get_rate(gpu->core_clk);
> - gpu->funcs->gpu_busy(gpu, );
> -
> - status->busy_time = ((u32) (cycles - gpu->devfreq.busy_cycles)) / freq;
> + if (gpu->funcs->gpu_get_freq)
> + status->current_frequency = gpu->funcs->gpu_get_freq(gpu);
> + else
> + status->current_frequency = clk_get_rate(gpu->core_clk);
>  
> - gpu->devfreq.busy_cycles = cycles;
> + status->busy_time = gpu->funcs->gpu_busy(gpu);
>  
>   time = ktime_get();
>   status->total_time = ktime_us_delta(time, gpu->devfreq.time);
> @@ -72,7 +74,10 @@ static int msm_devfreq_get_cur_freq(struct device *dev, 
> unsigned long *freq)
>  {
>   struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev));
>  
> - *freq = (unsigned long) clk_get_rate(gpu->core_clk);
> + if (gpu->funcs->gpu_get_freq)
> + *freq = gpu->funcs->gpu_get_freq(gpu);

This will get ugly on a 32 bit build.  I think that as long as the reset of the
subsystem uses unsigned long we might as well too. I can put on my fortune
tellers hat and guess we're probably not going to see a 4GB core running on a 32
bit target in the near future.

>   return 0;
>  }
> diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
> index 1876b81..d3f02e7 100644
> --- a/drivers/gpu/drm/msm/msm_gpu.h
> +++ b/drivers/gpu/drm/msm/msm_gpu.h
> @@ -68,7 +68,9 @@ struct msm_gpu_funcs {
>   /* for generation specific debugfs: */
>   int (*debugfs_init)(struct msm_gpu *gpu, struct drm_minor *minor);
>  #endif
> - int (*gpu_busy)(struct msm_gpu *gpu, uint64_t *value);
> + u64 (*gpu_busy)(struct msm_gpu *gpu);
> + u64 (*gpu_get_freq)(struct msm_gpu *gpu);
> + int (*gpu_set_freq)(struct msm_gpu *gpu, u64 freq);

So go ahead and change both of these to an unsigned long and that should help
the casting.

Jordan

>  };
>  
>  struct msm_gpu {
> -- 
> 1.9.1
> 

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Re: [Freedreno] [PATCH 2/3] drm/msm: move suspend/resume devfreq to their own functions

2018-05-25 Thread Jordan Crouse 
On Fri, May 25, 2018 at 04:00:45PM +0530, Sharat Masetty wrote:
> This is needed for hardware revisions which do not rely on the generic
> suspend, resume handlers for power management.
> 
> Signed-off-by: Sharat Masetty 
> ---
>  drivers/gpu/drm/msm/msm_gpu.c | 26 ++
>  drivers/gpu/drm/msm/msm_gpu.h |  2 ++
>  2 files changed, 20 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
> index d7586f2..d8d4fc9 100644
> --- a/drivers/gpu/drm/msm/msm_gpu.c
> +++ b/drivers/gpu/drm/msm/msm_gpu.c
> @@ -203,6 +203,22 @@ static int disable_axi(struct msm_gpu *gpu)
>   return 0;
>  }
>  
> +void msm_gpu_resume_devfreq(struct msm_gpu *gpu)
> +{
> + if (gpu->devfreq.devfreq) {
> + gpu->devfreq.busy_cycles = 0;
> + gpu->devfreq.time = ktime_get();
> +
> + devfreq_resume_device(gpu->devfreq.devfreq);
> + }

I just looked, we don't need the if() check - devfreq_resume_device should be
safe.  Yeah, we're doing an extra ktime_get() but its not the end of the world.

> +}
> +
> +void msm_gpu_suspend_devfreq(struct msm_gpu *gpu)
> +{
> + if (gpu->devfreq.devfreq)
> + devfreq_suspend_device(gpu->devfreq.devfreq);

We don't need the if check here either.

> +}
> +
>  int msm_gpu_pm_resume(struct msm_gpu *gpu)
>  {
>   int ret;
> @@ -221,12 +237,7 @@ int msm_gpu_pm_resume(struct msm_gpu *gpu)
>   if (ret)
>   return ret;
>  
> - if (gpu->devfreq.devfreq) {
> - gpu->devfreq.busy_cycles = 0;
> - gpu->devfreq.time = ktime_get();
> -
> - devfreq_resume_device(gpu->devfreq.devfreq);
> - }
> + msm_gpu_resume_devfreq(gpu);
>  
>   gpu->needs_hw_init = true;
>  
> @@ -239,8 +250,7 @@ int msm_gpu_pm_suspend(struct msm_gpu *gpu)
>  
>   DBG("%s", gpu->name);
>  
> - if (gpu->devfreq.devfreq)
> - devfreq_suspend_device(gpu->devfreq.devfreq);
> + msm_gpu_suspend_devfreq(gpu);
>  
>   ret = disable_axi(gpu);
>   if (ret)
> diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
> index b824117..1876b81 100644
> --- a/drivers/gpu/drm/msm/msm_gpu.h
> +++ b/drivers/gpu/drm/msm/msm_gpu.h
> @@ -226,6 +226,8 @@ static inline void gpu_write64(struct msm_gpu *gpu, u32 
> lo, u32 hi, u64 val)
>  
>  int msm_gpu_pm_suspend(struct msm_gpu *gpu);
>  int msm_gpu_pm_resume(struct msm_gpu *gpu);
> +void msm_gpu_resume_devfreq(struct msm_gpu *gpu);
> +void msm_gpu_suspend_devfreq(struct msm_gpu *gpu);
>  
>  int msm_gpu_hw_init(struct msm_gpu *gpu);
>  
> -- 
> 1.9.1
> 

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Re: [Freedreno] [PATCH 1/3] drm/msm: suspend devfreq on init

2018-05-25 Thread Jordan Crouse 
On Fri, May 25, 2018 at 04:00:44PM +0530, Sharat Masetty wrote:
> Devfreq turns on and starts recommending power level as soon as it is
> initialized. The GPU is still not powered on by the time the devfreq
> init happens and this leads to problems on GPU's where register access
> is needed to get/set power levels. So we start suspended and only restart
> devfreq when GPU is powered on.
> 
> Signed-off-by: Sharat Masetty 

Reviewed-by: Jordan Crouse 
> ---
>  drivers/gpu/drm/msm/msm_gpu.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
> index 1c09acf..d7586f2 100644
> --- a/drivers/gpu/drm/msm/msm_gpu.c
> +++ b/drivers/gpu/drm/msm/msm_gpu.c
> @@ -104,6 +104,8 @@ static void msm_devfreq_init(struct msm_gpu *gpu)
>   dev_err(>pdev->dev, "Couldn't initialize GPU devfreq\n");
>   gpu->devfreq.devfreq = NULL;
>   }
> +
> + devfreq_suspend_device(gpu->devfreq.devfreq);
>  }
>  
>  static int enable_pwrrail(struct msm_gpu *gpu)
> -- 
> 1.9.1
> 

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[Freedreno] [PATCH 2/3] drm/msm: move suspend/resume devfreq to their own functions

2018-05-25 Thread Sharat Masetty 
This is needed for hardware revisions which do not rely on the generic
suspend, resume handlers for power management.

Signed-off-by: Sharat Masetty 
---
 drivers/gpu/drm/msm/msm_gpu.c | 26 ++
 drivers/gpu/drm/msm/msm_gpu.h |  2 ++
 2 files changed, 20 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index d7586f2..d8d4fc9 100644
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -203,6 +203,22 @@ static int disable_axi(struct msm_gpu *gpu)
return 0;
 }
 
+void msm_gpu_resume_devfreq(struct msm_gpu *gpu)
+{
+   if (gpu->devfreq.devfreq) {
+   gpu->devfreq.busy_cycles = 0;
+   gpu->devfreq.time = ktime_get();
+
+   devfreq_resume_device(gpu->devfreq.devfreq);
+   }
+}
+
+void msm_gpu_suspend_devfreq(struct msm_gpu *gpu)
+{
+   if (gpu->devfreq.devfreq)
+   devfreq_suspend_device(gpu->devfreq.devfreq);
+}
+
 int msm_gpu_pm_resume(struct msm_gpu *gpu)
 {
int ret;
@@ -221,12 +237,7 @@ int msm_gpu_pm_resume(struct msm_gpu *gpu)
if (ret)
return ret;
 
-   if (gpu->devfreq.devfreq) {
-   gpu->devfreq.busy_cycles = 0;
-   gpu->devfreq.time = ktime_get();
-
-   devfreq_resume_device(gpu->devfreq.devfreq);
-   }
+   msm_gpu_resume_devfreq(gpu);
 
gpu->needs_hw_init = true;
 
@@ -239,8 +250,7 @@ int msm_gpu_pm_suspend(struct msm_gpu *gpu)
 
DBG("%s", gpu->name);
 
-   if (gpu->devfreq.devfreq)
-   devfreq_suspend_device(gpu->devfreq.devfreq);
+   msm_gpu_suspend_devfreq(gpu);
 
ret = disable_axi(gpu);
if (ret)
diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
index b824117..1876b81 100644
--- a/drivers/gpu/drm/msm/msm_gpu.h
+++ b/drivers/gpu/drm/msm/msm_gpu.h
@@ -226,6 +226,8 @@ static inline void gpu_write64(struct msm_gpu *gpu, u32 lo, 
u32 hi, u64 val)
 
 int msm_gpu_pm_suspend(struct msm_gpu *gpu);
 int msm_gpu_pm_resume(struct msm_gpu *gpu);
+void msm_gpu_resume_devfreq(struct msm_gpu *gpu);
+void msm_gpu_suspend_devfreq(struct msm_gpu *gpu);
 
 int msm_gpu_hw_init(struct msm_gpu *gpu);
 
-- 
1.9.1

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[Freedreno] [PATCH 3/3] drm/msm: re-factor devfreq code

2018-05-25 Thread Sharat Masetty 
devfreq framework requires the drivers to provide busy time estimations.
The GPU driver relies on the hardware performance counters for the busy time
estimations, but different hardware revisions have counters which can be
sourced from different clocks. So the busy time estimation will be target
dependent.  Additionally on targets where the clocks are completely controlled
by the on chip microcontroller, fetching and setting the current GPU frequency
will be different. This patch aims to embrace these differences by re-factoring
the devfreq code a bit.

Signed-off-by: Sharat Masetty 
---
 drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 15 +++
 drivers/gpu/drm/msm/msm_gpu.c | 23 ++-
 drivers/gpu/drm/msm/msm_gpu.h |  4 +++-
 3 files changed, 28 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index d39400e..a35a840 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -1219,12 +1219,19 @@ static struct msm_ringbuffer *a5xx_active_ring(struct 
msm_gpu *gpu)
return a5xx_gpu->cur_ring;
 }
 
-static int a5xx_gpu_busy(struct msm_gpu *gpu, uint64_t *value)
+static u64 a5xx_gpu_busy(struct msm_gpu *gpu)
 {
-   *value = gpu_read64(gpu, REG_A5XX_RBBM_PERFCTR_RBBM_0_LO,
-   REG_A5XX_RBBM_PERFCTR_RBBM_0_HI);
+   u64 busy_cycles, busy_time;
 
-   return 0;
+   busy_cycles = gpu_read64(gpu, REG_A5XX_RBBM_PERFCTR_RBBM_0_LO,
+   REG_A5XX_RBBM_PERFCTR_RBBM_0_HI);
+
+   busy_time = (busy_cycles - gpu->devfreq.busy_cycles) /
+   (clk_get_rate(gpu->core_clk) / 100);
+
+   gpu->devfreq.busy_cycles = busy_cycles;
+
+   return busy_time;
 }
 
 static const struct adreno_gpu_funcs funcs = {
diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index d8d4fc9..f437ee8 100644
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -40,7 +40,11 @@ static int msm_devfreq_target(struct device *dev, unsigned 
long *freq,
if (IS_ERR(opp))
return PTR_ERR(opp);
 
-   clk_set_rate(gpu->core_clk, *freq);
+   if (gpu->funcs->gpu_set_freq)
+   gpu->funcs->gpu_set_freq(gpu, (u64)*freq);
+   else
+   clk_set_rate(gpu->core_clk, *freq);
+
dev_pm_opp_put(opp);
 
return 0;
@@ -50,16 +54,14 @@ static int msm_devfreq_get_dev_status(struct device *dev,
struct devfreq_dev_status *status)
 {
struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev));
-   u64 cycles;
-   u32 freq = ((u32) status->current_frequency) / 100;
ktime_t time;
 
-   status->current_frequency = (unsigned long) clk_get_rate(gpu->core_clk);
-   gpu->funcs->gpu_busy(gpu, );
-
-   status->busy_time = ((u32) (cycles - gpu->devfreq.busy_cycles)) / freq;
+   if (gpu->funcs->gpu_get_freq)
+   status->current_frequency = gpu->funcs->gpu_get_freq(gpu);
+   else
+   status->current_frequency = clk_get_rate(gpu->core_clk);
 
-   gpu->devfreq.busy_cycles = cycles;
+   status->busy_time = gpu->funcs->gpu_busy(gpu);
 
time = ktime_get();
status->total_time = ktime_us_delta(time, gpu->devfreq.time);
@@ -72,7 +74,10 @@ static int msm_devfreq_get_cur_freq(struct device *dev, 
unsigned long *freq)
 {
struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev));
 
-   *freq = (unsigned long) clk_get_rate(gpu->core_clk);
+   if (gpu->funcs->gpu_get_freq)
+   *freq = gpu->funcs->gpu_get_freq(gpu);
+   else
+   *freq = clk_get_rate(gpu->core_clk);
 
return 0;
 }
diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
index 1876b81..d3f02e7 100644
--- a/drivers/gpu/drm/msm/msm_gpu.h
+++ b/drivers/gpu/drm/msm/msm_gpu.h
@@ -68,7 +68,9 @@ struct msm_gpu_funcs {
/* for generation specific debugfs: */
int (*debugfs_init)(struct msm_gpu *gpu, struct drm_minor *minor);
 #endif
-   int (*gpu_busy)(struct msm_gpu *gpu, uint64_t *value);
+   u64 (*gpu_busy)(struct msm_gpu *gpu);
+   u64 (*gpu_get_freq)(struct msm_gpu *gpu);
+   int (*gpu_set_freq)(struct msm_gpu *gpu, u64 freq);
 };
 
 struct msm_gpu {
-- 
1.9.1

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[Freedreno] [PATCH 0/3] drm/msm: re-factor devfreq common code

2018-05-25 Thread Sharat Masetty 
This series re-factors the devfreq code a bit in preparation for the upcoming
A6x related devfreq changes. The code applies cleanly on 4.17 and has been
verified on DB820C.

Sharat Masetty (3):
  drm/msm: suspend devfreq on init
  drm/msm: move suspend/resume devfreq to their own functions
  drm/msm: re-factor devfreq code

 drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 15 ---
 drivers/gpu/drm/msm/msm_gpu.c | 51 +++
 drivers/gpu/drm/msm/msm_gpu.h |  6 -
 3 files changed, 50 insertions(+), 22 deletions(-)

--
1.9.1
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[Freedreno] [PATCH 1/3] drm/msm: suspend devfreq on init

2018-05-25 Thread Sharat Masetty 
Devfreq turns on and starts recommending power level as soon as it is
initialized. The GPU is still not powered on by the time the devfreq
init happens and this leads to problems on GPU's where register access
is needed to get/set power levels. So we start suspended and only restart
devfreq when GPU is powered on.

Signed-off-by: Sharat Masetty 
---
 drivers/gpu/drm/msm/msm_gpu.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index 1c09acf..d7586f2 100644
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -104,6 +104,8 @@ static void msm_devfreq_init(struct msm_gpu *gpu)
dev_err(>pdev->dev, "Couldn't initialize GPU devfreq\n");
gpu->devfreq.devfreq = NULL;
}
+
+   devfreq_suspend_device(gpu->devfreq.devfreq);
 }
 
 static int enable_pwrrail(struct msm_gpu *gpu)
-- 
1.9.1

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Re: [Freedreno] [PATCH] gpu: Consistently use octal not symbolic permissions

2018-05-25 Thread Christian König 

Well I think we rejected that multiple times now.

At least I find the symbolic permissions easier to read and I absolutely 
don't see any reason why we should only use one form.


Christian.

Am 24.05.2018 um 22:22 schrieb Joe Perches:

There is currently a mixture of octal and symbolic permissions uses
in files in drivers/gpu/drm and one file in drivers/gpu.

There are ~270 existing octal uses and ~115 S_ uses.

Convert all the S_ symbolic permissions to their octal equivalents
as using octal and not symbolic permissions is preferred by many as more
readable.

see: https://lkml.org/lkml/2016/8/2/1945

Done with automated conversion via:
$ ./scripts/checkpatch.pl -f --types=SYMBOLIC_PERMS --fix-inplace 

Miscellanea:

o Wrapped modified multi-line calls to a single line where appropriate
o Realign modified multi-line calls to open parenthesis
o drivers/gpu/drm/msm/adreno/a5xx_debugfs.c has a world-writeable
   debug permission for "reset" - perhaps that should be modified

Signed-off-by: Joe Perches 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c|  2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 98 +++---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c   |  3 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|  9 +-
  drivers/gpu/drm/armada/armada_debugfs.c|  4 +-
  drivers/gpu/drm/drm_debugfs.c  |  6 +-
  drivers/gpu/drm/drm_debugfs_crc.c  |  4 +-
  drivers/gpu/drm/drm_sysfs.c|  2 +-
  drivers/gpu/drm/i915/gvt/firmware.c|  2 +-
  drivers/gpu/drm/i915/i915_debugfs.c|  8 +-
  drivers/gpu/drm/i915/i915_perf.c   |  2 +-
  drivers/gpu/drm/i915/i915_sysfs.c  | 22 ++---
  drivers/gpu/drm/i915/intel_pipe_crc.c  |  2 +-
  drivers/gpu/drm/msm/adreno/a5xx_debugfs.c  |  5 +-
  drivers/gpu/drm/msm/msm_perf.c |  4 +-
  drivers/gpu/drm/msm/msm_rd.c   |  4 +-
  drivers/gpu/drm/nouveau/nouveau_debugfs.c  |  2 +-
  drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c| 11 ++-
  .../drm/omapdrm/displays/panel-sony-acx565akm.c|  6 +-
  .../drm/omapdrm/displays/panel-tpo-td043mtea1.c| 10 +--
  drivers/gpu/drm/radeon/radeon_pm.c | 26 +++---
  drivers/gpu/drm/radeon/radeon_ttm.c|  4 +-
  drivers/gpu/drm/sti/sti_drv.c  |  2 +-
  drivers/gpu/drm/tinydrm/mipi-dbi.c |  4 +-
  drivers/gpu/drm/ttm/ttm_bo.c   |  2 +-
  drivers/gpu/drm/ttm/ttm_memory.c   | 12 +--
  drivers/gpu/drm/ttm/ttm_page_alloc.c   |  6 +-
  drivers/gpu/drm/ttm/ttm_page_alloc_dma.c   |  6 +-
  drivers/gpu/drm/udl/udl_fb.c   |  4 +-
  drivers/gpu/host1x/debug.c | 12 +--
  30 files changed, 138 insertions(+), 146 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index f5fb93795a69..7b29febff511 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -830,7 +830,7 @@ int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
  
  	for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {

ent = debugfs_create_file(debugfs_regs_names[i],
- S_IFREG | S_IRUGO, root,
+ S_IFREG | 0444, root,
  adev, debugfs_regs[i]);
if (IS_ERR(ent)) {
for (j = 0; j < i; j++) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index b455da487782..fa55d7e9e784 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -905,39 +905,39 @@ static ssize_t amdgpu_set_pp_power_profile_mode(struct 
device *dev,
return -EINVAL;
  }
  
-static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);

-static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
+static DEVICE_ATTR(power_dpm_state, 0644, amdgpu_get_dpm_state, 
amdgpu_set_dpm_state);
+static DEVICE_ATTR(power_dpm_force_performance_level, 0644,
   amdgpu_get_dpm_forced_performance_level,
   amdgpu_set_dpm_forced_performance_level);
-static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
-static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
-static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
-   amdgpu_get_pp_force_state,
-   amdgpu_set_pp_force_state);
-static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
-   amdgpu_get_pp_table,
-   amdgpu_set_pp_table);
-static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
-   amdgpu_get_pp_dpm_sclk,
-

Re: [Freedreno] [PATCH] gpu: Consistently use octal not symbolic permissions

2018-05-25 Thread Jani Nikula 
On Thu, 24 May 2018, Joe Perches  wrote:
> On Fri, 2018-05-25 at 09:41 +0300, Jani Nikula wrote:
>> On Thu, 24 May 2018, Joe Perches  wrote:
>> > There is currently a mixture of octal and symbolic permissions uses
>> > in files in drivers/gpu/drm and one file in drivers/gpu.
>> > 
>> > There are ~270 existing octal uses and ~115 S_ uses.
>> > 
>> > Convert all the S_ symbolic permissions to their octal equivalents
>> > as using octal and not symbolic permissions is preferred by many as more
>> > readable.
>> > 
>> > see: https://lkml.org/lkml/2016/8/2/1945
>> > 
>> > Done with automated conversion via:
>> > $ ./scripts/checkpatch.pl -f --types=SYMBOLIC_PERMS --fix-inplace 
>> > 
>> > 
>> > Miscellanea:
>> > 
>> > o Wrapped modified multi-line calls to a single line where appropriate
>> > o Realign modified multi-line calls to open parenthesis
>> > o drivers/gpu/drm/msm/adreno/a5xx_debugfs.c has a world-writeable
>> >   debug permission for "reset" - perhaps that should be modified
>> > Signed-off-by: Joe Perches 
>> > ---
>> >  drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c|  2 +-
>> >  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 98 
>> > +++---
>> >  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c   |  3 +-
>> >  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|  9 +-
>> >  drivers/gpu/drm/armada/armada_debugfs.c|  4 +-
>> >  drivers/gpu/drm/drm_debugfs.c  |  6 +-
>> >  drivers/gpu/drm/drm_debugfs_crc.c  |  4 +-
>> >  drivers/gpu/drm/drm_sysfs.c|  2 +-
>> >  drivers/gpu/drm/i915/gvt/firmware.c|  2 +-
>> >  drivers/gpu/drm/i915/i915_debugfs.c|  8 +-
>> >  drivers/gpu/drm/i915/i915_perf.c   |  2 +-
>> >  drivers/gpu/drm/i915/i915_sysfs.c  | 22 ++---
>> >  drivers/gpu/drm/i915/intel_pipe_crc.c  |  2 +-
>> 
>> Please send at least i915 changes separately. There's zero reason to
>> make our lives harder for this change.
>
> The idea is to avoid unnecessary multiple patches for
> individual trees.

You're changing like a dozen trees. And apparently maintainers of
different trees also have different opinions on whether this is a good
idea or not. Mass changes like this go nowhere, and if they do, will
cause unnecessary conflicts that could have been trivially avoided.

BR,
Jani.

> But you could do that via something like:
>
> $ git am --include='drivers/gpu/drm/i915/*' 
>
> cheers, Joe
>

-- 
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Re: [Freedreno] [PATCH] gpu: Consistently use octal not symbolic permissions

2018-05-25 Thread Joe Perches 
On Fri, 2018-05-25 at 09:41 +0300, Jani Nikula wrote:
> On Thu, 24 May 2018, Joe Perches  wrote:
> > There is currently a mixture of octal and symbolic permissions uses
> > in files in drivers/gpu/drm and one file in drivers/gpu.
> > 
> > There are ~270 existing octal uses and ~115 S_ uses.
> > 
> > Convert all the S_ symbolic permissions to their octal equivalents
> > as using octal and not symbolic permissions is preferred by many as more
> > readable.
> > 
> > see: https://lkml.org/lkml/2016/8/2/1945
> > 
> > Done with automated conversion via:
> > $ ./scripts/checkpatch.pl -f --types=SYMBOLIC_PERMS --fix-inplace 
> > 
> > Miscellanea:
> > 
> > o Wrapped modified multi-line calls to a single line where appropriate
> > o Realign modified multi-line calls to open parenthesis
> > o drivers/gpu/drm/msm/adreno/a5xx_debugfs.c has a world-writeable
> >   debug permission for "reset" - perhaps that should be modified
> > Signed-off-by: Joe Perches 
> > ---
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c|  2 +-
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 98 
> > +++---
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c   |  3 +-
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|  9 +-
> >  drivers/gpu/drm/armada/armada_debugfs.c|  4 +-
> >  drivers/gpu/drm/drm_debugfs.c  |  6 +-
> >  drivers/gpu/drm/drm_debugfs_crc.c  |  4 +-
> >  drivers/gpu/drm/drm_sysfs.c|  2 +-
> >  drivers/gpu/drm/i915/gvt/firmware.c|  2 +-
> >  drivers/gpu/drm/i915/i915_debugfs.c|  8 +-
> >  drivers/gpu/drm/i915/i915_perf.c   |  2 +-
> >  drivers/gpu/drm/i915/i915_sysfs.c  | 22 ++---
> >  drivers/gpu/drm/i915/intel_pipe_crc.c  |  2 +-
> 
> Please send at least i915 changes separately. There's zero reason to
> make our lives harder for this change.

The idea is to avoid unnecessary multiple patches for
individual trees.

But you could do that via something like:

$ git am --include='drivers/gpu/drm/i915/*' 

cheers, Joe

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Re: [Freedreno] [PATCH] gpu: Consistently use octal not symbolic permissions

2018-05-25 Thread Jani Nikula 
On Thu, 24 May 2018, Joe Perches  wrote:
> There is currently a mixture of octal and symbolic permissions uses
> in files in drivers/gpu/drm and one file in drivers/gpu.
>
> There are ~270 existing octal uses and ~115 S_ uses.
>
> Convert all the S_ symbolic permissions to their octal equivalents
> as using octal and not symbolic permissions is preferred by many as more
> readable.
>
> see: https://lkml.org/lkml/2016/8/2/1945
>
> Done with automated conversion via:
> $ ./scripts/checkpatch.pl -f --types=SYMBOLIC_PERMS --fix-inplace 
>
> Miscellanea:
>
> o Wrapped modified multi-line calls to a single line where appropriate
> o Realign modified multi-line calls to open parenthesis
> o drivers/gpu/drm/msm/adreno/a5xx_debugfs.c has a world-writeable
>   debug permission for "reset" - perhaps that should be modified
>
> Signed-off-by: Joe Perches 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c|  2 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 98 
> +++---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c   |  3 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|  9 +-
>  drivers/gpu/drm/armada/armada_debugfs.c|  4 +-
>  drivers/gpu/drm/drm_debugfs.c  |  6 +-
>  drivers/gpu/drm/drm_debugfs_crc.c  |  4 +-
>  drivers/gpu/drm/drm_sysfs.c|  2 +-
>  drivers/gpu/drm/i915/gvt/firmware.c|  2 +-
>  drivers/gpu/drm/i915/i915_debugfs.c|  8 +-
>  drivers/gpu/drm/i915/i915_perf.c   |  2 +-
>  drivers/gpu/drm/i915/i915_sysfs.c  | 22 ++---
>  drivers/gpu/drm/i915/intel_pipe_crc.c  |  2 +-

Please send at least i915 changes separately. There's zero reason to
make our lives harder for this change.

BR,
Jani.

-- 
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