Re: [Freedreno] [PATCH] drm: Split out drm_probe_helper.h
On Mon, Jan 21, 2019 at 11:13 PM Sam Ravnborg wrote: > > Hi Daniel et al. > > > > > > > Yeah the drm_crtc_helper.h header is a bit the miniature drmP.h for legacy > > > kms drivers. Just removing it from all the atomic drivers caused lots of > > > fallout, I expect even more if you entirely remove the includes it has. > > > Maybe a todo, care to pls create that patch since it's your idea? > > > > The main reason I bailed out initially was that this would create > > small changes to several otherwise seldomly touched files. > > And then we would later come and remove drmP.h - so lots of > > small but incremental changes to the same otherwise seldomly > > edited files. > > And the job was only partially done. > > > > I will try to experiment with an approach where I clean up the > > include/drm/*.h files a little (like suggested above, +delete drmP.h > > and maybe a bit more). > > > > Then to try on a driver by driver basis to make it build with a > > cleaned set of include files. > > I hope that the cleaned up driver can still build without the > > cleaned header files so the changes can be submitted piecemal. > > > > Will do so with an eye on the lesser maintained drivers to try it > > out to avoid creating too much chrunch for others. > > I have now a few patches queued, but the result is not too pretty. > I did the following: > > - For all files in include/drm/*.h the set of include files > were adjusted to the minimum number of files required to make > them build without any other files included first. > > Created one .c file for each .h file. Then included the .h > file and adjusted to the minimal set of include files. > In the process a lot of forwards were added. > > - Deleted drmP.h > > - Fixed build of a few drivers: sti, tilcdc, gma500, tve200, via > > Some observations: > > - Killing all the includes not needed in the headers files > results in a a lot of extra changes. > Examples: > drm_modseset_helper_vtables.h is no longer > included by anyone, so needs to be added in many files > > drm_atomic_state_helper.h is no longer included > by anyone so likewise needs to be added in many files > > - It is very tedious to do this properly. > The process I followed was: > - delete / comment out all include files > - add back the obvious from a quick scan of the code > - build - fix - build - fix - build - fix ... > - next file... > > - The result is errorprone as only the allyesconfig + allmodconfig > variants are tested. But reallife configurations are more diverse. > > Current diffstat: >111 files changed, 771 insertions(+), 401 deletions(-) > > This is for the 5 drivers alone and not the header cleanup. > So long story short - this is not good and not the way forward. > > I will try to come up with a few improvements to make the > headers files selfcontained, but restricted to the changes that > add forwards/include to avoid the chrunch in all the drivers. > > And then post for review a few patches to clean up some headers. > If the cleanup gets a go I will try to persuade the introduction > of these. > This will include, but will not be limited to, the above mentioned > drm_crtc_helper.h header file. > > For now too much time was already spent on this, so it is at the > moment pushed back on my TODO list. > This mail serve also as a kind of "where had I left", when/if I > pick this up again. > > If there are anyone that knows some tooling that can help in the > process of adjusting the header files I am all ears. Yeah in the process of splitting up drmP.h we've created a few smaller such piles of headers. I think in some cases it's just not going to be worth it to fully split them up, e.g. drm_crtc_helper.h is going to be a pure legacy helper, only needed by pre-atomic drivers. Splitting that up doesn't seem to useful to me. Similarly we might want drm_atomic_helper.h to keep pulling in the other helper headers. So probably going to be a judgement call on a case-by-case basis. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH v3] drm/msm/dpu: Change definition of RGB565 and BGR565
On Mon, Dec 17, 2018 at 03:34:09PM -0800, Tanmay Shah wrote:
> Correct definition of both formats by swapping red
> and blue channels
>
> v3: update commit message
>
> Signed-off-by: Tanmay Shah
Applied to dpu-staging, thanks!
Sean
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
> index d53abc8ce670..f59fe1a9f4b9 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
> @@ -263,13 +263,13 @@ static const struct dpu_format dpu_format_map[] = {
>
> INTERLEAVED_RGB_FMT(RGB565,
> 0, COLOR_5BIT, COLOR_6BIT, COLOR_5BIT,
> - C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3,
> + C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
> false, 2, 0,
> DPU_FETCH_LINEAR, 1),
>
> INTERLEAVED_RGB_FMT(BGR565,
> 0, COLOR_5BIT, COLOR_6BIT, COLOR_5BIT,
> - C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
> + C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3,
> false, 2, 0,
> DPU_FETCH_LINEAR, 1),
>
> --
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> a Linux Foundation Collaborative Project
>
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[Freedreno] [pull] drm/msm: drm-msm-fixes-2018-01-22 for 5.0
Hi Dave, A few fixes for v5.0.. the opp-level fix and removal of hard-coded irq name is partially to make things smoother in v5.1 merge window to avoid dependency on drm vs dt trees, but are otherwise sane changes. The following changes since commit ba0ede185ef4c74bfecfe1c992be5dbcc5c5ac04: drm/msm/dpu: Fix clock issue after bind failure (2018-12-11 13:10:19 -0500) are available in the Git repository at: git://people.freedesktop.org/~robclark/linux drm-msm-fixes-2018-01-22 for you to fetch changes up to fa3e64a16adcbad7c838589f0fbfb86abb24f5a0: drm/msm: avoid unused function warning (2019-01-22 11:32:10 -0500) Arnd Bergmann (2): drm/msm/gpu: fix building without debugfs drm/msm: avoid unused function warning Douglas Anderson (1): drm/msm: Fix A6XX support for opp-level Joe Perches (1): drm/msm: Add __printf verification Jordan Crouse (2): drm/msm/gpu: Remove hardcoded interrupt name drm/msm: drop interrupt-names Kristian H. Kristensen (1): drm/msm: Unblock writer if reader closes file Rob Clark (1): drm/msm: honor GPU_READONLY flag .../devicetree/bindings/display/msm/gpu.txt| 1 - drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 +- drivers/gpu/drm/msm/adreno/adreno_gpu.c| 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 26 +++--- drivers/gpu/drm/msm/msm_drv.h | 6 - drivers/gpu/drm/msm/msm_gem.c | 8 +-- drivers/gpu/drm/msm/msm_gem_vma.c | 5 +++-- drivers/gpu/drm/msm/msm_gpu.c | 2 +- drivers/gpu/drm/msm/msm_gpu.h | 3 +-- drivers/gpu/drm/msm/msm_rd.c | 7 +- 10 files changed, 36 insertions(+), 25 deletions(-) ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH v3 1/3] drm/msm/a6xx: Add support for an interconnect path
Hi,
On Mon, Jan 21, 2019 at 9:13 AM Georgi Djakov wrote:
>
> Hi Rob,
>
> On 1/18/19 21:16, Rob Clark wrote:
> > On Fri, Jan 18, 2019 at 1:06 PM Doug Anderson wrote:
> >>
> >> Hi,
> >>
> >> On Thu, Dec 20, 2018 at 9:30 AM Jordan Crouse
> >> wrote:
> >>>
> >>> Try to get the interconnect path for the GPU and vote for the maximum
> >>> bandwidth to support all frequencies. This is needed for performance.
> >>> Later we will want to scale the bandwidth based on the frequency to
> >>> also optimize for power but that will require some device tree
> >>> infrastructure that does not yet exist.
> >>>
> >>> v5: Remove hardcoded interconnect name and just use the default
> >>
> >> nit: ${SUBJECT} says v3, but this is v5.
> >>
> >> I'll put in my usual plug for considering "patman" to help post
> >> patches. Even though it lives in the u-boot git repo it's still a gem
> >> for kernel work.
> >>
> >>
> >>
> >>> @@ -85,6 +89,12 @@ static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu,
> >>> int index)
> >>> dev_err(gmu->dev, "GMU set GPU frequency error: %d\n",
> >>> ret);
> >>>
> >>> gmu->freq = gmu->gpu_freqs[index];
> >>> +
> >>> + /*
> >>> +* Eventually we will want to scale the path vote with the
> >>> frequency but
> >>> +* for now leave it at max so that the performance is nominal.
> >>> +*/
> >>> + icc_set(gpu->icc_path, 0, MBps_to_icc(7216));
> >>
> >> You'll need to change icc_set() here to icc_set_bw() to match v13, AKA:
> >>
> >> - https://patchwork.kernel.org/patch/10766335/
> >> - https://lkml.kernel.org/r/20190116161103.6937-2-georgi.dja...@linaro.org
> >>
> >>
> >>> @@ -695,6 +707,9 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
> >>> if (ret)
> >>> goto out;
> >>>
> >>> + /* Set the bus quota to a reasonable value for boot */
> >>> + icc_set(gpu->icc_path, 0, MBps_to_icc(3072));
> >>
> >> This will also need to change to icc_set_bw()
> >>
> >>
> >>> @@ -781,6 +798,9 @@ int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu)
> >>> /* Tell RPMh to power off the GPU */
> >>> a6xx_rpmh_stop(gmu);
> >>>
> >>> + /* Remove the bus vote */
> >>> + icc_set(gpu->icc_path, 0, 0);
> >>
> >> This will also need to change to icc_set_bw()
> >>
> >>
> >> I have the same questions for this series that I had in response to
> >> the email ("[v5 2/3] drm/msm/dpu: Integrate interconnect API in MDSS")
> >>
> >>
> >>
> >> Copy / pasting here (with minor name changes) so folks don't have to
> >> follow links / search email.
> >>
> >> ==
> >>
> >> I'm curious what the plan is for landing this series. Rob / Gerogi:
> >> do you have any preference? Options I'd imagine:
> >>
> >> A) Wait until interconnect lands (in 5.1?) and land this through
> >> msm-next in the version after (5.2?)
> >>
> >> B) Georgi provides an immutable branch for interconnect when his lands
> >> (assuming he's landing via pull request) and that gets pulled into the
> >> the relevant drm tree.
> >>
> >> C) Rob Acks this series and indicates that it should go in through
> >> Gerogi's tree (probably only works if Georgi plans to send a pull
> >> request). If we're going this route then (IIUC) we'd want to land
> >> this in Gerogi's tree sooner rather than later so it can get some bake
> >> time? NOTE: as per my prior reply, I believe Rob has already Acked
> >> this patch.
> >>
> >
> > I'm ok to ack and have it land via Georgi's tree, if Georgi wants to
> > do that. Or otherwise, I could maybe coordinate w/ airlied to send a
> > 2nd late msm-next pr including the gpu and display interconnect
> > patches.
>
> I'm fine either way. But it would be nice if both patches (this one and
> the dt-bindings go together. The v6 of this patch applies cleanly to my
> tree, but the next one (2/3) with the dt-bindings doesn't.
Ah, right. You need to be based upon commit 85437cddf4e5
("dt-bindings: drm/msm/a6xx: Document GMU and update GPU bindings")
from Rob Clark's msm-next AKA
...so I guess the easiest is to have the bindings could go through Rob
Clark's tree and the code through you tree if that's what people want
to do?
-Doug
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Re: [Freedreno] [v1] drm/msm/dpu: Remove unused enum and comment from dpu mdss
On Wed, Dec 19, 2018 at 12:23:53AM +0530, Jayant Shekhar wrote:
> Remove enum dpu_iommu_domain from dpu mdss as its unused.
>
> Remove unnecessary comment for variable which is already
> removed.
>
> Signed-off-by: Jayant Shekhar
Applied to dpu-staging, thanks!
Sean
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 7 ---
> 1 file changed, 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> index 68c54d2..1ab8d4a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> @@ -258,12 +258,6 @@ enum dpu_vbif {
> VBIF_NRT = VBIF_1
> };
>
> -enum dpu_iommu_domain {
> - DPU_IOMMU_DOMAIN_UNSECURE,
> - DPU_IOMMU_DOMAIN_SECURE,
> - DPU_IOMMU_DOMAIN_MAX
> -};
> -
> /**
> * DPU HW,Component order color map
> */
> @@ -358,7 +352,6 @@ enum dpu_3d_blend_mode {
> * @alpha_enable: whether the format has an alpha channel
> * @num_planes: number of planes (including meta data planes)
> * @fetch_mode: linear, tiled, or ubwc hw fetch behavior
> - * @is_yuv: is format a yuv variant
> * @flag: usage bit flags
> * @tile_width: format tile width
> * @tile_height: format tile height
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
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Re: [Freedreno] [v3] drm/msm/dpu: Clean up dpu hw interrupts
On Tue, Dec 18, 2018 at 05:05:48PM +0530, Jayant Shekhar wrote:
> Remove unused functions and macros from files handling
> dpu hardware interrupts.
>
> changes in v2:
> Removed clear_interrupt_status (Jordan Crouse)
> changes in v3:
> Changed commit text
>
> Signed-off-by: Jayant Shekhar
Applied to dpu-staging, thanks!
Sean
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 44
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 44
> ---
> 2 files changed, 88 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> index c0b7f00..8a28a03 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> @@ -170,10 +170,6 @@
> /**
> * AD4 interrupt status bit definitions
> */
> -#define DPU_INTR_BRIGHTPR_UPDATED BIT(4)
> -#define DPU_INTR_DARKENH_UPDATED BIT(3)
> -#define DPU_INTR_STREN_OUTROI_UPDATED BIT(2)
> -#define DPU_INTR_STREN_INROI_UPDATED BIT(1)
> #define DPU_INTR_BACKLIGHT_UPDATED BIT(0)
> /**
> * struct dpu_intr_reg - array of DPU register sets
> @@ -782,18 +778,6 @@ static int dpu_hw_intr_irqidx_lookup(enum dpu_intr_type
> intr_type,
> return -EINVAL;
> }
>
> -static void dpu_hw_intr_set_mask(struct dpu_hw_intr *intr, uint32_t reg_off,
> - uint32_t mask)
> -{
> - if (!intr)
> - return;
> -
> - DPU_REG_WRITE(>hw, reg_off, mask);
> -
> - /* ensure register writes go through */
> - wmb();
> -}
> -
> static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr,
> void (*cbfunc)(void *, int),
> void *arg)
> @@ -1004,18 +988,6 @@ static int dpu_hw_intr_disable_irqs(struct dpu_hw_intr
> *intr)
> return 0;
> }
>
> -static int dpu_hw_intr_get_valid_interrupts(struct dpu_hw_intr *intr,
> - uint32_t *mask)
> -{
> - if (!intr || !mask)
> - return -EINVAL;
> -
> - *mask = IRQ_SOURCE_MDP | IRQ_SOURCE_DSI0 | IRQ_SOURCE_DSI1
> - | IRQ_SOURCE_HDMI | IRQ_SOURCE_EDP;
> -
> - return 0;
> -}
> -
> static void dpu_hw_intr_get_interrupt_statuses(struct dpu_hw_intr *intr)
> {
> int i;
> @@ -1065,19 +1037,6 @@ static void
> dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr,
> wmb();
> }
>
> -static void dpu_hw_intr_clear_interrupt_status(struct dpu_hw_intr *intr,
> - int irq_idx)
> -{
> - unsigned long irq_flags;
> -
> - if (!intr)
> - return;
> -
> - spin_lock_irqsave(>irq_lock, irq_flags);
> - dpu_hw_intr_clear_intr_status_nolock(intr, irq_idx);
> - spin_unlock_irqrestore(>irq_lock, irq_flags);
> -}
> -
> static u32 dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr,
> int irq_idx, bool clear)
> {
> @@ -1113,16 +1072,13 @@ static u32 dpu_hw_intr_get_interrupt_status(struct
> dpu_hw_intr *intr,
>
> static void __setup_intr_ops(struct dpu_hw_intr_ops *ops)
> {
> - ops->set_mask = dpu_hw_intr_set_mask;
> ops->irq_idx_lookup = dpu_hw_intr_irqidx_lookup;
> ops->enable_irq = dpu_hw_intr_enable_irq;
> ops->disable_irq = dpu_hw_intr_disable_irq;
> ops->dispatch_irqs = dpu_hw_intr_dispatch_irq;
> ops->clear_all_irqs = dpu_hw_intr_clear_irqs;
> ops->disable_all_irqs = dpu_hw_intr_disable_irqs;
> - ops->get_valid_interrupts = dpu_hw_intr_get_valid_interrupts;
> ops->get_interrupt_statuses = dpu_hw_intr_get_interrupt_statuses;
> - ops->clear_interrupt_status = dpu_hw_intr_clear_interrupt_status;
> ops->clear_intr_status_nolock = dpu_hw_intr_clear_intr_status_nolock;
> ops->get_interrupt_status = dpu_hw_intr_get_interrupt_status;
> }
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> index 61e4cba..4d7a1c7 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> @@ -20,13 +20,6 @@
> #include "dpu_hw_util.h"
> #include "dpu_hw_mdss.h"
>
> -#define IRQ_SOURCE_MDP BIT(0)
> -#define IRQ_SOURCE_DSI0 BIT(4)
> -#define IRQ_SOURCE_DSI1 BIT(5)
> -#define IRQ_SOURCE_HDMI BIT(8)
> -#define IRQ_SOURCE_EDP BIT(12)
> -#define IRQ_SOURCE_MHL BIT(16)
> -
> /**
> * dpu_intr_type - HW Interrupt Type
> * @DPU_IRQ_TYPE_WB_ROT_COMP:WB rotator done
> @@ -96,18 +89,6 @@ enum dpu_intr_type {
> */
> struct dpu_hw_intr_ops {
> /**
> - * set_mask - Programs the given interrupt register with the
> - *given interrupt mask. Register value will get overwritten.
> - * @intr: HW interrupt handle
> - * @reg_off:MDSS HW register offset
> - * @irqmask:IRQ mask value
> - */
> - void (*set_mask)(
> - struct dpu_hw_intr
Re: [Freedreno] [v1] drm/msm/dpu: Cleanup dpu plane interface
On Tue, Dec 18, 2018 at 06:50:38PM +0530, Jayant Shekhar wrote:
> Remove unused functions from dpu plane interface
> and unused variables from dpu plane state structure.
>
> Signed-off-by: Jayant Shekhar
Applied to dpu-staging, thanks!
Sean
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 27 ---
> 1 file changed, 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> index 7fed0b6..0e6063a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> @@ -28,23 +28,18 @@
> /**
> * struct dpu_plane_state: Define dpu extension of drm plane state object
> * @base:base drm plane state object
> - * @property_state: Local storage for msm_prop properties
> - * @property_values: cached plane property values
> * @aspace: pointer to address space for input/output buffers
> - * @input_fence: dereferenced input fence pointer
> * @stage: assigned by crtc blender
> * @multirect_index: index of the rectangle of SSPP
> * @multirect_mode: parallel or time multiplex multirect mode
> * @pending: whether the current update is still pending
> * @scaler3_cfg: configuration data for scaler3
> * @pixel_ext: configuration data for pixel extensions
> - * @scaler_check_state: indicates status of user provided pixel extension
> data
> * @cdp_cfg: CDP configuration
> */
> struct dpu_plane_state {
> struct drm_plane_state base;
> struct msm_gem_address_space *aspace;
> - void *input_fence;
> enum dpu_stage stage;
> uint32_t multirect_index;
> uint32_t multirect_mode;
> @@ -107,12 +102,6 @@ void dpu_plane_get_ctl_flush(struct drm_plane *plane,
> struct dpu_hw_ctl *ctl,
> void dpu_plane_flush(struct drm_plane *plane);
>
> /**
> - * dpu_plane_kickoff - final plane operations before commit kickoff
> - * @plane: Pointer to drm plane structure
> - */
> -void dpu_plane_kickoff(struct drm_plane *plane);
> -
> -/**
> * dpu_plane_set_error: enable/disable error condition
> * @plane: pointer to drm_plane structure
> */
> @@ -147,14 +136,6 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
> void dpu_plane_clear_multirect(const struct drm_plane_state *drm_state);
>
> /**
> - * dpu_plane_wait_input_fence - wait for input fence object
> - * @plane: Pointer to DRM plane object
> - * @wait_ms: Wait timeout value
> - * Returns: Zero on success
> - */
> -int dpu_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms);
> -
> -/**
> * dpu_plane_color_fill - enables color fill on plane
> * @plane: Pointer to DRM plane object
> * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red
> @@ -164,12 +145,4 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
> int dpu_plane_color_fill(struct drm_plane *plane,
> uint32_t color, uint32_t alpha);
>
> -/**
> - * dpu_plane_set_revalidate - sets revalidate flag which forces a full
> - * validation of the plane properties in the next atomic check
> - * @plane: Pointer to DRM plane object
> - * @enable: Boolean to set/unset the flag
> - */
> -void dpu_plane_set_revalidate(struct drm_plane *plane, bool enable);
> -
> #endif /* _DPU_PLANE_H_ */
> --
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> a Linux Foundation Collaborative Project
>
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[Freedreno] [v6 1/3] drm/msm/dpu: clean up references of DPU custom bus scaling
Since the upstream interconnect bus framework has landed
upstream, the existing references of custom bus scaling
needs to be cleaned up.
Changes in v2:
- Fixed build error due to partial clean up
Changes in v3:
- Condense multiple lines into a single line (Sean Paul)
Changes in v4:
- None
Changes in v5:
- None
Changes in v6:
-None
Signed-off-by: Sravanthi Kollukuduru
Signed-off-by: Jayant Shekhar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c| 174 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h| 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 13 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c | 47 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h | 68 -
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h| 22 +--
6 files changed, 89 insertions(+), 239 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index 22e84b3..c75536e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
@@ -84,7 +84,6 @@ static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms,
struct dpu_core_perf_params *perf)
{
struct dpu_crtc_state *dpu_cstate;
- int i;
if (!kms || !kms->catalog || !crtc || !state || !perf) {
DPU_ERROR("invalid parameters\n");
@@ -95,35 +94,24 @@ static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms,
memset(perf, 0, sizeof(struct dpu_core_perf_params));
if (!dpu_cstate->bw_control) {
- for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
- perf->bw_ctl[i] = kms->catalog->perf.max_bw_high *
+ perf->bw_ctl = kms->catalog->perf.max_bw_high *
1000ULL;
- perf->max_per_pipe_ib[i] = perf->bw_ctl[i];
- }
+ perf->max_per_pipe_ib = perf->bw_ctl;
perf->core_clk_rate = kms->perf.max_core_clk_rate;
} else if (kms->perf.perf_tune.mode == DPU_PERF_MODE_MINIMUM) {
- for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
- perf->bw_ctl[i] = 0;
- perf->max_per_pipe_ib[i] = 0;
- }
+ perf->bw_ctl = 0;
+ perf->max_per_pipe_ib = 0;
perf->core_clk_rate = 0;
} else if (kms->perf.perf_tune.mode == DPU_PERF_MODE_FIXED) {
- for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
- perf->bw_ctl[i] = kms->perf.fix_core_ab_vote;
- perf->max_per_pipe_ib[i] = kms->perf.fix_core_ib_vote;
- }
+ perf->bw_ctl = kms->perf.fix_core_ab_vote;
+ perf->max_per_pipe_ib = kms->perf.fix_core_ib_vote;
perf->core_clk_rate = kms->perf.fix_core_clk_rate;
}
DPU_DEBUG(
- "crtc=%d clk_rate=%llu core_ib=%llu core_ab=%llu llcc_ib=%llu
llcc_ab=%llu mem_ib=%llu mem_ab=%llu\n",
+ "crtc=%d clk_rate=%llu core_ib=%llu core_ab=%llu\n",
crtc->base.id, perf->core_clk_rate,
- perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_MNOC],
- perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_MNOC],
- perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_LLCC],
- perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_LLCC],
- perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_EBI],
- perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_EBI]);
+ perf->max_per_pipe_ib, perf->bw_ctl);
}
int dpu_core_perf_crtc_check(struct drm_crtc *crtc,
@@ -136,7 +124,6 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc,
struct dpu_crtc_state *dpu_cstate;
struct drm_crtc *tmp_crtc;
struct dpu_kms *kms;
- int i;
if (!crtc || !state) {
DPU_ERROR("invalid crtc\n");
@@ -158,31 +145,25 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc,
/* obtain new values */
_dpu_core_perf_calc_crtc(kms, crtc, state, _cstate->new_perf);
- for (i = DPU_POWER_HANDLE_DBUS_ID_MNOC;
- i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
- bw_sum_of_intfs = dpu_cstate->new_perf.bw_ctl[i];
- curr_client_type = dpu_crtc_get_client_type(crtc);
+ bw_sum_of_intfs = dpu_cstate->new_perf.bw_ctl;
+ curr_client_type = dpu_crtc_get_client_type(crtc);
- drm_for_each_crtc(tmp_crtc, crtc->dev) {
- if (_dpu_core_perf_crtc_is_power_on(tmp_crtc) &&
- (dpu_crtc_get_client_type(tmp_crtc) ==
- curr_client_type) &&
- (tmp_crtc != crtc)) {
- struct dpu_crtc_state *tmp_cstate =
-
[Freedreno] [v6 2/3] drm/msm/dpu: Integrate interconnect API in MDSS
The interconnect framework is designed to provide a
standard kernel interface to control the settings of
the interconnects on a SoC.
The interconnect API uses a consumer/provider-based model,
where the providers are the interconnect buses and the
consumers could be various drivers.
MDSS is one of the interconnect consumers which uses the
interconnect APIs to get the path between endpoints and
set its bandwidth requirement for the given interconnected
path.
Changes in v2:
- Remove error log and unnecessary check (Jordan Crouse)
Changes in v3:
- Code clean involving variable name change, removal
of extra paranthesis and variables (Matthias Kaehlcke)
Changes in v4:
- Add comments, spacings, tabs, proper port name
and icc macro (Georgi Djakov)
Changes in v5:
- Commit text and parenthesis alignment (Georgi Djakov)
Changes in v6:
- Change to new icc_set API's (Doug Anderson)
Signed-off-by: Sravanthi Kollukuduru1
Signed-off-by: Jayant Shekhar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 49 +---
1 file changed, 45 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
index 38576f8..38daf8a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
@@ -4,11 +4,15 @@
*/
#include "dpu_kms.h"
+#include
#define to_dpu_mdss(x) container_of(x, struct dpu_mdss, base)
#define HW_INTR_STATUS 0x0010
+/* Max BW defined in KBps */
+#define MAX_BW 680
+
struct dpu_mdss {
struct msm_mdss base;
void __iomem *mmio;
@@ -16,8 +20,30 @@ struct dpu_mdss {
u32 hwversion;
struct dss_module_power mp;
struct dpu_irq_controller irq_controller;
+ struct icc_path *path[2];
+ u32 num_paths;
};
+static int dpu_mdss_parse_data_bus_icc_path(struct drm_device *dev,
+ struct dpu_mdss *dpu_mdss)
+{
+ struct icc_path *path0 = of_icc_get(dev->dev, "mdp0-mem");
+ struct icc_path *path1 = of_icc_get(dev->dev, "mdp1-mem");
+
+ if (IS_ERR(path0))
+ return PTR_ERR(path0);
+
+ dpu_mdss->path[0] = path0;
+ dpu_mdss->num_paths = 1;
+
+ if (!IS_ERR(path1)) {
+ dpu_mdss->path[1] = path1;
+ dpu_mdss->num_paths++;
+ }
+
+ return 0;
+}
+
static irqreturn_t dpu_mdss_irq(int irq, void *arg)
{
struct dpu_mdss *dpu_mdss = arg;
@@ -127,7 +153,11 @@ static int dpu_mdss_enable(struct msm_mdss *mdss)
{
struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss);
struct dss_module_power *mp = _mdss->mp;
- int ret;
+ int ret, i;
+ u64 avg_bw = dpu_mdss->num_paths ? MAX_BW / dpu_mdss->num_paths : 0;
+
+ for (i = 0; i < dpu_mdss->num_paths; i++)
+ icc_set_bw(dpu_mdss->path[i], avg_bw, kBps_to_icc(MAX_BW));
ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true);
if (ret)
@@ -140,12 +170,15 @@ static int dpu_mdss_disable(struct msm_mdss *mdss)
{
struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss);
struct dss_module_power *mp = _mdss->mp;
- int ret;
+ int ret, i;
ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, false);
if (ret)
DPU_ERROR("clock disable failed, ret:%d\n", ret);
+ for (i = 0; i < dpu_mdss->num_paths; i++)
+ icc_set_bw(dpu_mdss->path[i], 0, 0);
+
return ret;
}
@@ -155,6 +188,7 @@ static void dpu_mdss_destroy(struct drm_device *dev)
struct msm_drm_private *priv = dev->dev_private;
struct dpu_mdss *dpu_mdss = to_dpu_mdss(priv->mdss);
struct dss_module_power *mp = _mdss->mp;
+ int i;
pm_runtime_disable(dev->dev);
_dpu_mdss_irq_domain_fini(dpu_mdss);
@@ -162,6 +196,9 @@ static void dpu_mdss_destroy(struct drm_device *dev)
msm_dss_put_clk(mp->clk_config, mp->num_clk);
devm_kfree(>dev, mp->clk_config);
+ for (i = 0; i < dpu_mdss->num_paths; i++)
+ icc_put(dpu_mdss->path[i]);
+
if (dpu_mdss->mmio)
devm_iounmap(>dev, dpu_mdss->mmio);
dpu_mdss->mmio = NULL;
@@ -200,6 +237,10 @@ int dpu_mdss_init(struct drm_device *dev)
}
dpu_mdss->mmio_len = resource_size(res);
+ ret = dpu_mdss_parse_data_bus_icc_path(dev, dpu_mdss);
+ if (ret)
+ return ret;
+
mp = _mdss->mp;
ret = msm_dss_parse_clock(pdev, mp);
if (ret) {
@@ -221,14 +262,14 @@ int dpu_mdss_init(struct drm_device *dev)
goto irq_error;
}
+ priv->mdss = _mdss->base;
+
pm_runtime_enable(dev->dev);
pm_runtime_get_sync(dev->dev);
dpu_mdss->hwversion = readl_relaxed(dpu_mdss->mmio);
pm_runtime_put_sync(dev->dev);
- priv->mdss = _mdss->base;
-
[Freedreno] [v6 3/3] dt-bindings: msm/disp: Introduce interconnect bindings for MDSS on SDM845
Add interconnect properties such as interconnect provider specifier , the edge source and destination ports which are required by the interconnect API to configure interconnect path for MDSS. Changes in v2: - none Changes in v3: - Remove common property definitions (Rob Herring) Changes in v4: - Use port macros and change port string names (Georgi Djakov) Changes in v5: - None Changes in v6: -None Signed-off-by: Sravanthi Kollukuduru Signed-off-by: Jayant Shekhar --- Documentation/devicetree/bindings/display/msm/dpu.txt | 10 ++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt b/Documentation/devicetree/bindings/display/msm/dpu.txt index ad2e883..a61dd40 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu.txt +++ b/Documentation/devicetree/bindings/display/msm/dpu.txt @@ -28,6 +28,11 @@ Required properties: - #address-cells: number of address cells for the MDSS children. Should be 1. - #size-cells: Should be 1. - ranges: parent bus address space is the same as the child bus address space. +- interconnects : interconnect path specifier for MDSS according to + Documentation/devicetree/bindings/interconnect/interconnect.txt. Should be + 2 paths corresponding to 2 AXI ports. +- interconnect-names : MDSS will have 2 port names to differentiate between the + 2 interconnect paths defined with interconnect specifier. Optional properties: - assigned-clocks: list of clock specifiers for clocks needing rate assignment @@ -86,6 +91,11 @@ Example: interrupt-controller; #interrupt-cells = <1>; + interconnects = <_hlos MASTER_MDP0 _hlos SLAVE_EBI1>, + <_hlos MASTER_MDP1 _hlos SLAVE_EBI1>; + + interconnect-names = "mdp0-mem", "mdp1-mem"; + iommus = <_iommu 0>; #address-cells = <2>; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [v6 0/3] Use interconnect API in MDSS on SDM845
The interconnect API provides an interface for consumer drivers to express their bandwidth needs in the SoC. This data is aggregated and the on-chip interconnect hardware is configured to the appropriate power/performance profile. MDSS is one of the interconnect consumers which uses the interconnect APIs to get the path between endpoints and set its bandwidth requirements for the given interconnected path. Subsequently, there is a clean up patch to remove all the references of the DPU custom bus scaling. There is corresponding DT patch with the source and destination ports defined for display driver which will be sent separately. Changes in v2: - Remove error log and unnecessary check (Jordan Crouse) - Fixed build error due to partial clean up Changes in v3: - Remove common property definitions (Rob Herring) - Code clean up involving variable name change, removal of extra paranthesis and variables (Matthias Kaehlcke) - Condense multiple lines into a single line (Sean Paul) Changes in v4: - Add comments, spacings, tabs, proper port name and icc macro - Use port macros and change port string names (Georgi Djakov) Changes in v5: - Updated commit text and parenthesis alignment (Georgi Djakov) Changes in v6: - Change icc_set to icc_set_bw (Doug Anderson) Jayant Shekhar (3): drm/msm/dpu: clean up references of DPU custom bus scaling drm/msm/dpu: Integrate interconnect API in MDSS dt-bindings: msm/disp: Introduce interconnect bindings for MDSS on SDM845 .../devicetree/bindings/display/msm/dpu.txt| 10 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 174 - drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 13 +- drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 49 +- drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c | 47 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h | 68 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 22 +-- 8 files changed, 144 insertions(+), 243 deletions(-) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [v6 0/3] Use interconnect API in MDSS on SDM845
The interconnect API provides an interface for consumer drivers to express their bandwidth needs in the SoC. This data is aggregated and the on-chip interconnect hardware is configured to the appropriate power/performance profile. MDSS is one of the interconnect consumers which uses the interconnect APIs to get the path between endpoints and set its bandwidth requirements for the given interconnected path. Subsequently, there is a clean up patch to remove all the references of the DPU custom bus scaling. There is corresponding DT patch with the source and destination ports defined for display driver which will be sent separately. Changes in v2: - Remove error log and unnecessary check (Jordan Crouse) - Fixed build error due to partial clean up Changes in v3: - Remove common property definitions (Rob Herring) - Code clean up involving variable name change, removal of extra paranthesis and variables (Matthias Kaehlcke) - Condense multiple lines into a single line (Sean Paul) Changes in v4: - Add comments, spacings, tabs, proper port name and icc macro - Use port macros and change port string names (Georgi Djakov) Changes in v5: - Updated commit text and parenthesis alignment (Georgi Djakov) Changes in v6: - Change icc_set to icc_set_bw (Doug Anderson) Jayant Shekhar (3): drm/msm/dpu: clean up references of DPU custom bus scaling drm/msm/dpu: Integrate interconnect API in MDSS dt-bindings: msm/disp: Introduce interconnect bindings for MDSS on SDM845 .../devicetree/bindings/display/msm/dpu.txt| 10 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 174 - drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 13 +- drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 49 +- drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c | 47 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h | 68 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 22 +-- 8 files changed, 144 insertions(+), 243 deletions(-) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [v6 1/3] drm/msm/dpu: clean up references of DPU custom bus scaling
Since the upstream interconnect bus framework has landed
upstream, the existing references of custom bus scaling
needs to be cleaned up.
Changes in v2:
- Fixed build error due to partial clean up
Changes in v3:
- Condense multiple lines into a single line (Sean Paul)
Changes in v4:
- None
Changes in v5:
- None
Changes in v6:
- None
Signed-off-by: Sravanthi Kollukuduru
Signed-off-by: Jayant Shekhar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c| 174 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h| 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 13 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c | 47 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h | 68 -
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h| 22 +--
6 files changed, 89 insertions(+), 239 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index 22e84b3..c75536e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
@@ -84,7 +84,6 @@ static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms,
struct dpu_core_perf_params *perf)
{
struct dpu_crtc_state *dpu_cstate;
- int i;
if (!kms || !kms->catalog || !crtc || !state || !perf) {
DPU_ERROR("invalid parameters\n");
@@ -95,35 +94,24 @@ static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms,
memset(perf, 0, sizeof(struct dpu_core_perf_params));
if (!dpu_cstate->bw_control) {
- for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
- perf->bw_ctl[i] = kms->catalog->perf.max_bw_high *
+ perf->bw_ctl = kms->catalog->perf.max_bw_high *
1000ULL;
- perf->max_per_pipe_ib[i] = perf->bw_ctl[i];
- }
+ perf->max_per_pipe_ib = perf->bw_ctl;
perf->core_clk_rate = kms->perf.max_core_clk_rate;
} else if (kms->perf.perf_tune.mode == DPU_PERF_MODE_MINIMUM) {
- for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
- perf->bw_ctl[i] = 0;
- perf->max_per_pipe_ib[i] = 0;
- }
+ perf->bw_ctl = 0;
+ perf->max_per_pipe_ib = 0;
perf->core_clk_rate = 0;
} else if (kms->perf.perf_tune.mode == DPU_PERF_MODE_FIXED) {
- for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
- perf->bw_ctl[i] = kms->perf.fix_core_ab_vote;
- perf->max_per_pipe_ib[i] = kms->perf.fix_core_ib_vote;
- }
+ perf->bw_ctl = kms->perf.fix_core_ab_vote;
+ perf->max_per_pipe_ib = kms->perf.fix_core_ib_vote;
perf->core_clk_rate = kms->perf.fix_core_clk_rate;
}
DPU_DEBUG(
- "crtc=%d clk_rate=%llu core_ib=%llu core_ab=%llu llcc_ib=%llu
llcc_ab=%llu mem_ib=%llu mem_ab=%llu\n",
+ "crtc=%d clk_rate=%llu core_ib=%llu core_ab=%llu\n",
crtc->base.id, perf->core_clk_rate,
- perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_MNOC],
- perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_MNOC],
- perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_LLCC],
- perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_LLCC],
- perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_EBI],
- perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_EBI]);
+ perf->max_per_pipe_ib, perf->bw_ctl);
}
int dpu_core_perf_crtc_check(struct drm_crtc *crtc,
@@ -136,7 +124,6 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc,
struct dpu_crtc_state *dpu_cstate;
struct drm_crtc *tmp_crtc;
struct dpu_kms *kms;
- int i;
if (!crtc || !state) {
DPU_ERROR("invalid crtc\n");
@@ -158,31 +145,25 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc,
/* obtain new values */
_dpu_core_perf_calc_crtc(kms, crtc, state, _cstate->new_perf);
- for (i = DPU_POWER_HANDLE_DBUS_ID_MNOC;
- i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
- bw_sum_of_intfs = dpu_cstate->new_perf.bw_ctl[i];
- curr_client_type = dpu_crtc_get_client_type(crtc);
+ bw_sum_of_intfs = dpu_cstate->new_perf.bw_ctl;
+ curr_client_type = dpu_crtc_get_client_type(crtc);
- drm_for_each_crtc(tmp_crtc, crtc->dev) {
- if (_dpu_core_perf_crtc_is_power_on(tmp_crtc) &&
- (dpu_crtc_get_client_type(tmp_crtc) ==
- curr_client_type) &&
- (tmp_crtc != crtc)) {
- struct dpu_crtc_state *tmp_cstate =
-
[Freedreno] [v6 3/3] dt-bindings: msm/disp: Introduce interconnect bindings for MDSS on SDM845
Add interconnect properties such as interconnect provider specifier , the edge source and destination ports which are required by the interconnect API to configure interconnect path for MDSS. Changes in v2: - none Changes in v3: - Remove common property definitions (Rob Herring) Changes in v4: - Use port macros and change port string names (Georgi Djakov) Changes in v5: - None Changes in v6: - None Signed-off-by: Sravanthi Kollukuduru Signed-off-by: Jayant Shekhar --- Documentation/devicetree/bindings/display/msm/dpu.txt | 10 ++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt b/Documentation/devicetree/bindings/display/msm/dpu.txt index ad2e883..a61dd40 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu.txt +++ b/Documentation/devicetree/bindings/display/msm/dpu.txt @@ -28,6 +28,11 @@ Required properties: - #address-cells: number of address cells for the MDSS children. Should be 1. - #size-cells: Should be 1. - ranges: parent bus address space is the same as the child bus address space. +- interconnects : interconnect path specifier for MDSS according to + Documentation/devicetree/bindings/interconnect/interconnect.txt. Should be + 2 paths corresponding to 2 AXI ports. +- interconnect-names : MDSS will have 2 port names to differentiate between the + 2 interconnect paths defined with interconnect specifier. Optional properties: - assigned-clocks: list of clock specifiers for clocks needing rate assignment @@ -86,6 +91,11 @@ Example: interrupt-controller; #interrupt-cells = <1>; + interconnects = <_hlos MASTER_MDP0 _hlos SLAVE_EBI1>, + <_hlos MASTER_MDP1 _hlos SLAVE_EBI1>; + + interconnect-names = "mdp0-mem", "mdp1-mem"; + iommus = <_iommu 0>; #address-cells = <2>; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [v6 2/3] drm/msm/dpu: Integrate interconnect API in MDSS
The interconnect framework is designed to provide a
standard kernel interface to control the settings of
the interconnects on a SoC.
The interconnect API uses a consumer/provider-based model,
where the providers are the interconnect buses and the
consumers could be various drivers.
MDSS is one of the interconnect consumers which uses the
interconnect APIs to get the path between endpoints and
set its bandwidth requirement for the given interconnected
path.
Changes in v2:
- Remove error log and unnecessary check (Jordan Crouse)
Changes in v3:
- Code clean involving variable name change, removal
of extra paranthesis and variables (Matthias Kaehlcke)
Changes in v4:
- Add comments, spacings, tabs, proper port name
and icc macro (Georgi Djakov)
Changes in v5:
- Commit text and parenthesis alignment (Georgi Djakov)
Changes in v6:
- Change to new icc_set API's (Doug Anderson)
Signed-off-by: Sravanthi Kollukuduru1
Signed-off-by: Jayant Shekhar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 49 +---
1 file changed, 45 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
index 38576f8..38daf8a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
@@ -4,11 +4,15 @@
*/
#include "dpu_kms.h"
+#include
#define to_dpu_mdss(x) container_of(x, struct dpu_mdss, base)
#define HW_INTR_STATUS 0x0010
+/* Max BW defined in KBps */
+#define MAX_BW 680
+
struct dpu_mdss {
struct msm_mdss base;
void __iomem *mmio;
@@ -16,8 +20,30 @@ struct dpu_mdss {
u32 hwversion;
struct dss_module_power mp;
struct dpu_irq_controller irq_controller;
+ struct icc_path *path[2];
+ u32 num_paths;
};
+static int dpu_mdss_parse_data_bus_icc_path(struct drm_device *dev,
+ struct dpu_mdss *dpu_mdss)
+{
+ struct icc_path *path0 = of_icc_get(dev->dev, "mdp0-mem");
+ struct icc_path *path1 = of_icc_get(dev->dev, "mdp1-mem");
+
+ if (IS_ERR(path0))
+ return PTR_ERR(path0);
+
+ dpu_mdss->path[0] = path0;
+ dpu_mdss->num_paths = 1;
+
+ if (!IS_ERR(path1)) {
+ dpu_mdss->path[1] = path1;
+ dpu_mdss->num_paths++;
+ }
+
+ return 0;
+}
+
static irqreturn_t dpu_mdss_irq(int irq, void *arg)
{
struct dpu_mdss *dpu_mdss = arg;
@@ -127,7 +153,11 @@ static int dpu_mdss_enable(struct msm_mdss *mdss)
{
struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss);
struct dss_module_power *mp = _mdss->mp;
- int ret;
+ int ret, i;
+ u64 avg_bw = dpu_mdss->num_paths ? MAX_BW / dpu_mdss->num_paths : 0;
+
+ for (i = 0; i < dpu_mdss->num_paths; i++)
+ icc_set_bw(dpu_mdss->path[i], avg_bw, kBps_to_icc(MAX_BW));
ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true);
if (ret)
@@ -140,12 +170,15 @@ static int dpu_mdss_disable(struct msm_mdss *mdss)
{
struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss);
struct dss_module_power *mp = _mdss->mp;
- int ret;
+ int ret, i;
ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, false);
if (ret)
DPU_ERROR("clock disable failed, ret:%d\n", ret);
+ for (i = 0; i < dpu_mdss->num_paths; i++)
+ icc_set_bw(dpu_mdss->path[i], 0, 0);
+
return ret;
}
@@ -155,6 +188,7 @@ static void dpu_mdss_destroy(struct drm_device *dev)
struct msm_drm_private *priv = dev->dev_private;
struct dpu_mdss *dpu_mdss = to_dpu_mdss(priv->mdss);
struct dss_module_power *mp = _mdss->mp;
+ int i;
pm_runtime_disable(dev->dev);
_dpu_mdss_irq_domain_fini(dpu_mdss);
@@ -162,6 +196,9 @@ static void dpu_mdss_destroy(struct drm_device *dev)
msm_dss_put_clk(mp->clk_config, mp->num_clk);
devm_kfree(>dev, mp->clk_config);
+ for (i = 0; i < dpu_mdss->num_paths; i++)
+ icc_put(dpu_mdss->path[i]);
+
if (dpu_mdss->mmio)
devm_iounmap(>dev, dpu_mdss->mmio);
dpu_mdss->mmio = NULL;
@@ -200,6 +237,10 @@ int dpu_mdss_init(struct drm_device *dev)
}
dpu_mdss->mmio_len = resource_size(res);
+ ret = dpu_mdss_parse_data_bus_icc_path(dev, dpu_mdss);
+ if (ret)
+ return ret;
+
mp = _mdss->mp;
ret = msm_dss_parse_clock(pdev, mp);
if (ret) {
@@ -221,14 +262,14 @@ int dpu_mdss_init(struct drm_device *dev)
goto irq_error;
}
+ priv->mdss = _mdss->base;
+
pm_runtime_enable(dev->dev);
pm_runtime_get_sync(dev->dev);
dpu_mdss->hwversion = readl_relaxed(dpu_mdss->mmio);
pm_runtime_put_sync(dev->dev);
- priv->mdss = _mdss->base;
-
Re: [Freedreno] [PATCH] drm/msm/dpu: Convert to a chained irq chip
On Thu, Jan 03, 2019 at 11:06:02AM -0800, Stephen Boyd wrote:
> Devices that make up DPU, i.e. graphics card, request their interrupts
> from this "virtual" interrupt chip. The interrupt chip builds upon a GIC
> SPI interrupt that raises high when any of the interrupts in the DPU's
> irq status register are triggered. From the kernel's perspective this is
> a chained irq chip, so requesting a flow handler for the GIC SPI and
> then calling generic IRQ handling code from that irq handler is not
> completely proper. It's better to convert this to a chained irq so that
> the GIC SPI irq doesn't appear in /proc/interrupts, can't have CPU
> affinity changed, and won't be accounted for with irq stats. Doing this
> also silences a recursive lockdep warning because we can specify a
> different lock class for the chained interrupts, silencing a warning
> that is easy to see with 'threadirqs' on the kernel commandline.
>
> WARNING: inconsistent lock state
> 4.19.10 #76 Tainted: GW
>
> inconsistent {IN-HARDIRQ-W} -> {HARDIRQ-ON-W} usage.
> irq/40-dpu_mdss/203 [HC0[0]:SC0[2]:HE1:SE0] takes:
> 53ea9021 (_desc_lock_class){?.-.}, at:
> handle_level_irq+0x34/0x26c
> {IN-HARDIRQ-W} state was registered at:
>lock_acquire+0x244/0x360
>_raw_spin_lock+0x64/0xa0
>handle_fasteoi_irq+0x54/0x2ec
>generic_handle_irq+0x44/0x5c
>__handle_domain_irq+0x9c/0x11c
>gic_handle_irq+0x208/0x260
>el1_irq+0xb4/0x130
>arch_cpu_idle+0x178/0x3cc
>default_idle_call+0x3c/0x54
>do_idle+0x1a8/0x3dc
>cpu_startup_entry+0x24/0x28
>rest_init+0x240/0x270
>start_kernel+0x5a8/0x6bc
> irq event stamp: 18
> hardirqs last enabled at (17): []
> _raw_spin_unlock_irq+0x40/0xc0
> hardirqs last disabled at (16): [] __schedule+0x20c/0x1bbc
> softirqs last enabled at (0): [] copy_process+0xb50/0x3964
> softirqs last disabled at (18): []
> local_bh_disable+0x8/0x20
>
> other info that might help us debug this:
> Possible unsafe locking scenario:
>
> CPU0
>
>lock(_desc_lock_class);
>
> lock(_desc_lock_class);
>
> *** DEADLOCK ***
>
> no locks held by irq/40-dpu_mdss/203.
>
> stack backtrace:
> CPU: 0 PID: 203 Comm: irq/40-dpu_mdss Tainted: GW 4.19.10 #76
> Call trace:
> dump_backtrace+0x0/0x2f8
> show_stack+0x20/0x2c
> __dump_stack+0x20/0x28
> dump_stack+0xcc/0x10c
> mark_lock+0xbe0/0xe24
> __lock_acquire+0x4cc/0x2708
> lock_acquire+0x244/0x360
> _raw_spin_lock+0x64/0xa0
> handle_level_irq+0x34/0x26c
> generic_handle_irq+0x44/0x5c
> dpu_mdss_irq+0x64/0xec
> irq_forced_thread_fn+0x58/0x9c
> irq_thread+0x120/0x1dc
> kthread+0x248/0x260
> ret_from_fork+0x10/0x18
> [ cut here ]
> irq 169 handler irq_default_primary_handler+0x0/0x18 enabled interrupts
>
> Cc: Sean Paul
> Cc: Jordan Crouse
> Cc: Jayant Shekhar
> Cc: Rajesh Yadav
> Cc: Jeykumar Sankaran
> Signed-off-by: Stephen Boyd
LGTM, applied to dpu-staging.
Thanks,
Sean
> ---
>
> drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 36 ++--
> 1 file changed, 21 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
> index cb307a2abf06..7316b4ab1b85 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
> @@ -23,11 +23,14 @@ struct dpu_mdss {
> struct dpu_irq_controller irq_controller;
> };
>
> -static irqreturn_t dpu_mdss_irq(int irq, void *arg)
> +static void dpu_mdss_irq(struct irq_desc *desc)
> {
> - struct dpu_mdss *dpu_mdss = arg;
> + struct dpu_mdss *dpu_mdss = irq_desc_get_handler_data(desc);
> + struct irq_chip *chip = irq_desc_get_chip(desc);
> u32 interrupts;
>
> + chained_irq_enter(chip, desc);
> +
> interrupts = readl_relaxed(dpu_mdss->mmio + HW_INTR_STATUS);
>
> while (interrupts) {
> @@ -39,20 +42,20 @@ static irqreturn_t dpu_mdss_irq(int irq, void *arg)
> hwirq);
> if (mapping == 0) {
> DRM_ERROR("couldn't find irq mapping for %lu\n", hwirq);
> - return IRQ_NONE;
> + break;
> }
>
> rc = generic_handle_irq(mapping);
> if (rc < 0) {
> DRM_ERROR("handle irq fail: irq=%lu mapping=%u rc=%d\n",
> hwirq, mapping, rc);
> - return IRQ_NONE;
> + break;
> }
>
> interrupts &= ~(1 << hwirq);
> }
>
> - return IRQ_HANDLED;
> + chained_irq_exit(chip, desc);
> }
>
> static void dpu_mdss_irq_mask(struct irq_data *irqd)
> @@ -83,16 +86,16 @@ static struct irq_chip dpu_mdss_irq_chip = {
> .irq_unmask = dpu_mdss_irq_unmask,
> };
>
> +static struct lock_class_key dpu_mdss_lock_key,
Re: [Freedreno] [PATCH v4 1/3] drm/msm/dpu: fix documentation for intf_type
On Mon, Dec 17, 2018 at 02:35:03PM -0800, Jeykumar Sankaran wrote:
> Fix intf_type description in msm_disp_info to show that
> it represents drm encoder mode of the display.
>
> changes in v3:
> - introduced in the series
> changes in v4:
> - none
>
> Signed-off-by: Jeykumar Sankaran
Pushed to dpu-staging. For the DP part of this series, it'd be helpful for
Chandan to package it up with his set so it all goes in one bundle. That should
also hopefully make kbuildbot happy.
Sean
> ---
> drivers/gpu/drm/msm/msm_drv.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index 9cd6a96..4725d52 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -126,7 +126,7 @@ struct msm_display_topology {
>
> /**
> * struct msm_display_info - defines display properties
> - * @intf_type: DRM_MODE_CONNECTOR_ display type
> + * @intf_type: DRM_MODE_ENCODER_ type
> * @capabilities: Bitmask of display flags
> * @num_of_h_tiles: Number of horizontal tiles in case of split interface
> * @h_tile_instance:Controller instance used per tile. Number of
> elements is
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
> ___
> Freedreno mailing list
> Freedreno@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/freedreno
--
Sean Paul, Software Engineer, Google / Chromium OS
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Re: [Freedreno] [PATCH v4 2/3] drm/msm/dpu: handle failures while initializing displays
On Mon, Dec 17, 2018 at 02:35:04PM -0800, Jeykumar Sankaran wrote:
> Bail out KMS hw init on display initialization failures with
> proper error logging.
>
> changes in v3:
> - introduced in the series
> changes in v4:
> - avoid duplicate return on errors (Sean Paul)
> - avoid spamming errors on failures (Jordon Crouse)
>
> Signed-off-by: Jeykumar Sankaran
Pushed this one too, so just the 3/3 patch should go with Chandan's series
Sean
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 31 ++-
> 1 file changed, 18 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index d39b745..885bf88 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -405,35 +405,38 @@ static void dpu_kms_wait_for_commit_done(struct msm_kms
> *kms,
> }
> }
>
> -static void _dpu_kms_initialize_dsi(struct drm_device *dev,
> +static int _dpu_kms_initialize_dsi(struct drm_device *dev,
> struct msm_drm_private *priv,
> struct dpu_kms *dpu_kms)
> {
> struct drm_encoder *encoder = NULL;
> - int i, rc;
> + int i, rc = 0;
> +
> + if (!(priv->dsi[0] || priv->dsi[1]))
> + return rc;
>
> /*TODO: Support two independent DSI connectors */
> encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_DSI);
> - if (IS_ERR_OR_NULL(encoder)) {
> + if (IS_ERR(encoder)) {
> DPU_ERROR("encoder init failed for dsi display\n");
> - return;
> + return PTR_ERR(encoder);
> }
>
> priv->encoders[priv->num_encoders++] = encoder;
>
> for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) {
> - if (!priv->dsi[i]) {
> - DPU_DEBUG("invalid msm_dsi for ctrl %d\n", i);
> - return;
> - }
> + if (!priv->dsi[i])
> + continue;
>
> rc = msm_dsi_modeset_init(priv->dsi[i], dev, encoder);
> if (rc) {
> DPU_ERROR("modeset_init failed for dsi[%d], rc = %d\n",
> i, rc);
> - continue;
> + break;
> }
> }
> +
> + return rc;
> }
>
> /**
> @@ -444,16 +447,16 @@ static void _dpu_kms_initialize_dsi(struct drm_device
> *dev,
> * @dpu_kms:Pointer to dpu kms structure
> * Returns: Zero on success
> */
> -static void _dpu_kms_setup_displays(struct drm_device *dev,
> +static int _dpu_kms_setup_displays(struct drm_device *dev,
> struct msm_drm_private *priv,
> struct dpu_kms *dpu_kms)
> {
> - _dpu_kms_initialize_dsi(dev, priv, dpu_kms);
> -
> /**
>* Extend this function to initialize other
>* types of displays
>*/
> +
> + return _dpu_kms_initialize_dsi(dev, priv, dpu_kms);
> }
>
> static void _dpu_kms_drm_obj_destroy(struct dpu_kms *dpu_kms)
> @@ -516,7 +519,9 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms)
>* Create encoder and query display drivers to create
>* bridges and connectors
>*/
> - _dpu_kms_setup_displays(dev, priv, dpu_kms);
> + ret = _dpu_kms_setup_displays(dev, priv, dpu_kms);
> + if (ret)
> + goto fail;
>
> max_crtc_count = min(catalog->mixer_count, priv->num_encoders);
>
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
--
Sean Paul, Software Engineer, Google / Chromium OS
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Re: [Freedreno] [DPU PATCH] drm: add definitions for DP Audio/Video compliance tests
On Tue, Jan 01, 2019 at 11:15:25PM -0800, Chandan Uddaraju wrote: This seems fine to me. Could you please: - delete the cover letter - move the cover letter description into the patch commit msg - strip DPU from the subject prefix - send it to dri-devel, maintaining the cc's you have here With that, Reviewed-by: Sean Paul Sean > Signed-off-by: Chandan Uddaraju > --- > include/drm/drm_dp_helper.h | 13 + > 1 file changed, 13 insertions(+) > > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > index 5736c94..e688e05 100644 > --- a/include/drm/drm_dp_helper.h > +++ b/include/drm/drm_dp_helper.h > @@ -556,6 +556,8 @@ > # define DP_TEST_LINK_EDID_READ (1 << 2) > # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ > # define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */ > +# define DP_TEST_LINK_AUDIO_PATTERN (1 << 5) /* DPCD >= 1.2 */ > +# define DP_TEST_LINK_AUDIO_DISABLED_VIDEO (1 << 6) /* DPCD >= 1.2 */ > > #define DP_TEST_LINK_RATE0x219 > # define DP_LINK_RATE_162(0x6) > @@ -604,6 +606,7 @@ > # define DP_COLOR_FORMAT_RGB(0 << 1) > # define DP_COLOR_FORMAT_YCbCr422 (1 << 1) > # define DP_COLOR_FORMAT_YCbCr444 (2 << 1) > +# define DP_TEST_DYNAMIC_RANGE_VESA (0 << 3) > # define DP_TEST_DYNAMIC_RANGE_CEA (1 << 3) > # define DP_TEST_YCBCR_COEFFICIENTS (1 << 4) > # define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4) > @@ -653,6 +656,16 @@ > > #define DP_TEST_SINK 0x270 > # define DP_TEST_SINK_START (1 << 0) > +#define DP_TEST_AUDIO_MODE 0x271 > +#define DP_TEST_AUDIO_PATTERN_TYPE 0x272 > +#define DP_TEST_AUDIO_PERIOD_CH1 0x273 > +#define DP_TEST_AUDIO_PERIOD_CH2 0x274 > +#define DP_TEST_AUDIO_PERIOD_CH3 0x275 > +#define DP_TEST_AUDIO_PERIOD_CH4 0x276 > +#define DP_TEST_AUDIO_PERIOD_CH5 0x277 > +#define DP_TEST_AUDIO_PERIOD_CH6 0x278 > +#define DP_TEST_AUDIO_PERIOD_CH7 0x279 > +#define DP_TEST_AUDIO_PERIOD_CH8 0x27A > > #define DP_FEC_STATUS0x280/* 1.4 */ > # define DP_FEC_DECODE_EN_DETECTED (1 << 0) > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project > > ___ > Freedreno mailing list > Freedreno@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/freedreno -- Sean Paul, Software Engineer, Google / Chromium OS ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
