From: Tim Gardner
[ Upstream commit b220c154832c5cd0df34cbcbcc19d7135c16e823 ]
Coverity complains of a possible NULL dereference:
CID 120718 (#1 of 1): Dereference null return value (NULL_RETURNS)
23. dereference: Dereferencing a pointer that might be NULL state->bos when
calling
On 2021-11-02 16:44, Kuogee Hsieh wrote:
From: Kuogee Hsieh
Signed-off-by: Kuogee Hsieh
---
Anyone has comments on this patch?
Changes in v2:
-- move fixes of dp_phy reg property to other patch
Changes in v3:
-- delete "qcom,sc7180-dp" from msm_dp node
On Mon, Nov 15, 2021 at 6:43 AM Akhil P Oommen wrote:
>
> On 11/12/2021 12:54 AM, Rob Clark wrote:
> > From: Rob Clark
> >
> > When converting to use an idr to map userspace fence seqno values back
> > to a dma_fence, we lost the error return when userspace passes seqno
> > that is larger than
From: Tim Gardner
[ Upstream commit b220c154832c5cd0df34cbcbcc19d7135c16e823 ]
Coverity complains of a possible NULL dereference:
CID 120718 (#1 of 1): Dereference null return value (NULL_RETURNS)
23. dereference: Dereferencing a pointer that might be NULL state->bos when
calling
On 11/6/2021 9:25 AM, Bjorn Andersson wrote:
On Fri 05 Nov 16:22 CDT 2021, Kuogee Hsieh wrote:
Currently the msm_dp_*** functions implement the same sequence which would
happen when drm_bridge is used. hence get rid of this intermediate layer
and align with the drm_bridge usage to avoid
From: Rob Clark
This was the one GPU related kernel buffer which was not given a debug
name. Let's fix that.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 ++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 ++
2 files changed, 4 insertions(+)
diff --git
From: Tim Gardner
[ Upstream commit b220c154832c5cd0df34cbcbcc19d7135c16e823 ]
Coverity complains of a possible NULL dereference:
CID 120718 (#1 of 1): Dereference null return value (NULL_RETURNS)
23. dereference: Dereferencing a pointer that might be NULL state->bos when
calling
On 11/12/2021 12:54 AM, Rob Clark wrote:
From: Rob Clark
When converting to use an idr to map userspace fence seqno values back
to a dma_fence, we lost the error return when userspace passes seqno
that is larger than the last submitted fence. Restore this check.
Reported-by: Akhil P Oommen
Currently the msm_dp_*** functions implement the same sequence which would
happen when drm_bridge is used. hence get rid of this intermediate layer
and align with the drm_bridge usage to avoid customized implementation.
Signed-off-by: Kuogee Hsieh
Changes in v2:
-- revise commit text
-- rename
From: Sean Paul
This patch adds the bindings for the MSM DisplayPort HDCP registers
which are required to write the HDCP key into the display controller as
well as the registers to enable HDCP authentication/key
exchange/encryption.
We'll use a new compatible string for this since the fields
Quoting Douglas Anderson (2021-11-10 11:33:42)
> In commit 510410bfc034 ("drm/msm: Implement mmap as GEM object
> function") we switched to a new/cleaner method of doing things. That's
> good, but we missed a little bit.
>
> Before that commit, we used to _first_ run through the
>
From: Rob Clark
Signed-off-by: Rob Clark
Reviewed-by: Petri Latvala
---
lib/igt_debugfs.c | 17 +
lib/igt_debugfs.h | 13 +
2 files changed, 30 insertions(+)
diff --git a/lib/igt_debugfs.c b/lib/igt_debugfs.c
index a5bb95ca..dd6f2995 100644
--- a/lib/igt_debugfs.c
From: Rob Clark
A pretty minimal subset compared to what a full gallium driver would
need, but OTOH for igt tests we should only need to emit fairly basic
command stream.
Signed-off-by: Rob Clark
---
lib/igt_msm.c | 102 ++
lib/igt_msm.h | 48
From: Rob Clark
Add tests to exercise:
1. sw hangcheck timeout
2. gpu fault (hang) recovery
3. iova fault recovery
Signed-off-by: Rob Clark
---
lib/igt_msm.h| 3 +
tests/meson.build| 1 +
tests/msm_recovery.c | 174 +++
3 files changed,
From: Rob Clark
The first patch adds a easy way to write debugfs files (needed to
disable hw fault detection, so we can test the sw timeout fallback).
The second adds some helpers for cmdstream building. And the third
adds the new tests.
v2: Fix headerdoc comments in first patch
v3: Add helper
From: Rob Clark
Add a helper that can be used with, for ex, igt_require() so that tests
can be skipped if the kernel is too old.
Signed-off-by: Rob Clark
---
lib/igt_debugfs.c | 21 +
lib/igt_debugfs.h | 1 +
2 files changed, 22 insertions(+)
diff --git
Quoting cgel@gmail.com (2021-11-10 04:05:12)
> From: Changcheng Deng
>
> Fix the following coccicheck review:
> ./drivers/gpu/drm/msm/dp/dp_debug.c: Unneeded variable
>
> Remove unneeded variable used to store return value.
>
> Reported-by: Zeal Robot
> Signed-off-by: Changcheng Deng
> ---
Quoting Kuogee Hsieh (2021-11-02 16:44:33)
> From: Kuogee Hsieh
>
> Signed-off-by: Kuogee Hsieh
> ---
What tree is this based on? I don't see edp_phy upstream for sc7280
Otherwise, looks good to me.
Reviewed-by: Stephen Boyd
On 2021-11-09 13:38, Kuogee Hsieh wrote:
From: Kuogee Hsieh
Current DP drivers have regulators, clocks, irq and phy are grouped
together within a function and executed not in a symmetric manner.
This increase difficulty of code maintenance and limited code
scalability.
This patch divided the
When DSC is enabled, we need to configure DSI registers accordingly and
configure the respective stream compression registers.
Add support to calculate the register setting based on DSC params and
timing information and configure these registers.
Signed-off-by: Vinod Koul
---
When DSC is enabled, we need to pass the DSC parameters to panel driver
as well, so add a dsc parameter in panel and set it when DSC is enabled
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 16 +++-
include/drm/drm_panel.h| 7 +++
2 files
On Mon, Nov 15, 2021 at 04:30:40PM -0800, Rob Clark wrote:
> From: Rob Clark
>
> Add a helper that can be used with, for ex, igt_require() so that tests
> can be skipped if the kernel is too old.
>
> Signed-off-by: Rob Clark
Reviewed-by: Petri Latvala
> ---
> lib/igt_debugfs.c | 21
Display Stream Compression (DSC) compresses the display stream in host which
is later decoded by panel. This series enables this for Qualcomm msm driver.
This was tested on Google Pixel3 phone which use LGE SW43408 panel.
The changes include DSC data and hardware block enabling for DPU1 then
On 11/15/2021 10:26 PM, Rob Clark wrote:
On Mon, Nov 15, 2021 at 6:43 AM Akhil P Oommen wrote:
On 11/12/2021 12:54 AM, Rob Clark wrote:
From: Rob Clark
When converting to use an idr to map userspace fence seqno values back
to a dma_fence, we lost the error return when userspace passes
This series adds support for the eDP PHY on Qualcomm SC7280 platform.
The changes are dependent on v4 of the new eDP PHY driver introduced by Bjorn:
https://patchwork.kernel.org/project/linux-arm-msm/list/?series=575135
Sankeerth Billakanti (3):
dt-bindings: phy: Add eDP PHY compatible for
The sc7280 platform supports native eDP controller and PHY.
This change will add support for the eDP PHY on sc7280.
Signed-off-by: Sankeerth Billakanti
---
drivers/phy/qualcomm/phy-qcom-edp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c
Some legacy eDP sinks may not support SSC. The support for SSC is
indicated through an opts flag from the controller driver. This
change will enable SSC only if the sink supports it.
Signed-off-by: Sankeerth Billakanti
---
drivers/phy/qualcomm/phy-qcom-edp.c | 8 +---
1 file changed, 5
Add compatible string for the supported eDP PHY on sc7280 platform.
Signed-off-by: Sankeerth Billakanti
---
Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
We need to configure the encoder for DSC configuration and calculate DSC
parameters for the given timing so this patch adds that support by
adding dpu_encoder_prep_dsc() which is invoked when DSC is enabled.
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 140
Display Stream Compression (DSC) is one of the hw blocks in dpu, so add
support by adding hw blocks for DSC
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/Makefile | 1 +
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 13 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
Display Stream Compression (DSC) parameters need to be calculated. Add
helpers and struct msm_display_dsc_config in msm_drv for this
msm_display_dsc_config uses drm_dsc_config for DSC parameters.
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 132
This add the bits in RM to enable the DSC blocks
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 66 +
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 1 +
3 files changed, 68 insertions(+)
diff --git
We cannot enable mode_3d when we are using the DSC. So pass
configuration to detect DSC is enabled and not enable mode_3d
when we are using DSC
We add a helper dpu_encoder_helper_get_dsc() to detect dsc
enabled and pass this to .setup_intf_cfg()
Signed-off-by: Vinod Koul
---
Later gens of hardware have DSC bits moved to hw_ctl, so configure these
bits so that DSC would work there as well
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git
In SDM845, DSC can be enabled by writing to pingpong block registers, so
add support for DSC in hw_pp
Reviewed-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Vinod Koul
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 32 +++
This adds SDM845 DSC blocks into hw_catalog
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Vinod Koul
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 20 +++
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
Somehow documentation for dspp was missed, so add that
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/msm_drv.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index de7cb65bfc52..c4a588ad226e 100644
---
For DSC to work we typically need a 2,2,1 configuration. This should
suffice for resolutions up to 4k. For more resolutions like 8k this won't
work.
Also, it is better to use 2 LMs and DSC instances as half width results
in lesser power consumption as compared to single LM, DSC at full width.
Add a mode valid callback for dsi_mgr for checking mode being valid in
case of DSC. For DSC the height and width needs to be multiple of slice,
so we check that here
Signed-off-by: Vinod Koul
---
drivers/gpu/drm/msm/dsi/dsi.h | 2 ++
drivers/gpu/drm/msm/dsi/dsi_host.c| 26
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