Re: [Freedreno] [DPU PATCH v3 1/5] dt-bindings: msm/dp: add bindings of DP/DP-PLL driver for Snapdragon 845
On Mon, Dec 2, 2019 at 6:48 AM Chandan Uddaraju wrote: > > Add bindings for Snapdragon 845 DisplayPort and > display-port PLL driver. > > Changes in V2: > Provide details about sel-gpio > > Signed-off-by: Chandan Uddaraju > --- > .../devicetree/bindings/display/msm/dp.txt | 249 > + > .../devicetree/bindings/display/msm/dpu.txt| 16 +- > 2 files changed, 261 insertions(+), 4 deletions(-) > create mode 100644 Documentation/devicetree/bindings/display/msm/dp.txt > > diff --git a/Documentation/devicetree/bindings/display/msm/dp.txt > b/Documentation/devicetree/bindings/display/msm/dp.txt > new file mode 100644 > index 000..38be36d > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/msm/dp.txt > @@ -0,0 +1,249 @@ > +Qualcomm Technologies, Inc. > +DP is the master Display Port device which supports DP host controllers that > are compatible with VESA Display Port interface specification. > +DP Controller: Required properties: > +- compatible: Should be "qcom,dp-display". > +- reg: Base address and length of DP hardware's memory > mapped regions. > +- cell-index: Specifies the controller instance. > +- reg-names:A list of strings that name the list of regs. > + "dp_ahb" - DP controller memory region. > + "dp_aux" - DP AUX memory region. > + "dp_link" - DP link layer memory region. > + "dp_p0" - DP pixel clock domain memory region. > + "dp_phy" - DP PHY memory region. > + "dp_ln_tx0" - USB3 DP PHY combo TX-0 lane memory > region. > + "dp_ln_tx1" - USB3 DP PHY combo TX-1 lane memory > region. > + "dp_mmss_cc" - Display Clock Control memory region. > + "qfprom_physical" - QFPROM Phys memory region. > + "dp_pll" - USB3 DP combo PLL memory region. > + "usb3_dp_com" - USB3 DP PHY combo memory region. > + "hdcp_physical" - DP HDCP memory region. > +- interrupt-parent phandle to the interrupt parent device node. > +- interrupts: The interrupt signal from the DP block. > +- clocks: Clocks required for Display Port operation. See [1] > for details on clock bindings. > +- clock-names: Names of the clocks corresponding to handles. > Following clocks are required: > + "core_aux_clk", > "core_usb_ref_clk_src","core_usb_ref_clk", "core_usb_cfg_ahb_clk", > + "core_usb_pipe_clk", "ctrl_link_clk", > "ctrl_link_iface_clk", "ctrl_crypto_clk", > + "ctrl_pixel_clk", "pixel_clk_rcg", "pixel_parent". > +- pll-node:phandle to DP PLL node. > +- vdda-1p2-supply: phandle to vdda 1.2V regulator node. > +- vdda-0p9-supply: phandle to vdda 0.9V regulator node. > +- qcom,aux-cfg0-settings: Specifies the DP AUX configuration 0 > settings. The first > + entry in this array corresponds to > the register offset > + within DP AUX, while the remaining > entries indicate the > + programmable values. > +- qcom,aux-cfg1-settings: Specifies the DP AUX configuration 1 > settings. The first > + entry in this array corresponds to > the register offset > + within DP AUX, while the remaining > entries indicate the > + programmable values. > +- qcom,aux-cfg2-settings: Specifies the DP AUX configuration 2 > settings. The first > + entry in this array corresponds to > the register offset > + within DP AUX, while the remaining > entries indicate the > + programmable values. > +- qcom,aux-cfg3-settings: Specifies the DP AUX configuration 3 > settings. The first > + entry in this array corresponds to > the register offset > + within DP AUX, while the remaining > entries indicate the > + programmable values. > +- qcom,aux-cfg4-settings: Specifies the DP AUX configuration 4 > settings. The first > + entry in this array corresponds to > the register offset > + within DP AUX, while the remaining > entries indicate the > + programmable values. > +- qcom,aux-cfg5-settings: Specifies the DP AUX configuration 5 > settings. The first > + entry in this array corresponds to >
Re: [Freedreno] [DPU PATCH v3 1/5] dt-bindings: msm/dp: add bindings of DP/DP-PLL driver for Snapdragon 845
On Mon, Dec 02, 2019 at 01:47:45PM +, Chandan Uddaraju wrote: > Add bindings for Snapdragon 845 DisplayPort and > display-port PLL driver. Is it just me, but I keep getting 2 copies of codeaurora emails? > > Changes in V2: > Provide details about sel-gpio This is V3, what changed in V3? > > Signed-off-by: Chandan Uddaraju > --- > .../devicetree/bindings/display/msm/dp.txt | 249 > + > .../devicetree/bindings/display/msm/dpu.txt| 16 +- > 2 files changed, 261 insertions(+), 4 deletions(-) > create mode 100644 Documentation/devicetree/bindings/display/msm/dp.txt New bindings should be in DT schema format. > diff --git a/Documentation/devicetree/bindings/display/msm/dp.txt > b/Documentation/devicetree/bindings/display/msm/dp.txt > new file mode 100644 > index 000..38be36d > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/msm/dp.txt > @@ -0,0 +1,249 @@ > +Qualcomm Technologies, Inc. > +DP is the master Display Port device which supports DP host controllers that > are compatible with VESA Display Port interface specification. > +DP Controller: Required properties: > +- compatible: Should be "qcom,dp-display". Needs to be more specific like including the SoC name. > +- reg: Base address and length of DP hardware's memory > mapped regions. > +- cell-index: Specifies the controller instance. FDT doesn't use cell-index. > +- reg-names:A list of strings that name the list of regs. > + "dp_ahb" - DP controller memory region. > + "dp_aux" - DP AUX memory region. > + "dp_link" - DP link layer memory region. > + "dp_p0" - DP pixel clock domain memory region. > + "dp_phy" - DP PHY memory region. > + "dp_ln_tx0" - USB3 DP PHY combo TX-0 lane memory region. > + "dp_ln_tx1" - USB3 DP PHY combo TX-1 lane memory region. > + "dp_mmss_cc" - Display Clock Control memory region. Sounds like a separate clock controller node... > + "qfprom_physical" - QFPROM Phys memory region. > + "dp_pll" - USB3 DP combo PLL memory region. > + "usb3_dp_com" - USB3 DP PHY combo memory region. Should be a separate phy node? > + "hdcp_physical" - DP HDCP memory region. The 'dp_' part is redundant. What does 'physical' mean? Addresses in DT are always physical. > +- interrupt-parent phandle to the interrupt parent device node. Don't document interrupt-parent. It's not required either because it could be in a parent node. > +- interrupts:The interrupt signal from the DP block. > +- clocks: Clocks required for Display Port operation. See [1] > for details on clock bindings. > +- clock-names: Names of the clocks corresponding to handles. > Following clocks are required: > + "core_aux_clk", > "core_usb_ref_clk_src","core_usb_ref_clk", "core_usb_cfg_ahb_clk", > + "core_usb_pipe_clk", "ctrl_link_clk", > "ctrl_link_iface_clk", "ctrl_crypto_clk", > + "ctrl_pixel_clk", "pixel_clk_rcg", "pixel_parent". Clocks should be actual clock inputs to the module. If 'pixel_parent' is just some parent clock you want to assign, then use assigned-clocks. > +- pll-node: phandle to DP PLL node. But you have a DP PLL reg region defined. Is this something else? Needs a 'qcom' prefix if it stays. > +- vdda-1p2-supply: phandle to vdda 1.2V regulator node. > +- vdda-0p9-supply: phandle to vdda 0.9V regulator node. > +- qcom,aux-cfg0-settings:Specifies the DP AUX configuration 0 > settings. The first > + entry in this array corresponds to the > register offset > + within DP AUX, while the remaining > entries indicate the > + programmable values. Needs more details on what these are and why they must be in DT. We generally don't just stuff DT with raw values to initial registers with. Line lengths should be <80 char. > +- qcom,aux-cfg1-settings:Specifies the DP AUX configuration 1 > settings. The first > + entry in this array corresponds to the > register offset > + within DP AUX, while the remaining > entries indicate the > + programmable values. > +- qcom,aux-cfg2-settings:Specifies the DP AUX configuration 2 > settings. The first > + entry in this array corresponds to the > register offset > + within DP AUX, while the remaining > entries indicate the > + programmable values. > +- qcom,aux-cfg3-settings:
Re: [Freedreno] [PATCH v1 1/2] dt-bindings: display: add sc7180 panel variant
On Fri, Nov 29, 2019 at 12:25:44PM +0530, Harigovindan P wrote:
> Add a compatible string to support sc7180 panel version.
>
> Signed-off-by: Harigovindan P
> ---
> .../bindings/display/visionox,rm69299.txt | 68
> ++
> 1 file changed, 68 insertions(+)
> create mode 100755
> Documentation/devicetree/bindings/display/visionox,rm69299.txt
Source files should not have execute permission.
New bindings should be in DT schema format.
checkpatch.pl will tell you both of these things.
>
> diff --git a/Documentation/devicetree/bindings/display/visionox,rm69299.txt
> b/Documentation/devicetree/bindings/display/visionox,rm69299.txt
> new file mode 100755
> index 000..4622191
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/visionox,rm69299.txt
> @@ -0,0 +1,68 @@
> +Visionox model RM69299 DSI display driver
> +
> +The Visionox RM69299 is a generic display driver, currently only configured
> +for use in the 1080p display on the Qualcomm SC7180 MTP board.
> +
> +Required properties:
> +- compatible: should be "visionox,rm69299-1080p-display"
RM69299 may be generic, but 1080p sounds like a specific panel.
Is there anything besides a 'display'? If not, '-display' is redundant.
> +- vdda-supply: phandle of the regulator that provides the supply voltage
> + Power IC supply
> +- vdd3p3-supply: phandle of the regulator that provides the supply voltage
> + Power IC supply
> +- reset-gpios: phandle of gpio for reset line
> + This should be 8mA, gpio can be configured using mux, pinctrl,
> pinctrl-names
> + (active low)
> +- mode-gpios: phandle of the gpio for choosing the mode of the display
> + for single DSI
The modes are what?
> +- ports: This device has one video port driven by one DSI. Their connections
> + are modeled using the OF graph bindings specified in
> + Documentation/devicetree/bindings/graph.txt.
> + - port@0: DSI input port driven by master DSI
> +
> +Example:
> +
> + dsi@ae94000 {
> + panel@0 {
> + compatible = "visionox,rm69299-1080p-display";
> + reg = <0>;
> +
> + vdda-supply = <_pp1800_l8c>;
> + vdd3p3-supply = <_pp2800_l18a>;
> +
> + pinctrl-names = "default", "suspend";
> + pinctrl-0 = <_pins_default>;
> + pinctrl-1 = <_pins_default>;
> +
> + reset-gpios = <_gpios 3 0>;
> +
> + display-timings {
> + timing0: timing-0 {
> + /* originally
> + * 268316160 Mhz,
> + * but value below fits
> + * better w/ downstream
> + */
> + clock-frequency = <158695680>;
> + hactive = <1080>;
> + vactive = <2248>;
> + hfront-porch = <26>;
> + hback-porch = <36>;
> + hsync-len = <2>;
> + vfront-porch = <56>;
> + vback-porch = <4>;
> + vsync-len = <4>;
> + };
> + };
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + port@0 {
> + reg = <0>;
> + panel0_in: endpoint {
> + remote-endpoint = <_out>;
> + };
> + };
> + };
> + };
> + };
> --
> 2.7.4
>
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Re: [Freedreno] [PATCH 3/4] drm/msm: Use dma_resv locking wrappers
On Fri, Dec 13, 2019 at 12:08 PM Daniel Vetter wrote:
>
> On Mon, Nov 25, 2019 at 10:43:55AM +0100, Daniel Vetter wrote:
> > I'll add more fancy logic to them soon, so everyone really has to use
> > them. Plus they already provide some nice additional debug
> > infrastructure on top of direct ww_mutex usage for the fences tracked
> > by dma_resv.
> >
> > Signed-off-by: Daniel Vetter
> > Cc: Rob Clark
> > Cc: Sean Paul
> > Cc: linux-arm-...@vger.kernel.org
> > Cc: freedreno@lists.freedesktop.org
>
> Ping for some review/acks.
>
> Thanks, Daniel
>
> > ---
> > drivers/gpu/drm/msm/msm_gem_submit.c | 10 +-
> > 1 file changed, 5 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c
> > b/drivers/gpu/drm/msm/msm_gem_submit.c
> > index 7d04c47d0023..385d4965a8d0 100644
> > --- a/drivers/gpu/drm/msm/msm_gem_submit.c
> > +++ b/drivers/gpu/drm/msm/msm_gem_submit.c
> > @@ -157,7 +157,7 @@ static void submit_unlock_unpin_bo(struct
> > msm_gem_submit *submit,
> > msm_gem_unpin_iova(_obj->base, submit->aspace);
> >
> > if (submit->bos[i].flags & BO_LOCKED)
> > - ww_mutex_unlock(_obj->base.resv->lock);
> > + dma_resv_unlock(msm_obj->base.resv);
> >
> > if (backoff && !(submit->bos[i].flags & BO_VALID))
> > submit->bos[i].iova = 0;
> > @@ -180,8 +180,8 @@ static int submit_lock_objects(struct msm_gem_submit
> > *submit)
> > contended = i;
> >
> > if (!(submit->bos[i].flags & BO_LOCKED)) {
> > - ret =
> > ww_mutex_lock_interruptible(_obj->base.resv->lock,
> > - >ticket);
> > + ret = dma_resv_lock_interruptible(msm_obj->base.resv,
> > + >ticket);
> > if (ret)
> > goto fail;
> > submit->bos[i].flags |= BO_LOCKED;
> > @@ -202,8 +202,8 @@ static int submit_lock_objects(struct msm_gem_submit
> > *submit)
> > if (ret == -EDEADLK) {
> > struct msm_gem_object *msm_obj = submit->bos[contended].obj;
> > /* we lost out in a seqno race, lock and retry.. */
> > - ret =
> > ww_mutex_lock_slow_interruptible(_obj->base.resv->lock,
> > - >ticket);
> > + ret = dma_resv_lock_slow_interruptible(msm_obj->base.resv,
> > +>ticket);
> > if (!ret) {
> > submit->bos[contended].flags |= BO_LOCKED;
> > slow_locked = contended;
> > --
> > 2.24.0
> >
Reviewed-by: Eric Anholt
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[Freedreno] [PATCH v2 00/24] drivers, fs: y2038 updates
These are updates to devidce drivers and file systems that for some reason or another were not included in the kernel in the previous y2038 series. I've gone through all users of time_t again to make sure the kernel is in a long-term maintainable state. Posting these as a series for better organization, but each change here is applicable standalone. Please merge, review, ack/nack etc as you see fit. I will add these to my y2038 branch [1] for linux-next, but can keep rebasing for feedback and to remove any patches that get picked up by a maintainer. Changes since v1 [2]: - Add Acks I received - Rebase to v5.5-rc1, droping patches that got merged already - Add NFS, XFS and the final three patches from another series - Rewrite etnaviv patches Arnd [1] https://git.kernel.org/pub/scm/linux/kernel/git/arnd/playground.git/log/?h=y2038 [2] https://lore.kernel.org/lkml/20191108213257.3097633-1-a...@arndb.de/ Arnd Bergmann (24): Input: input_event: fix struct padding on sparc64 fat: use prandom_u32() for i_generation dlm: use SO_SNDTIMEO_NEW instead of SO_SNDTIMEO_OLD xtensa: ISS: avoid struct timeval um: ubd: use 64-bit time_t where possible acct: stop using get_seconds() tsacct: add 64-bit btime field packet: clarify timestamp overflow quota: avoid time_t in v1_disk_dqblk definition hostfs: pass 64-bit timestamps to/from user space hfs/hfsplus: use 64-bit inode timestamps drm/msm: avoid using 'timespec' drm/etnaviv: reject timeouts with tv_nsec >= NSEC_PER_SEC drm/etnaviv: avoid deprecated timespec sunrpc: convert to time64_t for expiry nfs: use time64_t internally nfs: fix timstamp debug prints nfs: fscache: use timespec64 in inode auxdata xfs: rename compat_time_t to old_time32_t xfs: disallow broken ioctls without compat-32-bit-time xfs: quota: move to time64_t interfaces y2038: remove obsolete jiffies conversion functions y2038: rename itimerval to __kernel_old_itimerval y2038: sparc: remove use of struct timex arch/sparc/kernel/sys_sparc_64.c | 29 +- arch/um/drivers/cow.h | 2 +- arch/um/drivers/cow_user.c| 7 ++- arch/um/drivers/ubd_kern.c| 10 ++-- arch/um/include/shared/os.h | 2 +- arch/um/os-Linux/file.c | 2 +- .../platforms/iss/include/platform/simcall.h | 4 +- drivers/gpu/drm/etnaviv/etnaviv_drv.c | 20 --- drivers/gpu/drm/etnaviv/etnaviv_drv.h | 11 ++-- drivers/gpu/drm/etnaviv/etnaviv_gem.c | 4 +- drivers/gpu/drm/etnaviv/etnaviv_gem.h | 2 +- drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 5 +- drivers/gpu/drm/etnaviv/etnaviv_gpu.h | 5 +- drivers/gpu/drm/msm/msm_drv.h | 3 +- drivers/input/evdev.c | 14 ++--- drivers/input/misc/uinput.c | 14 +++-- fs/dlm/lowcomms.c | 6 +- fs/fat/inode.c| 3 +- fs/hfs/hfs_fs.h | 28 +++-- fs/hfs/inode.c| 4 +- fs/hfsplus/hfsplus_fs.h | 28 +++-- fs/hfsplus/inode.c| 12 ++-- fs/hostfs/hostfs.h| 22 --- fs/hostfs/hostfs_kern.c | 15 +++-- fs/nfs/fscache-index.c| 6 +- fs/nfs/fscache.c | 18 -- fs/nfs/fscache.h | 8 ++- fs/nfs/nfs4xdr.c | 10 ++-- fs/quota/quotaio_v1.h | 6 +- fs/xfs/xfs_dquot.c| 6 +- fs/xfs/xfs_ioctl.c| 26 + fs/xfs/xfs_ioctl32.c | 2 +- fs/xfs/xfs_ioctl32.h | 2 +- fs/xfs/xfs_qm.h | 6 +- fs/xfs/xfs_quotaops.c | 6 +- fs/xfs/xfs_trans_dquot.c | 8 ++- include/linux/jiffies.h | 20 --- include/linux/sunrpc/cache.h | 42 -- include/linux/sunrpc/gss_api.h| 4 +- include/linux/sunrpc/gss_krb5.h | 2 +- include/linux/syscalls.h | 9 ++- include/uapi/linux/acct.h | 2 + include/uapi/linux/input.h| 1 + include/uapi/linux/taskstats.h| 6 +- include/uapi/linux/time_types.h | 5 ++ include/uapi/linux/timex.h| 2 + kernel/acct.c | 4 +- kernel/time/itimer.c | 18 +++--- kernel/time/time.c| 58 ++- kernel/tsacct.c | 9 ++- net/packet/af_packet.c| 27 + net/sunrpc/auth_gss/gss_krb5_mech.c | 12 +++-
[Freedreno] [PATCH v2 12/24] drm/msm: avoid using 'timespec'
The timespec structure and associated interfaces are deprecated and will
be removed in the future because of the y2038 overflow.
The use of ktime_to_timespec() in timeout_to_jiffies() does not
suffer from that overflow, but is easy to avoid by just converting
the ktime_t into jiffies directly.
Reviewed-by: Jordan Crouse
Signed-off-by: Arnd Bergmann
---
drivers/gpu/drm/msm/msm_drv.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 71547e756e29..740bf7c70d8f 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -454,8 +454,7 @@ static inline unsigned long timeout_to_jiffies(const
ktime_t *timeout)
remaining_jiffies = 0;
} else {
ktime_t rem = ktime_sub(*timeout, now);
- struct timespec ts = ktime_to_timespec(rem);
- remaining_jiffies = timespec_to_jiffies();
+ remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ);
}
return remaining_jiffies;
--
2.20.0
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Re: [Freedreno] [PATCH 3/4] drm/msm: Use dma_resv locking wrappers
On Mon, Nov 25, 2019 at 10:43:55AM +0100, Daniel Vetter wrote:
> I'll add more fancy logic to them soon, so everyone really has to use
> them. Plus they already provide some nice additional debug
> infrastructure on top of direct ww_mutex usage for the fences tracked
> by dma_resv.
>
> Signed-off-by: Daniel Vetter
> Cc: Rob Clark
> Cc: Sean Paul
> Cc: linux-arm-...@vger.kernel.org
> Cc: freedreno@lists.freedesktop.org
Ping for some review/acks.
Thanks, Daniel
> ---
> drivers/gpu/drm/msm/msm_gem_submit.c | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c
> b/drivers/gpu/drm/msm/msm_gem_submit.c
> index 7d04c47d0023..385d4965a8d0 100644
> --- a/drivers/gpu/drm/msm/msm_gem_submit.c
> +++ b/drivers/gpu/drm/msm/msm_gem_submit.c
> @@ -157,7 +157,7 @@ static void submit_unlock_unpin_bo(struct msm_gem_submit
> *submit,
> msm_gem_unpin_iova(_obj->base, submit->aspace);
>
> if (submit->bos[i].flags & BO_LOCKED)
> - ww_mutex_unlock(_obj->base.resv->lock);
> + dma_resv_unlock(msm_obj->base.resv);
>
> if (backoff && !(submit->bos[i].flags & BO_VALID))
> submit->bos[i].iova = 0;
> @@ -180,8 +180,8 @@ static int submit_lock_objects(struct msm_gem_submit
> *submit)
> contended = i;
>
> if (!(submit->bos[i].flags & BO_LOCKED)) {
> - ret =
> ww_mutex_lock_interruptible(_obj->base.resv->lock,
> - >ticket);
> + ret = dma_resv_lock_interruptible(msm_obj->base.resv,
> + >ticket);
> if (ret)
> goto fail;
> submit->bos[i].flags |= BO_LOCKED;
> @@ -202,8 +202,8 @@ static int submit_lock_objects(struct msm_gem_submit
> *submit)
> if (ret == -EDEADLK) {
> struct msm_gem_object *msm_obj = submit->bos[contended].obj;
> /* we lost out in a seqno race, lock and retry.. */
> - ret =
> ww_mutex_lock_slow_interruptible(_obj->base.resv->lock,
> - >ticket);
> + ret = dma_resv_lock_slow_interruptible(msm_obj->base.resv,
> +>ticket);
> if (!ret) {
> submit->bos[contended].flags |= BO_LOCKED;
> slow_locked = contended;
> --
> 2.24.0
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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