On 2020-09-28 17:19, Rob Clark wrote:
From: Rob Clark
Neither of these code-paths apply to older 32b devices, but it is rude
to introduce warnings.
Signed-off-by: Rob Clark
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +-
From: Rob Clark
Neither of these code-paths apply to older 32b devices, but it is rude
to introduce warnings.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +-
drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff
Quoting Kuogee Hsieh (2020-09-26 13:34:54)
> At dp_pm_resume, reinitialize both dp host controller and hpd block
dp_pm_resume()
> so that hpd connection can be detected at realtime by reading hpd state
> status register. Also hpd plug interrupt can be generated accordingly.
Can you describe
Assuming I merged it right,
32-bit builds adds warning
In file included from
/home/airlied/devel/kernel/dim/src/include/linux/bitops.h:5,
from
/home/airlied/devel/kernel/dim/src/include/linux/kernel.h:12,
from
From: AngeloGioacchino Del Regno
The Adreno 508/509/512 GPUs are stripped versions of the Adreno
5xx found in the mid-end SoCs such as SDM630, SDM636, SDM660 and
SDA variants; these SoCs are usually provided with ZAP firmwares,
but they have no available GPMU.
Signed-off-by: AngeloGioacchino
From: Konrad Dybcio
Port over the command from downstream to prevent undefined
behaviour.
Signed-off-by: Konrad Dybcio
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/adreno/a5xx.xml.h | 2 ++
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 3 +++
2 files changed, 5 insertions(+)
From: Konrad Dybcio
The upstream API for some reason uses logbase2 instead of
just passing the argument as-is, whereas downstream CAF
kernel does the latter.
Hence, a mistake has been made when porting:
4 is the value that's supposed to be passed, but
log2(4) = 2. Changing the value to 16 (=
From: AngeloGioacchino Del Regno
The "main" if branch where we program the other registers for the
Adreno 5xx family of GPUs should not contain the PC_DBG_ECO_CNTL
register programming because this has logical similarity
differences from all the others.
A later commit will show the entire sense
From: AngeloGioacchino Del Regno
Resetting the VBIF before power collapse is done to avoid getting
bogus FIFO entries during the suspend sequence or subsequent resume,
but this is doable only on Adreno 510 and Adreno 530, as the other
units will tendentially lock up.
Especially on Adreno 508,
From: Konrad Dybcio
Port over the command from downstream to prevent undefined
behaviour.
Signed-off-by: Konrad Dybcio
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
From: AngeloGioacchino Del Regno
The PC_DBG_ECO_CNTL register on the Adreno A5xx family gets
programmed to some different values on a per-model basis.
At least, this is what we intend to do here;
Unfortunately, though, this register is being overwritten with a
static magic number, right after
From: AngeloGioacchino Del Regno
In this patch series, we are adding support for lower end Adreno 5
series GPUs, such as A508, A509 and A512 that we have found in the
Qualcomm SDM630, SDM636 and SDM660 SoCs.
On a note, adding support for these three units, also adds 99% of
the required "things"
Il giorno lun 28 set 2020 alle ore 18:16 Jordan Crouse
ha scritto:
>
> On Sat, Sep 26, 2020 at 02:51:44PM +0200, khol...@gmail.com wrote:
> > From: Konrad Dybcio
> >
> > The upstream API for some reason uses logbase2 instead of
> > just passing the argument as-is, whereas downstream CAF
> >
On 2020-09-28 12:16, Stephen Boyd wrote:
Printk messages need newlines. Add it here.
Cc: Abhinav Kumar
Cc: Jeykumar Sankaran
Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support")
Signed-off-by: Stephen Boyd
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 4
Printk messages need newlines. Add it here.
Cc: Abhinav Kumar
Cc: Jeykumar Sankaran
Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support")
Signed-off-by: Stephen Boyd
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
On 2020-09-28 21:41, Jordan Crouse wrote:
On Mon, Sep 28, 2020 at 05:56:55PM +0530, Sai Prakash Ranjan wrote:
Hi Jordan,
On 2020-09-23 20:33, Jordan Crouse wrote:
>On Tue, Sep 22, 2020 at 11:48:17AM +0530, Sai Prakash Ranjan wrote:
>>From: Sharat Masetty
>>
>>The last level system cache can
On Sat, Sep 26, 2020 at 02:51:43PM +0200, khol...@gmail.com wrote:
> From: AngeloGioacchino Del Regno
>
> Resetting the VBIF before power collapse is done to avoid getting
> bogus FIFO entries during the suspend sequence or subsequent resume,
> but this is doable only on Adreno 510 and Adreno
On Sat, Sep 26, 2020 at 02:51:42PM +0200, khol...@gmail.com wrote:
> From: AngeloGioacchino Del Regno
>
> The Adreno 508/509/512 GPUs are stripped versions of the Adreno
> 5xx found in the mid-end SoCs such as SDM630, SDM636, SDM660 and
> SDA variants; these SoCs are usually provided with ZAP
On Sat, Sep 26, 2020 at 02:51:41PM +0200, khol...@gmail.com wrote:
> From: AngeloGioacchino Del Regno
>
> The "main" if branch where we program the other regsiters for the
Nit - regsiters -> registers
> Adreno 5xx family of GPUs should not contain the PC_DBG_ECO_CNTL
> register programming
On Sat, Sep 26, 2020 at 02:51:40PM +0200, khol...@gmail.com wrote:
> From: AngeloGioacchino Del Regno
>
> The PC_DBG_ECO_CNTL register on the Adreno A5xx family gets
> programmed to some different values on a per-model basis.
> At least, this is what we intend to do here;
>
> Unfortunately,
On Sat, Sep 26, 2020 at 02:51:44PM +0200, khol...@gmail.com wrote:
> From: Konrad Dybcio
>
> The upstream API for some reason uses logbase2 instead of
> just passing the argument as-is, whereas downstream CAF
> kernel does the latter.
>
> Hence, a mistake has been made when porting:
> 4 is the
On Mon, Sep 28, 2020 at 05:56:55PM +0530, Sai Prakash Ranjan wrote:
> Hi Jordan,
>
> On 2020-09-23 20:33, Jordan Crouse wrote:
> >On Tue, Sep 22, 2020 at 11:48:17AM +0530, Sai Prakash Ranjan wrote:
> >>From: Sharat Masetty
> >>
> >>The last level system cache can be partitioned to 32 different
>
On 2020-09-23 20:54, Robin Murphy wrote:
On 2020-09-22 07:18, Sai Prakash Ranjan wrote:
Use table and of_match_node() to match qcom implementation
instead of multiple of_device_compatible() calls for each
QCOM SMMU implementation.
Signed-off-by: Sai Prakash Ranjan
---
Hi Jordan,
On 2020-09-23 20:33, Jordan Crouse wrote:
On Tue, Sep 22, 2020 at 11:48:17AM +0530, Sai Prakash Ranjan wrote:
From: Sharat Masetty
The last level system cache can be partitioned to 32 different
slices of which GPU has two slices preallocated. One slice is
used for caching GPU
24 matches
Mail list logo
