date:20220601

Re: [Freedreno] [PATCH v1 5/5] drm/msm/dpu: make dpu hardware catalog static const

2022-06-01 Thread kernel test robot

Hi Dmitry,

I love your patch! Yet something to improve:

[auto build test ERROR on drm/drm-next]
[also build test ERROR on next-20220601]
[cannot apply to v5.18]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:
https://github.com/intel-lab-lkp/linux/commits/Dmitry-Baryshkov/drm-msm-clean-up-the-hw-catalog-init/20220601-231925
base:   git://anongit.freedesktop.org/drm/drm drm-next
config: arm64-randconfig-r003-20220531 
(https://download.01.org/0day-ci/archive/20220602/202206020857.gd3c79od-...@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 
c825abd6b0198fb088d9752f556a70705bc99dfd)
reproduce (this is a W=1 build):
wget 
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm64 cross compiling tool for clang build
# apt-get install binutils-aarch64-linux-gnu
# 
https://github.com/intel-lab-lkp/linux/commit/ae9332859e2098bf10e3c915aa912fc851b7541c
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review 
Dmitry-Baryshkov/drm-msm-clean-up-the-hw-catalog-init/20220601-231925
git checkout ae9332859e2098bf10e3c915aa912fc851b7541c
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 
O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/gpu/drm/msm/

If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot 

All errors (new ones prefixed by >>):

>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c:1747:10: error: initializer 
>> element is not a compile-time constant
   .perf = msm8998_perf_data,
   ^
   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c:1770:13: error: initializer 
element is not a compile-time constant
   .dma_cfg = sdm845_regdma,
  ^
   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c:1794:13: error: initializer 
element is not a compile-time constant
   .dma_cfg = sdm845_regdma,
  ^
   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c:1820:13: error: initializer 
element is not a compile-time constant
   .dma_cfg = sm8150_regdma,
  ^
   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c:1844:13: error: initializer 
element is not a compile-time constant
   .dma_cfg = sm8150_regdma,
  ^
   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c:1872:13: error: initializer 
element is not a compile-time constant
   .dma_cfg = sm8250_regdma,
  ^
   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c:1893:10: error: initializer 
element is not a compile-time constant
   .perf = sc7280_perf_data,
   ^~~~
   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c:1916:13: error: initializer 
element is not a compile-time constant
   .dma_cfg = sdm845_regdma,
  ^
   8 errors generated.


vim +1747 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c

591e34a091d17df Krishna Manikandan 2021-04-06  1702  
5334087ee7438fa Loic Poulain   2022-02-14  1703  static const 
struct dpu_perf_cfg qcm2290_perf_data = {
5334087ee7438fa Loic Poulain   2022-02-14  1704 .max_bw_low = 
270,
5334087ee7438fa Loic Poulain   2022-02-14  1705 .max_bw_high = 
270,
5334087ee7438fa Loic Poulain   2022-02-14  1706 .min_core_ib = 
130,
5334087ee7438fa Loic Poulain   2022-02-14  1707 .min_llcc_ib = 
0,
5334087ee7438fa Loic Poulain   2022-02-14  1708 .min_dram_ib = 
160,
5334087ee7438fa Loic Poulain   2022-02-14  1709 
.min_prefill_lines = 24,
5334087ee7438fa Loic Poulain   2022-02-14  1710 .danger_lut_tbl 
= {0xff, 0x0, 0x0},
5334087ee7438fa Loic Poulain   2022-02-14  1711 .safe_lut_tbl = 
{0xfff0, 0x0, 0x0},
5334087ee7438fa Loic Poulain   2022-02-14  1712 .qos_lut_tbl = {
5334087ee7438fa Loic Poulain   2022-02-14  1713 
{.nentry = ARRAY_SIZE(qcm2290_qos_linear),
5334087ee7438fa Loic Poulain   2022-02-14  1714 
.entries = qcm2290_qos_linear
5334087ee7438fa Loic Poulain   2022-02-14  1715 },
5334087ee7438fa Loic Poulain   2022-02-14  1716 },
5334087ee7438fa Loic Poulain   2022-02-14  1717 .cdp_cfg = {
5334087ee7438fa Loic Poulain   2022-02-14  1718 
{.rd_enable = 1, .wr_enable = 1},
5334087ee7438fa Loic Poulain

Re: [Freedreno] [PATCH v2] drm/msm/dpu: Move min BW request and full BW disable back to mdss

2022-06-01 Thread Dmitry Baryshkov


On 01/06/2022 02:01, Douglas Anderson wrote:

In commit a670ff578f1f ("drm/msm/dpu: always use mdp device to scale
bandwidth") we fully moved interconnect stuff to the DPU driver. This
had no change for sc7180 but _did_ have an impact for other SoCs. It
made them match the sc7180 scheme.

Unfortunately, the sc7180 scheme seems like it was a bit broken.
Specifically the interconnect needs to be on for more than just the
DPU driver's AXI bus. In the very least it also needs to be on for the
DSI driver's AXI bus. This can be seen fairly easily by doing this on
a ChromeOS sc7180-trogdor class device:

   set_power_policy --ac_screen_dim_delay=5 --ac_screen_off_delay=10
   sleep 10
   cd /sys/bus/platform/devices/ae94000.dsi/power
   echo on > control

When you do that, you'll get a warning splat in the logs about
"gcc_disp_hf_axi_clk status stuck at 'off'".

One could argue that perhaps what I have done above is "illegal" and
that it can't happen naturally in the system because in normal system
usage the DPU is pretty much always on when DSI is on. That being
said:
* In official ChromeOS builds (admittedly a 5.4 kernel with backports)
   we have seen that splat at bootup.
* Even though we don't use "autosuspend" for these components, we
   don't use the "put_sync" variants. Thus plausibly the DSI could stay
   "runtime enabled" past when the DPU is enabled. Techncially we
   shouldn't do that if the DPU's suspend ends up yanking our clock.

Let's change things such that the "bare minimum" request for the
interconnect happens in the mdss driver again. That means that all of
the children can assume that the interconnect is on at the minimum
bandwidth. We'll then let the DPU request the higher amount that it
wants.

It should be noted that this isn't as hacky of a solution as it might
initially appear. Specifically:
* Since MDSS and DPU individually get their own references to the
   interconnect then the framework will actually handle aggregating
   them. The two drivers are _not_ clobbering each other.
* When the Qualcomm interconnect driver aggregates it takes the max of
   all the peaks. Thus having MDSS request a peak, as we're doing here,
   won't actually change the total interconnect bandwidth (it won't be
   added to the request for the DPU). This perhaps explains why the
   "average" requested in MDSS was historically 0 since that one
   _would_ be added in.

NOTE also that in the downstream ChromeOS 5.4 and 5.15 kernels, we're
also seeing some RPMH hangs that are addressed by this fix. These
hangs are showing up in the field and on _some_ devices with enough
stress testing of suspend/resume. Specifically right at suspend time
with a stack crawl that looks like this (from chromeos-5.15 tree):
   rpmh_write_batch+0x19c/0x240
   qcom_icc_bcm_voter_commit+0x210/0x420
   qcom_icc_set+0x28/0x38
   apply_constraints+0x70/0xa4
   icc_set_bw+0x150/0x24c
   dpu_runtime_resume+0x50/0x1c4
   pm_generic_runtime_resume+0x30/0x44
   __genpd_runtime_resume+0x68/0x7c
   genpd_runtime_resume+0x12c/0x20c
   __rpm_callback+0x98/0x138
   rpm_callback+0x30/0x88
   rpm_resume+0x370/0x4a0
   __pm_runtime_resume+0x80/0xb0
   dpu_kms_enable_commit+0x24/0x30
   msm_atomic_commit_tail+0x12c/0x630
   commit_tail+0xac/0x150
   drm_atomic_helper_commit+0x114/0x11c
   drm_atomic_commit+0x68/0x78
   drm_atomic_helper_disable_all+0x158/0x1c8
   drm_atomic_helper_suspend+0xc0/0x1c0
   drm_mode_config_helper_suspend+0x2c/0x60
   msm_pm_prepare+0x2c/0x40
   pm_generic_prepare+0x30/0x44
   genpd_prepare+0x80/0xd0
   device_prepare+0x78/0x17c
   dpm_prepare+0xb0/0x384
   dpm_suspend_start+0x34/0xc0

We don't completely understand all the mechanisms in play, but the
hang seemed to come and go with random factors. It's not terribly
surprising that the hang is gone after this patch since the line of
code that was failing is no longer present in the kernel.

Fixes: a670ff578f1f ("drm/msm/dpu: always use mdp device to scale bandwidth")
Fixes: c33b7c0389e1 ("drm/msm/dpu: add support for clk and bw scaling for 
display")
Signed-off-by: Douglas Anderson 
---

Changes in v2:
- Don't set bandwidth in init.


Reviewed-by: Dmitry Baryshkov 



  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c |  8 
  drivers/gpu/drm/msm/msm_mdss.c  | 57 +
  2 files changed, 57 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 2b9d931474e0..3025184053e0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -49,8 +49,6 @@
  #define DPU_DEBUGFS_DIR "msm_dpu"
  #define DPU_DEBUGFS_HWMASKNAME "hw_log_mask"
  
-#define MIN_IB_BW	4ULL /* Min ib vote 400MB */

-
  static int dpu_kms_hw_init(struct msm_kms *kms);
  static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms);
  
@@ -1303,15 +1301,9 @@ static int __maybe_unused dpu_runtime_resume(struct device *dev)

struct dpu_kms *dpu_kms =

Re: [Freedreno] [PATCH v2] drm/msm/dpu: Move min BW request and full BW disable back to mdss

2022-06-01 Thread Abhinav Kumar





On 6/1/2022 12:58 PM, Dmitry Baryshkov wrote:

On Wed, 1 Jun 2022 at 20:18, Abhinav Kumar  wrote:

On 6/1/2022 3:04 AM, Dmitry Baryshkov wrote:

On Wed, 1 Jun 2022 at 02:01, Douglas Anderson  wrote:


In commit a670ff578f1f ("drm/msm/dpu: always use mdp device to scale
bandwidth") we fully moved interconnect stuff to the DPU driver. This
had no change for sc7180 but _did_ have an impact for other SoCs. It
made them match the sc7180 scheme.


[skipped the description]



Changes in v2:
- Don't set bandwidth in init.

   drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c |  8 
   drivers/gpu/drm/msm/msm_mdss.c  | 57 +
   2 files changed, 57 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 2b9d931474e0..3025184053e0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -49,8 +49,6 @@
   #define DPU_DEBUGFS_DIR "msm_dpu"
   #define DPU_DEBUGFS_HWMASKNAME "hw_log_mask"

-#define MIN_IB_BW  4ULL /* Min ib vote 400MB */
-
   static int dpu_kms_hw_init(struct msm_kms *kms);
   static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms);



[skipped]


diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 0454a571adf7..e13c5c12b775 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -5,6 +5,7 @@

   #include 
   #include 
+#include 
   #include 
   #include 
   #include 
@@ -25,6 +26,8 @@
   #define UBWC_CTRL_20x150
   #define UBWC_PREDICTION_MODE   0x154

+#define MIN_IB_BW  4UL /* Min ib vote 400MB */


As msm_mdss is now used for both DPU and MDP5 devices, could you
please confirm that this value is valid for older devices too? E.g.
db410c or 8974


I need to check with Kalyan on this value (400MB) as I am unable to find
documentation on this. Will update this thread when I do.

So prior to this change 627dc55c273da ("drm/msm/disp/dpu1: icc path
needs to be set before dpu runtime resume"), this value was coming from
the hw catalog

@@ -1191,10 +1193,10 @@ static int __maybe_unused
dpu_runtime_resume(struct device *dev)

  ddev = dpu_kms->dev;

+   WARN_ON(!(dpu_kms->num_paths));
  /* Min vote of BW is required before turning on AXI clk */
  for (i = 0; i < dpu_kms->num_paths; i++)
-   icc_set_bw(dpu_kms->path[i], 0,
-   dpu_kms->catalog->perf.min_dram_ib);
+   icc_set_bw(dpu_kms->path[i], 0, Bps_to_icc(MIN_IB_BW));

After this, we moved to a hard-coded value, I am not sure why.

So nothing wrong with this change as such, the only question is whether
this value is correct for older chips.

But the question here is, are older chips even using icc.

It seems like only sc7180, RB3/RB5 are unless i am mistaken.


We are not using it for msm8916 (but we should most probably). And for
the msm8996 the icc patches were by Yassine.


So is there really any impact to the older chips with this change.

If not, we should probably let this one go ahead and move back to
catalog based approach while extending ICC for older chips.


Let's get this sorted out. I'm fine with 400 MBps, if that works for
all chipsets.



I confirm that 400MBps min vote will work for all chipsets based on the 
discussion i had with my team.


Here, the additional thing to note as per discussion with doug on IRC is

now two ICC paths get created, one from mdp5's probe and the other from 
msm_mdss_init().


So the ICC driver will aggregate the votes and take the max for the 
second parameter ( IB ).


So for normal use-cases this will still work fine.

Thanks

Abhinav

[Freedreno] [PATCH v2 11/11] drm/msm/dsi_phy_7nm: Replace parent names with clk_hw pointers

2022-06-01 Thread Marijn Suijten

parent_hw pointers are easier to manage and cheaper to use than
repeatedly formatting the parent name and subsequently leaving the clk
framework to perform lookups based on that name.

Signed-off-by: Marijn Suijten 
Reviewed-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 70 +++
 1 file changed, 34 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c 
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index 6a58dd62bac5..c1710a8824e7 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -588,24 +588,24 @@ static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy)
  */
 static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw 
**provided_clocks)
 {
-   char clk_name[32], parent[32], vco_name[32];
-   char parent2[32];
+   char clk_name[32];
struct clk_init_data vco_init = {
.parent_data = &(const struct clk_parent_data) {
.fw_name = "ref",
},
.num_parents = 1,
-   .name = vco_name,
+   .name = clk_name,
.flags = CLK_IGNORE_UNUSED,
.ops = _ops_dsi_pll_7nm_vco,
};
struct device *dev = _7nm->phy->pdev->dev;
-   struct clk_hw *hw;
+   struct clk_hw *hw, *pll_out_div, *pll_bit, *pll_by_2_bit;
+   struct clk_hw *pll_post_out_div, *phy_pll_out_dsi_parent;
int ret;
 
DBG("DSI%d", pll_7nm->phy->id);
 
-   snprintf(vco_name, sizeof(vco_name), "dsi%dvco_clk", pll_7nm->phy->id);
+   snprintf(clk_name, sizeof(clk_name), "dsi%dvco_clk", pll_7nm->phy->id);
pll_7nm->clk_hw.init = _init;
 
ret = devm_clk_hw_register(dev, _7nm->clk_hw);
@@ -613,36 +613,34 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, 
struct clk_hw **provide
return ret;
 
snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_out_div_clk", 
pll_7nm->phy->id);
-   snprintf(parent, sizeof(parent), "dsi%dvco_clk", pll_7nm->phy->id);
 
-   hw = devm_clk_hw_register_divider(dev, clk_name, parent,
-   CLK_SET_RATE_PARENT, pll_7nm->phy->pll_base +
+   pll_out_div = devm_clk_hw_register_divider_parent_hw(dev, clk_name,
+   _7nm->clk_hw, CLK_SET_RATE_PARENT,
+   pll_7nm->phy->pll_base +
REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE,
0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);
-   if (IS_ERR(hw)) {
-   ret = PTR_ERR(hw);
+   if (IS_ERR(pll_out_div)) {
+   ret = PTR_ERR(pll_out_div);
goto fail;
}
 
snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_bit_clk", 
pll_7nm->phy->id);
-   snprintf(parent, sizeof(parent), "dsi%d_pll_out_div_clk", 
pll_7nm->phy->id);
 
/* BIT CLK: DIV_CTRL_3_0 */
-   hw = devm_clk_hw_register_divider(dev, clk_name, parent,
-   CLK_SET_RATE_PARENT,
+   pll_bit = devm_clk_hw_register_divider_parent_hw(dev, clk_name,
+   pll_out_div, CLK_SET_RATE_PARENT,
pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG0,
0, 4, CLK_DIVIDER_ONE_BASED, _7nm->postdiv_lock);
-   if (IS_ERR(hw)) {
-   ret = PTR_ERR(hw);
+   if (IS_ERR(pll_bit)) {
+   ret = PTR_ERR(pll_bit);
goto fail;
}
 
snprintf(clk_name, sizeof(clk_name), "dsi%d_phy_pll_out_byteclk", 
pll_7nm->phy->id);
-   snprintf(parent, sizeof(parent), "dsi%d_pll_bit_clk", pll_7nm->phy->id);
 
/* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */
-   hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
-   CLK_SET_RATE_PARENT, 1,
+   hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, clk_name,
+   pll_bit, CLK_SET_RATE_PARENT, 1,
pll_7nm->phy->cphy_mode ? 7 : 8);
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
@@ -652,24 +650,24 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, 
struct clk_hw **provide
provided_clocks[DSI_BYTE_PLL_CLK] = hw;
 
snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_by_2_bit_clk", 
pll_7nm->phy->id);
-   snprintf(parent, sizeof(parent), "dsi%d_pll_bit_clk", pll_7nm->phy->id);
 
-   hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
-  0, 1, 2);
-   if (IS_ERR(hw)) {
-   ret = PTR_ERR(hw);
+   pll_by_2_bit = devm_clk_hw_register_fixed_factor_parent_hw(dev,
+   clk_name, pll_bit, 0, 1, 2);
+   if (IS_ERR(pll_by_2_bit)) {
+   ret = PTR_ERR(pll_by_2_bit);
goto fail;
}
 
snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_post_out_div_clk", 
pll_7nm->phy->id);
-   snprintf(parent, sizeof(parent),

[Freedreno] [PATCH v2 10/11] drm/msm/dsi_phy_10nm: Replace parent names with clk_hw pointers

2022-06-01 Thread Marijn Suijten

parent_hw pointers are easier to manage and cheaper to use than
repeatedly formatting the parent name and subsequently leaving the clk
framework to perform lookups based on that name.

Signed-off-by: Marijn Suijten 
Reviewed-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 79 ++
 1 file changed, 36 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c 
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
index 8bd7b97b1b9b..ae57f95edf63 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
@@ -574,24 +574,24 @@ static int dsi_10nm_set_usecase(struct msm_dsi_phy *phy)
  */
 static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw 
**provided_clocks)
 {
-   char clk_name[32], parent[32], vco_name[32];
-   char parent2[32], parent3[32], parent4[32];
+   char clk_name[32];
struct clk_init_data vco_init = {
.parent_data = &(const struct clk_parent_data) {
.fw_name = "ref",
},
.num_parents = 1,
-   .name = vco_name,
+   .name = clk_name,
.flags = CLK_IGNORE_UNUSED,
.ops = _ops_dsi_pll_10nm_vco,
};
struct device *dev = _10nm->phy->pdev->dev;
-   struct clk_hw *hw;
+   struct clk_hw *hw, *pll_out_div, *pll_bit, *pll_by_2_bit;
+   struct clk_hw *pll_post_out_div, *pclk_mux;
int ret;
 
DBG("DSI%d", pll_10nm->phy->id);
 
-   snprintf(vco_name, sizeof(vco_name), "dsi%dvco_clk", pll_10nm->phy->id);
+   snprintf(clk_name, sizeof(clk_name), "dsi%dvco_clk", pll_10nm->phy->id);
pll_10nm->clk_hw.init = _init;
 
ret = devm_clk_hw_register(dev, _10nm->clk_hw);
@@ -599,36 +599,34 @@ static int pll_10nm_register(struct dsi_pll_10nm 
*pll_10nm, struct clk_hw **prov
return ret;
 
snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_out_div_clk", 
pll_10nm->phy->id);
-   snprintf(parent, sizeof(parent), "dsi%dvco_clk", pll_10nm->phy->id);
 
-   hw = devm_clk_hw_register_divider(dev, clk_name, parent,
-   CLK_SET_RATE_PARENT, pll_10nm->phy->pll_base +
+   pll_out_div = devm_clk_hw_register_divider_parent_hw(dev, clk_name,
+   _10nm->clk_hw, CLK_SET_RATE_PARENT,
+   pll_10nm->phy->pll_base +
REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE,
0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);
-   if (IS_ERR(hw)) {
-   ret = PTR_ERR(hw);
+   if (IS_ERR(pll_out_div)) {
+   ret = PTR_ERR(pll_out_div);
goto fail;
}
 
snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_bit_clk", 
pll_10nm->phy->id);
-   snprintf(parent, sizeof(parent), "dsi%d_pll_out_div_clk", 
pll_10nm->phy->id);
 
/* BIT CLK: DIV_CTRL_3_0 */
-   hw = devm_clk_hw_register_divider(dev, clk_name, parent,
-   CLK_SET_RATE_PARENT,
+   pll_bit = devm_clk_hw_register_divider_parent_hw(dev, clk_name,
+   pll_out_div, CLK_SET_RATE_PARENT,
pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG0,
0, 4, CLK_DIVIDER_ONE_BASED, _10nm->postdiv_lock);
-   if (IS_ERR(hw)) {
-   ret = PTR_ERR(hw);
+   if (IS_ERR(pll_bit)) {
+   ret = PTR_ERR(pll_bit);
goto fail;
}
 
snprintf(clk_name, sizeof(clk_name), "dsi%d_phy_pll_out_byteclk", 
pll_10nm->phy->id);
-   snprintf(parent, sizeof(parent), "dsi%d_pll_bit_clk", 
pll_10nm->phy->id);
 
/* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */
-   hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
-  CLK_SET_RATE_PARENT, 1, 8);
+   hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, clk_name,
+   pll_bit, CLK_SET_RATE_PARENT, 1, 8);
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
goto fail;
@@ -637,48 +635,43 @@ static int pll_10nm_register(struct dsi_pll_10nm 
*pll_10nm, struct clk_hw **prov
provided_clocks[DSI_BYTE_PLL_CLK] = hw;
 
snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_by_2_bit_clk", 
pll_10nm->phy->id);
-   snprintf(parent, sizeof(parent), "dsi%d_pll_bit_clk", 
pll_10nm->phy->id);
 
-   hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
-  0, 1, 2);
-   if (IS_ERR(hw)) {
-   ret = PTR_ERR(hw);
+   pll_by_2_bit = devm_clk_hw_register_fixed_factor_parent_hw(dev,
+   clk_name, pll_bit, 0, 1, 2);
+   if (IS_ERR(pll_by_2_bit)) {
+   ret = PTR_ERR(pll_by_2_bit);
goto fail;
}
 
snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_post_out_div_clk",

[Freedreno] [PATCH v2 09/11] drm/msm/dsi_phy_14nm: Replace parent names with clk_hw pointers

2022-06-01 Thread Marijn Suijten

parent_hw pointers are easier to manage and cheaper to use than
repeatedly formatting the parent name and subsequently leaving the clk
framework to perform lookups based on that name.

Signed-off-by: Marijn Suijten 
Reviewed-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 40 ++
 1 file changed, 19 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c 
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
index e10ba1b09b2f..1a855351654c 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
@@ -764,14 +764,14 @@ static int dsi_14nm_set_usecase(struct msm_dsi_phy *phy)
 
 static struct clk_hw *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm,
const char *name,
-   const char *parent_name,
+   const struct clk_hw *parent_hw,
unsigned long flags,
u8 shift)
 {
struct dsi_pll_14nm_postdiv *pll_postdiv;
struct device *dev = _14nm->phy->pdev->dev;
struct clk_init_data postdiv_init = {
-   .parent_names = (const char *[]) { parent_name },
+   .parent_hws = (const struct clk_hw *[]) { parent_hw },
.num_parents = 1,
.name = name,
.flags = flags,
@@ -800,23 +800,23 @@ static struct clk_hw *pll_14nm_postdiv_register(struct 
dsi_pll_14nm *pll_14nm,
 
 static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw 
**provided_clocks)
 {
-   char clk_name[32], parent[32], vco_name[32];
+   char clk_name[32];
struct clk_init_data vco_init = {
.parent_data = &(const struct clk_parent_data) {
.fw_name = "ref",
},
.num_parents = 1,
-   .name = vco_name,
+   .name = clk_name,
.flags = CLK_IGNORE_UNUSED,
.ops = _ops_dsi_pll_14nm_vco,
};
struct device *dev = _14nm->phy->pdev->dev;
-   struct clk_hw *hw;
+   struct clk_hw *hw, *n1_postdiv, *n1_postdivby2;
int ret;
 
DBG("DSI%d", pll_14nm->phy->id);
 
-   snprintf(vco_name, sizeof(vco_name), "dsi%dvco_clk", pll_14nm->phy->id);
+   snprintf(clk_name, sizeof(clk_name), "dsi%dvco_clk", pll_14nm->phy->id);
pll_14nm->clk_hw.init = _init;
 
ret = devm_clk_hw_register(dev, _14nm->clk_hw);
@@ -824,48 +824,46 @@ static int pll_14nm_register(struct dsi_pll_14nm 
*pll_14nm, struct clk_hw **prov
return ret;
 
snprintf(clk_name, sizeof(clk_name), "dsi%dn1_postdiv_clk", 
pll_14nm->phy->id);
-   snprintf(parent, sizeof(parent), "dsi%dvco_clk", pll_14nm->phy->id);
 
/* N1 postdiv, bits 0-3 in REG_DSI_14nm_PHY_CMN_CLK_CFG0 */
-   hw = pll_14nm_postdiv_register(pll_14nm, clk_name, parent,
-  CLK_SET_RATE_PARENT, 0);
-   if (IS_ERR(hw))
-   return PTR_ERR(hw);
+   n1_postdiv = pll_14nm_postdiv_register(pll_14nm, clk_name,
+   _14nm->clk_hw, CLK_SET_RATE_PARENT, 0);
+   if (IS_ERR(n1_postdiv))
+   return PTR_ERR(n1_postdiv);
 
snprintf(clk_name, sizeof(clk_name), "dsi%dpllbyte", pll_14nm->phy->id);
-   snprintf(parent, sizeof(parent), "dsi%dn1_postdiv_clk", 
pll_14nm->phy->id);
 
/* DSI Byte clock = VCO_CLK / N1 / 8 */
-   hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
-  CLK_SET_RATE_PARENT, 1, 8);
+   hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, clk_name,
+   n1_postdiv, CLK_SET_RATE_PARENT, 1, 8);
if (IS_ERR(hw))
return PTR_ERR(hw);
 
provided_clocks[DSI_BYTE_PLL_CLK] = hw;
 
snprintf(clk_name, sizeof(clk_name), "dsi%dn1_postdivby2_clk", 
pll_14nm->phy->id);
-   snprintf(parent, sizeof(parent), "dsi%dn1_postdiv_clk", 
pll_14nm->phy->id);
 
/*
 * Skip the mux for now, force DSICLK_SEL to 1, Add a /2 divider
 * on the way. Don't let it set parent.
 */
-   hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, 0, 1, 2);
-   if (IS_ERR(hw))
-   return PTR_ERR(hw);
+   n1_postdivby2 = devm_clk_hw_register_fixed_factor_parent_hw(dev,
+   clk_name, n1_postdiv, 0, 1, 2);
+   if (IS_ERR(n1_postdivby2))
+   return PTR_ERR(n1_postdivby2);
 
snprintf(clk_name, sizeof(clk_name), "dsi%dpll", pll_14nm->phy->id);
-   snprintf(parent, sizeof(parent), "dsi%dn1_postdivby2_clk", 
pll_14nm->phy->id);
 
/* DSI pixel clock = VCO_CLK / N1 / 2 / N2
 * This is the output of N2 post-divider, bits 4-7 in
 * REG_DSI_14nm_PHY_CMN_CLK_CFG0. Don't

[Freedreno] [PATCH v2 08/11] drm/msm/dsi_phy_28nm: Replace parent names with clk_hw pointers

2022-06-01 Thread Marijn Suijten

parent_hw pointers are easier to manage and cheaper to use than
repeatedly formatting the parent name and subsequently leaving the clk
framework to perform lookups based on that name.

Signed-off-by: Marijn Suijten 
---
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 50 ++
 1 file changed, 23 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c 
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
index 7d3cabeca743..04411fefb808 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
@@ -519,17 +519,17 @@ static int dsi_28nm_pll_restore_state(struct msm_dsi_phy 
*phy)
 
 static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw 
**provided_clocks)
 {
-   char clk_name[32], parent1[32], parent2[32], vco_name[32];
+   char clk_name[32];
struct clk_init_data vco_init = {
.parent_data = &(const struct clk_parent_data) {
.fw_name = "ref", .name = "xo",
},
.num_parents = 1,
-   .name = vco_name,
+   .name = clk_name,
.flags = CLK_IGNORE_UNUSED,
};
struct device *dev = _28nm->phy->pdev->dev;
-   struct clk_hw *hw;
+   struct clk_hw *hw, *analog_postdiv, *indirect_path_div2, *byte_mux;
int ret;
 
DBG("%d", pll_28nm->phy->id);
@@ -539,32 +539,30 @@ static int pll_28nm_register(struct dsi_pll_28nm 
*pll_28nm, struct clk_hw **prov
else
vco_init.ops = _ops_dsi_pll_28nm_vco_hpm;
 
-   snprintf(vco_name, sizeof(vco_name), "dsi%dvco_clk", pll_28nm->phy->id);
+   snprintf(clk_name, sizeof(clk_name), "dsi%dvco_clk", pll_28nm->phy->id);
pll_28nm->clk_hw.init = _init;
ret = devm_clk_hw_register(dev, _28nm->clk_hw);
if (ret)
return ret;
 
snprintf(clk_name, sizeof(clk_name), "dsi%danalog_postdiv_clk", 
pll_28nm->phy->id);
-   snprintf(parent1, sizeof(parent1), "dsi%dvco_clk", pll_28nm->phy->id);
-   hw = devm_clk_hw_register_divider(dev, clk_name, parent1,
-   CLK_SET_RATE_PARENT, pll_28nm->phy->pll_base +
+   analog_postdiv = devm_clk_hw_register_divider_parent_hw(dev, clk_name,
+   _28nm->clk_hw, CLK_SET_RATE_PARENT,
+   pll_28nm->phy->pll_base +
REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG,
0, 4, 0, NULL);
-   if (IS_ERR(hw))
-   return PTR_ERR(hw);
+   if (IS_ERR(analog_postdiv))
+   return PTR_ERR(analog_postdiv);
 
snprintf(clk_name, sizeof(clk_name), "dsi%dindirect_path_div2_clk", 
pll_28nm->phy->id);
-   snprintf(parent1, sizeof(parent1), "dsi%danalog_postdiv_clk", 
pll_28nm->phy->id);
-   hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent1,
-   CLK_SET_RATE_PARENT, 1, 2);
-   if (IS_ERR(hw))
-   return PTR_ERR(hw);
+   indirect_path_div2 = devm_clk_hw_register_fixed_factor_parent_hw(dev,
+   clk_name, analog_postdiv, CLK_SET_RATE_PARENT, 1, 2);
+   if (IS_ERR(indirect_path_div2))
+   return PTR_ERR(indirect_path_div2);
 
snprintf(clk_name, sizeof(clk_name), "dsi%dpll", pll_28nm->phy->id);
-   snprintf(parent1, sizeof(parent1), "dsi%dvco_clk", pll_28nm->phy->id);
-   hw = devm_clk_hw_register_divider(dev, clk_name, parent1, 0,
-   pll_28nm->phy->pll_base +
+   hw = devm_clk_hw_register_divider_parent_hw(dev, clk_name,
+   _28nm->clk_hw, 0, pll_28nm->phy->pll_base +
REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG,
0, 8, 0, NULL);
if (IS_ERR(hw))
@@ -572,20 +570,18 @@ static int pll_28nm_register(struct dsi_pll_28nm 
*pll_28nm, struct clk_hw **prov
provided_clocks[DSI_PIXEL_PLL_CLK] = hw;
 
snprintf(clk_name, sizeof(clk_name), "dsi%dbyte_mux", 
pll_28nm->phy->id);
-   snprintf(parent1, sizeof(parent1), "dsi%dvco_clk", pll_28nm->phy->id);
-   snprintf(parent2, sizeof(parent2), "dsi%dindirect_path_div2_clk", 
pll_28nm->phy->id);
-   hw = devm_clk_hw_register_mux(dev, clk_name,
-   ((const char *[]){
-   parent1, parent2,
+   byte_mux = devm_clk_hw_register_mux_parent_hws(dev, clk_name,
+   ((const struct clk_hw *[]){
+   _28nm->clk_hw,
+   indirect_path_div2,
}), 2, CLK_SET_RATE_PARENT, pll_28nm->phy->pll_base +
REG_DSI_28nm_PHY_PLL_VREG_CFG, 1, 1, 0, NULL);
-   if (IS_ERR(hw))
-   return PTR_ERR(hw);
+   if (IS_ERR(byte_mux))
+   return PTR_ERR(byte_mux);
 
snprintf(clk_name, sizeof(clk_name), "dsi%dpllbyte", pll_28nm->phy->id);
-   snprintf(parent1,

[Freedreno] [PATCH v2 07/11] drm/msm/dsi_phy_28nm_8960: Replace parent names with clk_hw pointers

2022-06-01 Thread Marijn Suijten

parent_hw pointers are easier to manage and cheaper to use than
repeatedly formatting the parent name and subsequently leaving the clk
framework to perform lookups based on that name.

Signed-off-by: Marijn Suijten 
Reviewed-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 15 ---
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c 
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
index 3deb306f4cc4..69c1b2d8333c 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
@@ -383,7 +383,7 @@ static int dsi_28nm_pll_restore_state(struct msm_dsi_phy 
*phy)
 
 static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw 
**provided_clocks)
 {
-   char clk_name[32], parent_name[32], vco_name[32];
+   char clk_name[32];
struct clk_init_data vco_init = {
.parent_data = &(const struct clk_parent_data) {
.fw_name = "ref",
@@ -404,8 +404,8 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, 
struct clk_hw **prov
if (!bytediv)
return -ENOMEM;
 
-   snprintf(vco_name, sizeof(vco_name), "dsi%dvco_clk", pll_28nm->phy->id);
-   vco_init.name = vco_name;
+   snprintf(clk_name, sizeof(clk_name), "dsi%dvco_clk", pll_28nm->phy->id);
+   vco_init.name = clk_name;
 
pll_28nm->clk_hw.init = _init;
 
@@ -417,13 +417,14 @@ static int pll_28nm_register(struct dsi_pll_28nm 
*pll_28nm, struct clk_hw **prov
bytediv->hw.init = _init;
bytediv->reg = pll_28nm->phy->pll_base + 
REG_DSI_28nm_8960_PHY_PLL_CTRL_9;
 
-   snprintf(parent_name, sizeof(parent_name), "dsi%dvco_clk", 
pll_28nm->phy->id);
snprintf(clk_name, sizeof(clk_name), "dsi%dpllbyte", pll_28nm->phy->id 
+ 1);
 
bytediv_init.name = clk_name;
bytediv_init.ops = _bytediv_ops;
bytediv_init.flags = CLK_SET_RATE_PARENT;
-   bytediv_init.parent_names = (const char * const *) _name;
+   bytediv_init.parent_hws = (const struct clk_hw*[]){
+   _28nm->clk_hw,
+   };
bytediv_init.num_parents = 1;
 
/* DIV2 */
@@ -434,8 +435,8 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, 
struct clk_hw **prov
 
snprintf(clk_name, sizeof(clk_name), "dsi%dpll", pll_28nm->phy->id + 1);
/* DIV3 */
-   hw = devm_clk_hw_register_divider(dev, clk_name, parent_name, 0,
-   pll_28nm->phy->pll_base +
+   hw = devm_clk_hw_register_divider_parent_hw(dev, clk_name,
+   _28nm->clk_hw, 0, pll_28nm->phy->pll_base +
REG_DSI_28nm_8960_PHY_PLL_CTRL_10,
0, 8, 0, NULL);
if (IS_ERR(hw))
-- 
2.36.1

[Freedreno] [PATCH v2 06/11] drm/msm/dsi/phy: Replace hardcoded char-array length with sizeof()

2022-06-01 Thread Marijn Suijten

Now that the last DSI PHY PLL driver (dsi_phy_28nm_8960) has been
converted to use a simple stack-local char-array instead of a
devm_kzalloc heap allocation we can safely call sizeof() on every string
variable (that's now a sized array instead of a pointer) passed into
snprintf instead of hardcoding the size.

Signed-off-by: Marijn Suijten 
---
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c| 36 +--
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c| 18 +-
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c| 24 ++---
 .../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c   |  8 ++---
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 34 +-
 5 files changed, 60 insertions(+), 60 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c 
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
index 56892036e419..8bd7b97b1b9b 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
@@ -591,15 +591,15 @@ static int pll_10nm_register(struct dsi_pll_10nm 
*pll_10nm, struct clk_hw **prov
 
DBG("DSI%d", pll_10nm->phy->id);
 
-   snprintf(vco_name, 32, "dsi%dvco_clk", pll_10nm->phy->id);
+   snprintf(vco_name, sizeof(vco_name), "dsi%dvco_clk", pll_10nm->phy->id);
pll_10nm->clk_hw.init = _init;
 
ret = devm_clk_hw_register(dev, _10nm->clk_hw);
if (ret)
return ret;
 
-   snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_10nm->phy->id);
-   snprintf(parent, 32, "dsi%dvco_clk", pll_10nm->phy->id);
+   snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_out_div_clk", 
pll_10nm->phy->id);
+   snprintf(parent, sizeof(parent), "dsi%dvco_clk", pll_10nm->phy->id);
 
hw = devm_clk_hw_register_divider(dev, clk_name, parent,
CLK_SET_RATE_PARENT, pll_10nm->phy->pll_base +
@@ -610,8 +610,8 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, 
struct clk_hw **prov
goto fail;
}
 
-   snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_10nm->phy->id);
-   snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->phy->id);
+   snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_bit_clk", 
pll_10nm->phy->id);
+   snprintf(parent, sizeof(parent), "dsi%d_pll_out_div_clk", 
pll_10nm->phy->id);
 
/* BIT CLK: DIV_CTRL_3_0 */
hw = devm_clk_hw_register_divider(dev, clk_name, parent,
@@ -623,8 +623,8 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, 
struct clk_hw **prov
goto fail;
}
 
-   snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_10nm->phy->id);
-   snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->phy->id);
+   snprintf(clk_name, sizeof(clk_name), "dsi%d_phy_pll_out_byteclk", 
pll_10nm->phy->id);
+   snprintf(parent, sizeof(parent), "dsi%d_pll_bit_clk", 
pll_10nm->phy->id);
 
/* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */
hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
@@ -636,8 +636,8 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, 
struct clk_hw **prov
 
provided_clocks[DSI_BYTE_PLL_CLK] = hw;
 
-   snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->phy->id);
-   snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->phy->id);
+   snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_by_2_bit_clk", 
pll_10nm->phy->id);
+   snprintf(parent, sizeof(parent), "dsi%d_pll_bit_clk", 
pll_10nm->phy->id);
 
hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
   0, 1, 2);
@@ -646,8 +646,8 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, 
struct clk_hw **prov
goto fail;
}
 
-   snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->phy->id);
-   snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->phy->id);
+   snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_post_out_div_clk", 
pll_10nm->phy->id);
+   snprintf(parent, sizeof(parent), "dsi%d_pll_out_div_clk", 
pll_10nm->phy->id);
 
hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
   0, 1, 4);
@@ -656,11 +656,11 @@ static int pll_10nm_register(struct dsi_pll_10nm 
*pll_10nm, struct clk_hw **prov
goto fail;
}
 
-   snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_10nm->phy->id);
-   snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->phy->id);
-   snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->phy->id);
-   snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_10nm->phy->id);
-   snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->phy->id);
+   snprintf(clk_name, sizeof(clk_name), "dsi%d_pclk_mux", 
pll_10nm->phy->id);
+   snprintf(parent, sizeof(parent), "dsi%d_pll_bit_clk", 
pll_10nm->phy->id);
+   snprintf(parent2, sizeof(parent2), "dsi%d_pll_by_2_bit_clk",

[Freedreno] [PATCH v2 04/11] drm/msm/dsi/phy: Reindent and reflow multiline function calls

2022-06-01 Thread Marijn Suijten

Patch 613cbd1da3c9 ("drm/msm/dsi: use devm_clk_*register to registe DSI
PHY clocks") introduced the devm_ prefix to clk_hw registration calls,
without updating the indentation of the arguments on the following
lines.

Similarly e55b3fc8 ("drm/msm/dsi: drop PLL accessor functions")
moved from pll_write to dsi_phy_write without updating the indentation
of followup arguments either.

Preparing for a series that heavily touches the clk calls, reflow and
reindent function calls that are adhering to an 80-char column limit by
spanning multiple lines.  Where function names are very long the
arguments are indented with a fixed number of two tab characters instead
of aligning with the opening parenthesis of the function call.

Signed-off-by: Marijn Suijten 
---
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c| 96 +--
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c|  9 +-
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c| 73 +++---
 .../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c   | 63 ++--
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 84 
 5 files changed, 161 insertions(+), 164 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c 
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
index 08b015ea1b1e..56892036e419 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
@@ -188,19 +188,19 @@ static void dsi_pll_ssc_commit(struct dsi_pll_10nm *pll, 
struct dsi_pll_config *
pr_debug("SSC is enabled\n");
 
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1,
- config->ssc_stepsize & 0xff);
+ config->ssc_stepsize & 0xff);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1,
- config->ssc_stepsize >> 8);
+ config->ssc_stepsize >> 8);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1,
- config->ssc_div_per & 0xff);
+ config->ssc_div_per & 0xff);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1,
- config->ssc_div_per >> 8);
+ config->ssc_div_per >> 8);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1,
- config->ssc_adj_per & 0xff);
+ config->ssc_adj_per & 0xff);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1,
- config->ssc_adj_per >> 8);
+ config->ssc_adj_per >> 8);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_CONTROL,
- SSC_EN | (config->ssc_center ? SSC_CENTER : 0));
+ SSC_EN | (config->ssc_center ? SSC_CENTER : 0));
}
 }
 
@@ -215,16 +215,19 @@ static void dsi_pll_config_hzindep_reg(struct 
dsi_pll_10nm *pll)
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER, 0x4e);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS, 0x40);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE,
- 0xba);
-   dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE, 
0x0c);
+ 0xba);
+   dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE,
+ 0x0c);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_OUTDIV, 0x00);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE, 0x00);
-   dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO, 0x08);
+   dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO,
+ 0x08);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1, 0x08);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1, 0xc0);
-   dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 
0xfa);
+   dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1,
+ 0xfa);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1,
- 0x4c);
+ 0x4c);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE, 0x80);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PFILT, 0x29);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_IFILT, 0x3f);
@@ -236,18 +239,18 @@ static void dsi_pll_commit(struct dsi_pll_10nm *pll, 
struct dsi_pll_config *conf
 
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1,
- config->decimal_div_start);
+ config->decimal_div_start);
dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1,
- config->frac_div_start & 0xff);
+

[Freedreno] [PATCH v2 03/11] clk: fixed-factor: Introduce *clk_hw_register_fixed_factor_parent_hw()

2022-06-01 Thread Marijn Suijten

Add the devres and non-devres variant of
clk_hw_register_fixed_factor_parent_hw() for registering a fixed factor
clock with clk_hw parent pointer instead of parent name.

Signed-off-by: Marijn Suijten 
---
 drivers/clk/clk-fixed-factor.c | 57 --
 include/linux/clk-provider.h   |  8 +
 2 files changed, 55 insertions(+), 10 deletions(-)

diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
index 54942d758ee6..fabb98d0cdb2 100644
--- a/drivers/clk/clk-fixed-factor.c
+++ b/drivers/clk/clk-fixed-factor.c
@@ -78,7 +78,8 @@ static void devm_clk_hw_register_fixed_factor_release(struct 
device *dev, void *
 
 static struct clk_hw *
 __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np,
-   const char *name, const char *parent_name, int index,
+   const char *name, const char *parent_name,
+   const struct clk_hw *parent_hw, int index,
unsigned long flags, unsigned int mult, unsigned int div,
bool devm)
 {
@@ -108,7 +109,9 @@ __clk_hw_register_fixed_factor(struct device *dev, struct 
device_node *np,
init.name = name;
init.ops = _fixed_factor_ops;
init.flags = flags;
-   if (parent_name)
+   if (parent_hw)
+   init.parent_hws = _hw;
+   else if (parent_name)
init.parent_names = _name;
else
init.parent_data = 
@@ -148,17 +151,50 @@ struct clk_hw 
*devm_clk_hw_register_fixed_factor_index(struct device *dev,
const char *name, unsigned int index, unsigned long flags,
unsigned int mult, unsigned int div)
 {
-   return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, index,
- flags, mult, div, true);
+   return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, NULL,
+ index, flags, mult, div, true);
 }
 EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_index);
 
+/**
+ * devm_clk_hw_register_fixed_factor_parent_hw - Register a fixed factor clock 
with
+ * pointer to parent clock
+ * @dev: device that is registering this clock
+ * @name: name of this clock
+ * @parent_hw: pointer to parent clk
+ * @flags: fixed factor flags
+ * @mult: multiplier
+ * @div: divider
+ *
+ * Return: Pointer to fixed factor clk_hw structure that was registered or
+ * an error pointer.
+ */
+struct clk_hw *devm_clk_hw_register_fixed_factor_parent_hw(struct device *dev,
+   const char *name, const struct clk_hw *parent_hw,
+   unsigned long flags, unsigned int mult, unsigned int div)
+{
+   return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, parent_hw,
+ -1, flags, mult, div, true);
+}
+EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_parent_hw);
+
+struct clk_hw *clk_hw_register_fixed_factor_parent_hw(struct device *dev,
+   const char *name, const struct clk_hw *parent_hw,
+   unsigned long flags, unsigned int mult, unsigned int div)
+{
+   return __clk_hw_register_fixed_factor(dev, NULL, name, NULL,
+ parent_hw, -1, flags, mult, div,
+ false);
+}
+EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor_parent_hw);
+
 struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
const char *name, const char *parent_name, unsigned long flags,
unsigned int mult, unsigned int div)
 {
-   return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, -1,
- flags, mult, div, false);
+   return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name,
+ NULL, -1, flags, mult, div,
+ false);
 }
 EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor);
 
@@ -204,8 +240,9 @@ struct clk_hw *devm_clk_hw_register_fixed_factor(struct 
device *dev,
const char *name, const char *parent_name, unsigned long flags,
unsigned int mult, unsigned int div)
 {
-   return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, -1,
-   flags, mult, div, true);
+   return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name,
+ NULL, -1, flags, mult, div,
+ true);
 }
 EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor);
 
@@ -240,8 +277,8 @@ static struct clk_hw *_of_fixed_factor_clk_setup(struct 
device_node *node)
if (of_match_node(set_rate_parent_matches, node))
flags |= CLK_SET_RATE_PARENT;
 
-   hw = __clk_hw_register_fixed_factor(NULL, node, clk_name, NULL, 0,
-   flags, mult, div, false);
+   hw =

[Freedreno] [PATCH v2 00/11] drm/msm/dsi_phy: Replace parent names with clk_hw pointers

2022-06-01 Thread Marijn Suijten

As stated in [1] I promised to tackle and send this series.

parent_hw pointers are easier to manage and cheaper to use than
repeatedly formatting the parent name and subsequently leaving the clk
framework to perform lookups based on that name.

This series starts out by adding extra constructors for divider, mux and
fixed-factor clocks that have parent_hw(s) pointer argument(s) instead
of some DT index or name.  Followed by individual patches performing the
conversion, one DSI PHY at a time.

dsi_phy_28nm_8960 includes an extra fixup to replace "eternal"
devm_kzalloc allocations (for the lifetime of the device) with
stack-local char arrays, like all the other DSI PHY drivers.

(Questions from v1 cover letter regarding the future of these drivers
 is omitted for brevity.)

And with enough future improvements out of the way, let's round out this
patch-series by stating that it has been successfully tested on:

- Sony Nile Discovery (Xperia XA2 Ultra): 14nm;
- Sony Seine PDX201 (Xperia 10II): 14nm;
- Sony Loire Suzu (Xperia X): 28nm.

And no diff is observed in debugfs's clk_summary.

Unfortunately all other devices in my collection with a 7/10nm DSI PHY
have a DSC panel which we have yet to get working.

[1]: 
https://lore.kernel.org/linux-arm-msm/20220502214235.s5plebunh4ttj...@somainline.org/

Changes since v1:

- Moved indentation changes to separate patch (Dmitry);
- dsi_phy_28nm_8960: move clock name allocation removal prior to
  parent_hw refactor;
- Remove vco_name stack-local char array in favour of reusing clk_name
  (Dmitry);
- Inserted additional patch to replace hardcoded char-array length
  constant 32 with sizeof(clk_name).

v1: 
https://lore.kernel.org/linux-arm-msm/20220523213837.1016542-1-marijn.suij...@somainline.org/T/#u

Marijn Suijten (11):
  clk: divider: Introduce devm_clk_hw_register_divider_parent_hw()
  clk: mux: Introduce devm_clk_hw_register_mux_parent_hws()
  clk: fixed-factor: Introduce *clk_hw_register_fixed_factor_parent_hw()
  drm/msm/dsi/phy: Reindent and reflow multiline function calls
  drm/msm/dsi_phy_28nm_8960: Use stack memory for temporary clock names
  drm/msm/dsi/phy: Replace hardcoded char-array length with sizeof()
  drm/msm/dsi_phy_28nm_8960: Replace parent names with clk_hw pointers
  drm/msm/dsi_phy_28nm: Replace parent names with clk_hw pointers
  drm/msm/dsi_phy_14nm: Replace parent names with clk_hw pointers
  drm/msm/dsi_phy_10nm: Replace parent names with clk_hw pointers
  drm/msm/dsi_phy_7nm: Replace parent names with clk_hw pointers

 drivers/clk/clk-fixed-factor.c|  57 --
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c| 165 +-
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c|  55 +++---
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c| 117 ++---
 .../gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c   |  90 +-
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 156 -
 include/linux/clk-provider.h  |  34 
 7 files changed, 358 insertions(+), 316 deletions(-)

-- 
2.36.1

[Freedreno] [PATCH v2 02/11] clk: mux: Introduce devm_clk_hw_register_mux_parent_hws()

2022-06-01 Thread Marijn Suijten

Add the devres variant of clk_hw_register_mux_hws() for registering a
mux clock with clk_hw parent pointers instead of parent names.

Signed-off-by: Marijn Suijten 
---
 include/linux/clk-provider.h | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 4e07621849e6..316c7e082934 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -980,6 +980,13 @@ struct clk *clk_register_mux_table(struct device *dev, 
const char *name,
  (parent_names), NULL, NULL, (flags), (reg), \
  (shift), BIT((width)) - 1, (clk_mux_flags), \
  NULL, (lock))
+#define devm_clk_hw_register_mux_parent_hws(dev, name, parent_hws,   \
+   num_parents, flags, reg, shift,   \
+   width, clk_mux_flags, lock)   \
+   __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL,  \
+  (parent_hws), NULL, (flags), (reg),\
+  (shift), BIT((width)) - 1, \
+  (clk_mux_flags), NULL, (lock))
 
 int clk_mux_val_to_index(struct clk_hw *hw, const u32 *table, unsigned int 
flags,
 unsigned int val);
-- 
2.36.1

[Freedreno] [PATCH v2 01/11] clk: divider: Introduce devm_clk_hw_register_divider_parent_hw()

2022-06-01 Thread Marijn Suijten

Add the devres variant of clk_hw_register_divider_parent_hw() for
registering a divider clock with clk_hw parent pointer instead of parent
name.

Signed-off-by: Marijn Suijten 
---
 include/linux/clk-provider.h | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index c10dc4c659e2..4e07621849e6 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -831,6 +831,25 @@ struct clk *clk_register_divider_table(struct device *dev, 
const char *name,
__devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), 
NULL,   \
  NULL, (flags), (reg), (shift), (width), \
  (clk_divider_flags), NULL, (lock))
+/**
+ * devm_clk_hw_register_divider_parent_hw - register a divider clock with the 
clock framework
+ * @dev: device registering this clock
+ * @name: name of this clock
+ * @parent_hw: pointer to parent clk
+ * @flags: framework-specific flags
+ * @reg: register address to adjust divider
+ * @shift: number of bits to shift the bitfield
+ * @width: width of the bitfield
+ * @clk_divider_flags: divider-specific flags for this clock
+ * @lock: shared register lock for this clock
+ */
+#define devm_clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags,   \
+  reg, shift, width, \
+  clk_divider_flags, lock)   \
+   __devm_clk_hw_register_divider((dev), NULL, (name), NULL, \
+  (parent_hw), NULL, (flags), (reg), \
+  (shift), (width), (clk_divider_flags), \
+  NULL, (lock))
 /**
  * devm_clk_hw_register_divider_table - register a table based divider clock
  * with the clock framework (devres variant)
-- 
2.36.1

Re: [Freedreno] [PATCH v3 4/4] drm/bridge: parade-ps8640: Handle DP AUX more properly

2022-06-01 Thread Dmitry Baryshkov


On 10/05/2022 22:29, Douglas Anderson wrote:

While it works, for the most part, to assume that the panel has
finished probing when devm_of_dp_aux_populate_ep_devices() returns,
it's a bit fragile. This is talked about at length in commit
a1e3667a9835 ("drm/bridge: ti-sn65dsi86: Promote the AUX channel to
its own sub-dev").

When reviewing the ps8640 code, I managed to convince myself that it
was OK not to worry about it there and that maybe it wasn't really
_that_ fragile. However, it turns out that it really is. Simply
hardcoding panel_edp_probe() to return -EPROBE_DEFER was enough to put
the boot process into an infinite loop. I believe this manages to trip
the same issues that we used to trip with the main MSM code where
something about our actions trigger Linux to re-probe previously
deferred devices right away and each time we try again we re-trigger
Linux to re-probe.

Let's fix this using the callback introduced in the patch ("drm/dp:
Callbacks to make it easier for drivers to use DP AUX bus properly").
When using the new callback, we have to be a little careful. The
probe_done() callback is no longer always called in the context of
our probe routine. That means we can't rely on being able to return
-EPROBE_DEFER from it. We re-jigger the order of things a bit to
account for that.

With this change, the device still boots (though obviously the panel
doesn't come up) if I force panel-edp to always return
-EPROBE_DEFER. If I fake it and make the panel probe exactly once it
also works.

Signed-off-by: Douglas Anderson 


Reviewed-by: Dmitry Baryshkov 


---

Changes in v3:
- Adapt to v3 changes in aux bus.
- Use devm_drm_bridge_add() to simplify.

Changes in v2:
- Rewrote atop new method introduced by patch #1.

  drivers/gpu/drm/bridge/parade-ps8640.c | 74 --
  1 file changed, 46 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c 
b/drivers/gpu/drm/bridge/parade-ps8640.c
index e2467e58b5b7..ff4227f6d800 100644
--- a/drivers/gpu/drm/bridge/parade-ps8640.c
+++ b/drivers/gpu/drm/bridge/parade-ps8640.c
@@ -537,7 +537,7 @@ static const struct drm_bridge_funcs ps8640_bridge_funcs = {
.pre_enable = ps8640_pre_enable,
  };
  
-static int ps8640_bridge_host_attach(struct device *dev, struct ps8640 *ps_bridge)

+static int ps8640_bridge_get_dsi_resources(struct device *dev, struct ps8640 
*ps_bridge)
  {
struct device_node *in_ep, *dsi_node;
struct mipi_dsi_device *dsi;
@@ -576,13 +576,40 @@ static int ps8640_bridge_host_attach(struct device *dev, 
struct ps8640 *ps_bridg
dsi->format = MIPI_DSI_FMT_RGB888;
dsi->lanes = NUM_MIPI_LANES;
  
-	return devm_mipi_dsi_attach(dev, dsi);

+   return 0;
+}
+
+static int ps8640_bridge_link_panel(struct drm_dp_aux *aux)
+{
+   struct ps8640 *ps_bridge = aux_to_ps8640(aux);
+   struct device *dev = aux->dev;
+   struct device_node *np = dev->of_node;
+   int ret;
+
+   /*
+* NOTE about returning -EPROBE_DEFER from this function: if we
+* return an error (most relevant to -EPROBE_DEFER) it will only
+* be passed out to ps8640_probe() if it called this directly (AKA the
+* panel isn't under the "aux-bus" node). That should be fine because
+* if the panel is under "aux-bus" it's guaranteed to have probed by
+* the time this function has been called.
+*/
+
+   /* port@1 is ps8640 output port */
+   ps_bridge->panel_bridge = devm_drm_of_get_bridge(dev, np, 1, 0);
+   if (IS_ERR(ps_bridge->panel_bridge))
+   return PTR_ERR(ps_bridge->panel_bridge);
+
+   ret = devm_drm_bridge_add(dev, _bridge->bridge);
+   if (ret)
+   return ret;
+
+   return devm_mipi_dsi_attach(dev, ps_bridge->dsi);
  }
  
  static int ps8640_probe(struct i2c_client *client)

  {
struct device *dev = >dev;
-   struct device_node *np = dev->of_node;
struct ps8640 *ps_bridge;
int ret;
u32 i;
@@ -623,6 +650,14 @@ static int ps8640_probe(struct i2c_client *client)
if (!ps8640_of_panel_on_aux_bus(>dev))
ps_bridge->bridge.ops = DRM_BRIDGE_OP_EDID;
  
+	/*

+* Get MIPI DSI resources early. These can return -EPROBE_DEFER so
+* we want to get them out of the way sooner.
+*/
+   ret = ps8640_bridge_get_dsi_resources(>dev, ps_bridge);
+   if (ret)
+   return ret;
+
ps_bridge->page[PAGE0_DP_CNTL] = client;
  
  	ps_bridge->regmap[PAGE0_DP_CNTL] = devm_regmap_init_i2c(client, ps8640_regmap_config);

@@ -665,35 +700,19 @@ static int ps8640_probe(struct i2c_client *client)
if (ret)
return ret;
  
-	devm_of_dp_aux_populate_ep_devices(_bridge->aux);

+   ret = devm_of_dp_aux_populate_bus(_bridge->aux, 
ps8640_bridge_link_panel);
  
-	/* port@1 is ps8640 output port */

-   ps_bridge->panel_bridge = devm_drm_of_get_bridge(dev, np, 1, 0);
-   if

Re: [Freedreno] [PATCH v4] drm/probe-helper: Default to 640x480 if no EDID on DP

2022-06-01 Thread Dmitry Baryshkov


On 01/06/2022 21:23, Douglas Anderson wrote:

If we're unable to read the EDID for a display because it's corrupt /
bogus / invalid then we'll add a set of standard modes for the
display. Since we have no true information about the connected
display, these modes are essentially guesses but better than nothing.
At the moment, none of the modes returned is marked as preferred, but
the modes are sorted such that the higher resolution modes are listed
first.

When userspace sees these modes presented by the kernel it needs to
figure out which one to pick. At least one userspace, ChromeOS [1]
seems to use the rules (which seem pretty reasonable):
1. Try to pick the first mode marked as preferred.
2. Try to pick the mode which matches the first detailed timing
descriptor in the EDID.
3. If no modes were marked as preferred then pick the first mode.

Unfortunately, userspace's rules combined with what the kernel is
doing causes us to fail section 4.2.2.6 (EDID Corruption Detection) of
the DP 1.4a Link CTS. That test case says that, while it's OK to allow
some implementation-specific fall-back modes if the EDID is bad that
userspace should _default_ to 640x480.

Let's fix this by marking 640x480 as default for DP in the no-EDID
case.

NOTES:
- In the discussion around v3 of this patch [2] there was talk about
   solving this in userspace and I even implemented a patch that would
   have solved this for ChromeOS, but then the discussion turned back
   to solving this in the kernel.
- Also in the discussion of v3 [2] it was requested to limit this
83;40900;0c  change to just DP since folks were worried that it would break some


Nit: this line seems broken


   subtle corner case on VGA or HDMI.

[1] 
https://source.chromium.org/chromium/chromium/src/+/a051f741d0a15caff2251301efe081c30e0f4a96:ui/ozone/platform/drm/common/drm_util.cc;l=488
[2] 
https://lore.kernel.org/r/20220513130533.v3.1.I31ec454f8d4ffce51a7708a8092f8a6f9c929092@changeid

Signed-off-by: Douglas Anderson 
Reviewed-by: Abhinav Kumar 


Reviewed-by: Dmitry Baryshkov 


---
I put Abhinav's Reviewed-by tag from v2 here since this is nearly the
same as v2. Hope this is OK.

Changes in v4:
- Code is back to v2, but limit to just DP.
- Beefed up the commit message.

Changes in v3:
- Don't set preferred, just disable the sort.

Changes in v2:
- Don't modify drm_add_modes_noedid() 'cause that'll break others
- Set 640x480 as preferred in drm_helper_probe_single_connector_modes()

  drivers/gpu/drm/drm_probe_helper.c | 11 ++-
  1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_probe_helper.c 
b/drivers/gpu/drm/drm_probe_helper.c
index 425f56280d51..75a71649b64d 100644
--- a/drivers/gpu/drm/drm_probe_helper.c
+++ b/drivers/gpu/drm/drm_probe_helper.c
@@ -569,8 +569,17 @@ int drm_helper_probe_single_connector_modes(struct 
drm_connector *connector,
count = drm_add_override_edid_modes(connector);
  
  	if (count == 0 && (connector->status == connector_status_connected ||

-  connector->status == connector_status_unknown))
+  connector->status == connector_status_unknown)) {
count = drm_add_modes_noedid(connector, 1024, 768);
+
+   /*
+* Section 4.2.2.6 (EDID Corruption Detection) of the DP 1.4a
+* Link CTS specifies that 640x480 (the official "failsafe"
+* mode) needs to be the default if there's no EDID.
+*/
+   if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort)
+   drm_set_preferred_mode(connector, 640, 480);
+   }
count += drm_helper_probe_add_cmdline_mode(connector);
if (count != 0) {
ret = __drm_helper_update_and_validate(connector, maxX, maxY, 
);



--
With best wishes
Dmitry

Re: [Freedreno] [PATCH v3 1/2] drm/probe-helper: Add helper for drm_helper_probe_single_connector_modes()

2022-06-01 Thread Dmitry Baryshkov


On 12/05/2022 01:58, Douglas Anderson wrote:

The drm_helper_probe_single_connector_modes() is a bit long. Let's
break a chunk off to update and validate modes. This helps avoid one
goto and also will allow us to more easily call the helper a second
time in a future patch without adding looping or another goto.

This change is intended to be a no-op change--just code movement.

Signed-off-by: Douglas Anderson 
Reviewed-by: Abhinav Kumar 
Reviewed-by: Thomas Zimmermann 


Reviewed-by: Dmitry Baryshkov 


---

Changes in v3:
- Removed WARN_ON

Changes in v2:
- Two underscores for __drm_helper_update_and_validate().
- Return err and use WARN_ON instead of returning a bool.

  drivers/gpu/drm/drm_probe_helper.c | 106 -
  1 file changed, 60 insertions(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/drm_probe_helper.c 
b/drivers/gpu/drm/drm_probe_helper.c
index 682359512996..2570d47e7eab 100644
--- a/drivers/gpu/drm/drm_probe_helper.c
+++ b/drivers/gpu/drm/drm_probe_helper.c
@@ -354,6 +354,61 @@ drm_helper_probe_detect(struct drm_connector *connector,
  }
  EXPORT_SYMBOL(drm_helper_probe_detect);
  
+static int __drm_helper_update_and_validate(struct drm_connector *connector,

+   uint32_t maxX, uint32_t maxY,
+   struct drm_modeset_acquire_ctx *ctx)
+{
+   struct drm_device *dev = connector->dev;
+   struct drm_display_mode *mode;
+   int mode_flags = 0;
+   int ret;
+
+   drm_connector_list_update(connector);
+
+   if (connector->interlace_allowed)
+   mode_flags |= DRM_MODE_FLAG_INTERLACE;
+   if (connector->doublescan_allowed)
+   mode_flags |= DRM_MODE_FLAG_DBLSCAN;
+   if (connector->stereo_allowed)
+   mode_flags |= DRM_MODE_FLAG_3D_MASK;
+
+   list_for_each_entry(mode, >modes, head) {
+   if (mode->status != MODE_OK)
+   continue;
+
+   mode->status = drm_mode_validate_driver(dev, mode);
+   if (mode->status != MODE_OK)
+   continue;
+
+   mode->status = drm_mode_validate_size(mode, maxX, maxY);
+   if (mode->status != MODE_OK)
+   continue;
+
+   mode->status = drm_mode_validate_flag(mode, mode_flags);
+   if (mode->status != MODE_OK)
+   continue;
+
+   ret = drm_mode_validate_pipeline(mode, connector, ctx,
+>status);
+   if (ret) {
+   drm_dbg_kms(dev,
+   "drm_mode_validate_pipeline failed: %d\n",
+   ret);
+
+   if (drm_WARN_ON_ONCE(dev, ret != -EDEADLK))
+   mode->status = MODE_ERROR;
+   else
+   return -EDEADLK;
+   }
+
+   if (mode->status != MODE_OK)
+   continue;
+   mode->status = drm_mode_validate_ycbcr420(mode, connector);
+   }
+
+   return 0;
+}
+
  /**
   * drm_helper_probe_single_connector_modes - get complete set of display modes
   * @connector: connector to probe
@@ -421,7 +476,6 @@ int drm_helper_probe_single_connector_modes(struct 
drm_connector *connector,
const struct drm_connector_helper_funcs *connector_funcs =
connector->helper_private;
int count = 0, ret;
-   int mode_flags = 0;
bool verbose_prune = true;
enum drm_connector_status old_status;
struct drm_modeset_acquire_ctx ctx;
@@ -519,52 +573,12 @@ int drm_helper_probe_single_connector_modes(struct 
drm_connector *connector,
   connector->status == connector_status_unknown))
count = drm_add_modes_noedid(connector, 1024, 768);
count += drm_helper_probe_add_cmdline_mode(connector);
-   if (count == 0)
-   goto prune;
-
-   drm_connector_list_update(connector);
-
-   if (connector->interlace_allowed)
-   mode_flags |= DRM_MODE_FLAG_INTERLACE;
-   if (connector->doublescan_allowed)
-   mode_flags |= DRM_MODE_FLAG_DBLSCAN;
-   if (connector->stereo_allowed)
-   mode_flags |= DRM_MODE_FLAG_3D_MASK;
-
-   list_for_each_entry(mode, >modes, head) {
-   if (mode->status != MODE_OK)
-   continue;
-
-   mode->status = drm_mode_validate_driver(dev, mode);
-   if (mode->status != MODE_OK)
-   continue;
-
-   mode->status = drm_mode_validate_size(mode, maxX, maxY);
-   if (mode->status != MODE_OK)
-   continue;
-
-   mode->status = drm_mode_validate_flag(mode, mode_flags);
-   if (mode->status != MODE_OK)
-   continue;
-
-   ret =

Re: [Freedreno] [PATCH v3 1/4] drm/dp: Export symbol / kerneldoc fixes for DP AUX bus

2022-06-01 Thread Dmitry Baryshkov


On 10/05/2022 22:29, Douglas Anderson wrote:

While working on the DP AUX bus code I found a few small things that
should be fixed. Namely the non-devm version of
of_dp_aux_populate_ep_devices() was missing an export. There was also
an extra blank line in a kerneldoc and a kerneldoc that incorrectly
documented a return value. Fix these.

Fixes: aeb33699fc2c ("drm: Introduce the DP AUX bus")
Signed-off-by: Douglas Anderson 


Reviewed-by: Dmitry Baryshkov 


---
None of these seem critical, so my plan is to land this in
drm-misc-next and not drm-misc-fixes. This will avoid merge conflicts
with future patches.

Changes in v3:
- Patch ("drm/dp: Export symbol / kerneldoc fixes...") split for v3.

  drivers/gpu/drm/display/drm_dp_aux_bus.c | 4 +---
  1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/display/drm_dp_aux_bus.c 
b/drivers/gpu/drm/display/drm_dp_aux_bus.c
index dccf3e2ea323..552f949cff59 100644
--- a/drivers/gpu/drm/display/drm_dp_aux_bus.c
+++ b/drivers/gpu/drm/display/drm_dp_aux_bus.c
@@ -66,7 +66,6 @@ static int dp_aux_ep_probe(struct device *dev)
   * @dev: The device to remove.
   *
   * Calls through to the endpoint driver remove.
- *
   */
  static void dp_aux_ep_remove(struct device *dev)
  {
@@ -120,8 +119,6 @@ ATTRIBUTE_GROUPS(dp_aux_ep_dev);
  /**
   * dp_aux_ep_dev_release() - Free memory for the dp_aux_ep device
   * @dev: The device to free.
- *
- * Return: 0 if no error or negative error code.
   */
  static void dp_aux_ep_dev_release(struct device *dev)
  {
@@ -256,6 +253,7 @@ int of_dp_aux_populate_ep_devices(struct drm_dp_aux *aux)
  
  	return 0;

  }
+EXPORT_SYMBOL_GPL(of_dp_aux_populate_ep_devices);
  
  static void of_dp_aux_depopulate_ep_devices_void(void *data)

  {



--
With best wishes
Dmitry

Re: [Freedreno] [PATCH] drm/msm: less magic numbers in msm_mdss_enable

2022-06-01 Thread Dmitry Baryshkov

On Wed, 1 Jun 2022 at 20:38, Abhinav Kumar  wrote:
>
>
>
> On 6/1/2022 2:46 AM, Dmitry Baryshkov wrote:
> > On Wed, 1 Jun 2022 at 01:01, Abhinav Kumar  
> > wrote:
> >> On 5/31/2022 5:18 AM, Dmitry Baryshkov wrote:
> >>> Replace magic register writes in msm_mdss_enable() with version that
> >>> contains less magic and more variable names that can be traced back to
> >>> the dpu_hw_catalog or the downstream dtsi files.
> >>>
> >>> Signed-off-by: Dmitry Baryshkov 
> >>> ---
> >>>drivers/gpu/drm/msm/msm_mdss.c | 79 ++
> >>>1 file changed, 71 insertions(+), 8 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/msm/msm_mdss.c 
> >>> b/drivers/gpu/drm/msm/msm_mdss.c
> >>> index 0454a571adf7..2a48263cd1b5 100644
> >>> --- a/drivers/gpu/drm/msm/msm_mdss.c
> >>> +++ b/drivers/gpu/drm/msm/msm_mdss.c
> >>> @@ -21,6 +21,7 @@
> >>>#define HW_REV  0x0
> >>>#define HW_INTR_STATUS  0x0010
> >>>
> >>> +#define UBWC_DEC_HW_VERSION  0x58
> >>>#define UBWC_STATIC 0x144
> >>>#define UBWC_CTRL_2 0x150
> >>>#define UBWC_PREDICTION_MODE0x154
> >>> @@ -132,9 +133,63 @@ static int _msm_mdss_irq_domain_add(struct msm_mdss 
> >>> *msm_mdss)
> >>>return 0;
> >>>}
> >>>
> >>> +#define UBWC_1_0 0x1000
> >>> +#define UBWC_2_0 0x2000
> >>> +#define UBWC_3_0 0x3000
> >>> +#define UBWC_4_0 0x4000
> >>> +
> >>> +static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss,
> >>> +u32 ubwc_static)
> >>> +{
> >>> + writel_relaxed(ubwc_static, msm_mdss->mmio + UBWC_STATIC);
> >>> +}
> >>> +
> >>> +static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss,
> >>> +unsigned int ubwc_version,
> >>> +u32 ubwc_swizzle,
> >>> +u32 highest_bank_bit,
> >>> +u32 macrotile_mode)
> >>> +{
> >>> + u32 value = (ubwc_swizzle & 0x1) |
> >>> + (highest_bank_bit & 0x3) << 4 |
> >>> + (macrotile_mode & 0x1) << 12;
> >>> +
> >>> + if (ubwc_version == UBWC_3_0)
> >>> + value |= BIT(10);
> >>> +
> >>> + if (ubwc_version == UBWC_1_0)
> >>> + value |= BIT(8);
> >>> +
> >>> + writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC);
> >>> +}
> >>> +
> >>> +static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss,
> >>> +unsigned int ubwc_version,
> >>> +u32 ubwc_swizzle,
> >>> +u32 ubwc_static,
> >>> +u32 highest_bank_bit,
> >>> +u32 macrotile_mode)
> >>> +{
> >>> + u32 value = (ubwc_swizzle & 0x7) |
> >>> + (ubwc_static & 0x1) << 3 |
> >>> + (highest_bank_bit & 0x7) << 4 |
> >>> + (macrotile_mode & 0x1) << 12;
> >>> +
> >>> + writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC);
> >>> +
> >>> + if (ubwc_version == UBWC_3_0) {
> >>> + writel_relaxed(1, msm_mdss->mmio + UBWC_CTRL_2);
> >>> + writel_relaxed(0, msm_mdss->mmio + UBWC_PREDICTION_MODE);
> >>> + } else {
> >>> + writel_relaxed(2, msm_mdss->mmio + UBWC_CTRL_2);
> >>> + writel_relaxed(1, msm_mdss->mmio + UBWC_PREDICTION_MODE);
> >>> + }
> >>> +}
> >>> +
> >>
> >> Is it possible to unify the above functions by having the internal
> >> ubwc_version checks?
> >
> > Note, it's not the ubwc_version, it is the ubwc_dec_hw_version. And
> > also different functions take different sets of arguments.
> >
> >> It seems like msm_mdss_setup_ubwc_dec_xxx can keep growing.
> >>
> >> I have not looked into each bit programming but from the top level so
> >> feel free to correct if wrong but it seems both do write UBWC_STATIC
> >> (different values based on different UBWC versions) and write some extra
> >> registers based on version
> >
> > This is what both the current code and the downstream do. See
> > https://github.com/MiCode/Xiaomi_Kernel_OpenSource/blob/zeus-s-oss/techpack/display-drivers/msm/sde/sde_hw_top.c#L312
> >
>
> Thanks for pointing to the downstream method for this,
>
> This is exactly what i was also suggesting to do when I mentioned
> unifying the above functions.
>
> So instead of having a separate function for each version why not handle
> all the versions in the same function like what the link you have shown
> does.

I wouldn't like that. The downstream uses hw_catalog to pass all
possible parameters. We do not, so we'd have a whole set of artificial
values.

>
> >>
> >>>static int msm_mdss_enable(struct msm_mdss *msm_mdss)
> >>>{
> >>>int ret;
> >>> + u32 hw_rev;
> >>>
> >>>ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, 
>

Re: [Freedreno] [PATCH v2] drm/msm/dpu: Move min BW request and full BW disable back to mdss

2022-06-01 Thread Dmitry Baryshkov

On Wed, 1 Jun 2022 at 20:18, Abhinav Kumar  wrote:
> On 6/1/2022 3:04 AM, Dmitry Baryshkov wrote:
> > On Wed, 1 Jun 2022 at 02:01, Douglas Anderson  wrote:
> >>
> >> In commit a670ff578f1f ("drm/msm/dpu: always use mdp device to scale
> >> bandwidth") we fully moved interconnect stuff to the DPU driver. This
> >> had no change for sc7180 but _did_ have an impact for other SoCs. It
> >> made them match the sc7180 scheme.
> >
> > [skipped the description]
> >
> >>
> >> Changes in v2:
> >> - Don't set bandwidth in init.
> >>
> >>   drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c |  8 
> >>   drivers/gpu/drm/msm/msm_mdss.c  | 57 +
> >>   2 files changed, 57 insertions(+), 8 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c 
> >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> >> index 2b9d931474e0..3025184053e0 100644
> >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> >> @@ -49,8 +49,6 @@
> >>   #define DPU_DEBUGFS_DIR "msm_dpu"
> >>   #define DPU_DEBUGFS_HWMASKNAME "hw_log_mask"
> >>
> >> -#define MIN_IB_BW  4ULL /* Min ib vote 400MB */
> >> -
> >>   static int dpu_kms_hw_init(struct msm_kms *kms);
> >>   static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms);
> >>
> >
> > [skipped]
> >
> >> diff --git a/drivers/gpu/drm/msm/msm_mdss.c 
> >> b/drivers/gpu/drm/msm/msm_mdss.c
> >> index 0454a571adf7..e13c5c12b775 100644
> >> --- a/drivers/gpu/drm/msm/msm_mdss.c
> >> +++ b/drivers/gpu/drm/msm/msm_mdss.c
> >> @@ -5,6 +5,7 @@
> >>
> >>   #include 
> >>   #include 
> >> +#include 
> >>   #include 
> >>   #include 
> >>   #include 
> >> @@ -25,6 +26,8 @@
> >>   #define UBWC_CTRL_20x150
> >>   #define UBWC_PREDICTION_MODE   0x154
> >>
> >> +#define MIN_IB_BW  4UL /* Min ib vote 400MB */
> >
> > As msm_mdss is now used for both DPU and MDP5 devices, could you
> > please confirm that this value is valid for older devices too? E.g.
> > db410c or 8974
> >
> I need to check with Kalyan on this value (400MB) as I am unable to find
> documentation on this. Will update this thread when I do.
>
> So prior to this change 627dc55c273da ("drm/msm/disp/dpu1: icc path
> needs to be set before dpu runtime resume"), this value was coming from
> the hw catalog
>
> @@ -1191,10 +1193,10 @@ static int __maybe_unused
> dpu_runtime_resume(struct device *dev)
>
>  ddev = dpu_kms->dev;
>
> +   WARN_ON(!(dpu_kms->num_paths));
>  /* Min vote of BW is required before turning on AXI clk */
>  for (i = 0; i < dpu_kms->num_paths; i++)
> -   icc_set_bw(dpu_kms->path[i], 0,
> -   dpu_kms->catalog->perf.min_dram_ib);
> +   icc_set_bw(dpu_kms->path[i], 0, Bps_to_icc(MIN_IB_BW));
>
> After this, we moved to a hard-coded value, I am not sure why.
>
> So nothing wrong with this change as such, the only question is whether
> this value is correct for older chips.
>
> But the question here is, are older chips even using icc.
>
> It seems like only sc7180, RB3/RB5 are unless i am mistaken.

We are not using it for msm8916 (but we should most probably). And for
the msm8996 the icc patches were by Yassine.

> So is there really any impact to the older chips with this change.
>
> If not, we should probably let this one go ahead and move back to
> catalog based approach while extending ICC for older chips.

Let's get this sorted out. I'm fine with 400 MBps, if that works for
all chipsets.

-- 
With best wishes
Dmitry

Re: [Freedreno] [PATCH v4] drm/probe-helper: Default to 640x480 if no EDID on DP

2022-06-01 Thread Sean Paul

On Wed, Jun 1, 2022 at 2:23 PM Douglas Anderson  wrote:
>
> If we're unable to read the EDID for a display because it's corrupt /
> bogus / invalid then we'll add a set of standard modes for the
> display. Since we have no true information about the connected
> display, these modes are essentially guesses but better than nothing.
> At the moment, none of the modes returned is marked as preferred, but
> the modes are sorted such that the higher resolution modes are listed
> first.
>
> When userspace sees these modes presented by the kernel it needs to
> figure out which one to pick. At least one userspace, ChromeOS [1]
> seems to use the rules (which seem pretty reasonable):
> 1. Try to pick the first mode marked as preferred.
> 2. Try to pick the mode which matches the first detailed timing
>descriptor in the EDID.
> 3. If no modes were marked as preferred then pick the first mode.
>
> Unfortunately, userspace's rules combined with what the kernel is
> doing causes us to fail section 4.2.2.6 (EDID Corruption Detection) of
> the DP 1.4a Link CTS. That test case says that, while it's OK to allow
> some implementation-specific fall-back modes if the EDID is bad that
> userspace should _default_ to 640x480.
>
> Let's fix this by marking 640x480 as default for DP in the no-EDID
> case.
>
> NOTES:
> - In the discussion around v3 of this patch [2] there was talk about
>   solving this in userspace and I even implemented a patch that would
>   have solved this for ChromeOS, but then the discussion turned back
>   to solving this in the kernel.
> - Also in the discussion of v3 [2] it was requested to limit this
> 83;40900;0c  change to just DP since folks were worried that it would break 
> some
>   subtle corner case on VGA or HDMI.
>
> [1] 
> https://source.chromium.org/chromium/chromium/src/+/a051f741d0a15caff2251301efe081c30e0f4a96:ui/ozone/platform/drm/common/drm_util.cc;l=488
> [2] 
> https://lore.kernel.org/r/20220513130533.v3.1.I31ec454f8d4ffce51a7708a8092f8a6f9c929092@changeid
>
> Signed-off-by: Douglas Anderson 
> Reviewed-by: Abhinav Kumar 


Reviewed-by: Sean Paul 

>
> ---
> I put Abhinav's Reviewed-by tag from v2 here since this is nearly the
> same as v2. Hope this is OK.
>
> Changes in v4:
> - Code is back to v2, but limit to just DP.
> - Beefed up the commit message.
>
> Changes in v3:
> - Don't set preferred, just disable the sort.
>
> Changes in v2:
> - Don't modify drm_add_modes_noedid() 'cause that'll break others
> - Set 640x480 as preferred in drm_helper_probe_single_connector_modes()
>
>  drivers/gpu/drm/drm_probe_helper.c | 11 ++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/drm_probe_helper.c 
> b/drivers/gpu/drm/drm_probe_helper.c
> index 425f56280d51..75a71649b64d 100644
> --- a/drivers/gpu/drm/drm_probe_helper.c
> +++ b/drivers/gpu/drm/drm_probe_helper.c
> @@ -569,8 +569,17 @@ int drm_helper_probe_single_connector_modes(struct 
> drm_connector *connector,
> count = drm_add_override_edid_modes(connector);
>
> if (count == 0 && (connector->status == connector_status_connected ||
> -  connector->status == connector_status_unknown))
> +  connector->status == connector_status_unknown)) {
> count = drm_add_modes_noedid(connector, 1024, 768);
> +
> +   /*
> +* Section 4.2.2.6 (EDID Corruption Detection) of the DP 1.4a
> +* Link CTS specifies that 640x480 (the official "failsafe"
> +* mode) needs to be the default if there's no EDID.
> +*/
> +   if (connector->connector_type == 
> DRM_MODE_CONNECTOR_DisplayPort)
> +   drm_set_preferred_mode(connector, 640, 480);
> +   }
> count += drm_helper_probe_add_cmdline_mode(connector);
> if (count != 0) {
> ret = __drm_helper_update_and_validate(connector, maxX, maxY, 
> );
> --
> 2.36.1.255.ge46751e96f-goog
>

[Freedreno] [PATCH v4] drm/probe-helper: Default to 640x480 if no EDID on DP

2022-06-01 Thread Douglas Anderson

If we're unable to read the EDID for a display because it's corrupt /
bogus / invalid then we'll add a set of standard modes for the
display. Since we have no true information about the connected
display, these modes are essentially guesses but better than nothing.
At the moment, none of the modes returned is marked as preferred, but
the modes are sorted such that the higher resolution modes are listed
first.

When userspace sees these modes presented by the kernel it needs to
figure out which one to pick. At least one userspace, ChromeOS [1]
seems to use the rules (which seem pretty reasonable):
1. Try to pick the first mode marked as preferred.
2. Try to pick the mode which matches the first detailed timing
   descriptor in the EDID.
3. If no modes were marked as preferred then pick the first mode.

Unfortunately, userspace's rules combined with what the kernel is
doing causes us to fail section 4.2.2.6 (EDID Corruption Detection) of
the DP 1.4a Link CTS. That test case says that, while it's OK to allow
some implementation-specific fall-back modes if the EDID is bad that
userspace should _default_ to 640x480.

Let's fix this by marking 640x480 as default for DP in the no-EDID
case.

NOTES:
- In the discussion around v3 of this patch [2] there was talk about
  solving this in userspace and I even implemented a patch that would
  have solved this for ChromeOS, but then the discussion turned back
  to solving this in the kernel.
- Also in the discussion of v3 [2] it was requested to limit this
83;40900;0c  change to just DP since folks were worried that it would break some
  subtle corner case on VGA or HDMI.

[1] 
https://source.chromium.org/chromium/chromium/src/+/a051f741d0a15caff2251301efe081c30e0f4a96:ui/ozone/platform/drm/common/drm_util.cc;l=488
[2] 
https://lore.kernel.org/r/20220513130533.v3.1.I31ec454f8d4ffce51a7708a8092f8a6f9c929092@changeid

Signed-off-by: Douglas Anderson 
Reviewed-by: Abhinav Kumar 
---
I put Abhinav's Reviewed-by tag from v2 here since this is nearly the
same as v2. Hope this is OK.

Changes in v4:
- Code is back to v2, but limit to just DP.
- Beefed up the commit message.

Changes in v3:
- Don't set preferred, just disable the sort.

Changes in v2:
- Don't modify drm_add_modes_noedid() 'cause that'll break others
- Set 640x480 as preferred in drm_helper_probe_single_connector_modes()

 drivers/gpu/drm/drm_probe_helper.c | 11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_probe_helper.c 
b/drivers/gpu/drm/drm_probe_helper.c
index 425f56280d51..75a71649b64d 100644
--- a/drivers/gpu/drm/drm_probe_helper.c
+++ b/drivers/gpu/drm/drm_probe_helper.c
@@ -569,8 +569,17 @@ int drm_helper_probe_single_connector_modes(struct 
drm_connector *connector,
count = drm_add_override_edid_modes(connector);
 
if (count == 0 && (connector->status == connector_status_connected ||
-  connector->status == connector_status_unknown))
+  connector->status == connector_status_unknown)) {
count = drm_add_modes_noedid(connector, 1024, 768);
+
+   /*
+* Section 4.2.2.6 (EDID Corruption Detection) of the DP 1.4a
+* Link CTS specifies that 640x480 (the official "failsafe"
+* mode) needs to be the default if there's no EDID.
+*/
+   if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort)
+   drm_set_preferred_mode(connector, 640, 480);
+   }
count += drm_helper_probe_add_cmdline_mode(connector);
if (count != 0) {
ret = __drm_helper_update_and_validate(connector, maxX, maxY, 
);
-- 
2.36.1.255.ge46751e96f-goog

Re: [Freedreno] [PATCH] drm/msm: less magic numbers in msm_mdss_enable

2022-06-01 Thread Abhinav Kumar





On 6/1/2022 2:46 AM, Dmitry Baryshkov wrote:

On Wed, 1 Jun 2022 at 01:01, Abhinav Kumar  wrote:

On 5/31/2022 5:18 AM, Dmitry Baryshkov wrote:

Replace magic register writes in msm_mdss_enable() with version that
contains less magic and more variable names that can be traced back to
the dpu_hw_catalog or the downstream dtsi files.

Signed-off-by: Dmitry Baryshkov 
---
   drivers/gpu/drm/msm/msm_mdss.c | 79 ++
   1 file changed, 71 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 0454a571adf7..2a48263cd1b5 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -21,6 +21,7 @@
   #define HW_REV  0x0
   #define HW_INTR_STATUS  0x0010

+#define UBWC_DEC_HW_VERSION  0x58
   #define UBWC_STATIC 0x144
   #define UBWC_CTRL_2 0x150
   #define UBWC_PREDICTION_MODE0x154
@@ -132,9 +133,63 @@ static int _msm_mdss_irq_domain_add(struct msm_mdss 
*msm_mdss)
   return 0;
   }

+#define UBWC_1_0 0x1000
+#define UBWC_2_0 0x2000
+#define UBWC_3_0 0x3000
+#define UBWC_4_0 0x4000
+
+static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss,
+u32 ubwc_static)
+{
+ writel_relaxed(ubwc_static, msm_mdss->mmio + UBWC_STATIC);
+}
+
+static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss,
+unsigned int ubwc_version,
+u32 ubwc_swizzle,
+u32 highest_bank_bit,
+u32 macrotile_mode)
+{
+ u32 value = (ubwc_swizzle & 0x1) |
+ (highest_bank_bit & 0x3) << 4 |
+ (macrotile_mode & 0x1) << 12;
+
+ if (ubwc_version == UBWC_3_0)
+ value |= BIT(10);
+
+ if (ubwc_version == UBWC_1_0)
+ value |= BIT(8);
+
+ writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC);
+}
+
+static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss,
+unsigned int ubwc_version,
+u32 ubwc_swizzle,
+u32 ubwc_static,
+u32 highest_bank_bit,
+u32 macrotile_mode)
+{
+ u32 value = (ubwc_swizzle & 0x7) |
+ (ubwc_static & 0x1) << 3 |
+ (highest_bank_bit & 0x7) << 4 |
+ (macrotile_mode & 0x1) << 12;
+
+ writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC);
+
+ if (ubwc_version == UBWC_3_0) {
+ writel_relaxed(1, msm_mdss->mmio + UBWC_CTRL_2);
+ writel_relaxed(0, msm_mdss->mmio + UBWC_PREDICTION_MODE);
+ } else {
+ writel_relaxed(2, msm_mdss->mmio + UBWC_CTRL_2);
+ writel_relaxed(1, msm_mdss->mmio + UBWC_PREDICTION_MODE);
+ }
+}
+


Is it possible to unify the above functions by having the internal
ubwc_version checks?


Note, it's not the ubwc_version, it is the ubwc_dec_hw_version. And
also different functions take different sets of arguments.


It seems like msm_mdss_setup_ubwc_dec_xxx can keep growing.

I have not looked into each bit programming but from the top level so
feel free to correct if wrong but it seems both do write UBWC_STATIC
(different values based on different UBWC versions) and write some extra
registers based on version


This is what both the current code and the downstream do. See
https://github.com/MiCode/Xiaomi_Kernel_OpenSource/blob/zeus-s-oss/techpack/display-drivers/msm/sde/sde_hw_top.c#L312



Thanks for pointing to the downstream method for this,

This is exactly what i was also suggesting to do when I mentioned 
unifying the above functions.


So instead of having a separate function for each version why not handle 
all the versions in the same function like what the link you have shown 
does.





   static int msm_mdss_enable(struct msm_mdss *msm_mdss)
   {
   int ret;
+ u32 hw_rev;

   ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks);
   if (ret) {
@@ -149,26 +204,34 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)
   if (msm_mdss->is_mdp5)
   return 0;

+ hw_rev = readl_relaxed(msm_mdss->mmio + HW_REV);
+ dev_info(msm_mdss->dev, "HW_REV: 0x%x\n", hw_rev);
+ dev_info(msm_mdss->dev, "UBWC_DEC_HW_VERSION: 0x%x\n",
+ readl_relaxed(msm_mdss->mmio + UBWC_DEC_HW_VERSION));


we are already printing the HW version here

https://gitlab.freedesktop.org/drm/msm/-/blob/msm-next/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c#L1096

Do you want to remove that print then? May be. Let me take a look.


[skipped]

Re: [Freedreno] [PATCH v2] drm/msm/dpu: Move min BW request and full BW disable back to mdss

2022-06-01 Thread Abhinav Kumar





On 6/1/2022 3:04 AM, Dmitry Baryshkov wrote:

On Wed, 1 Jun 2022 at 02:01, Douglas Anderson  wrote:


In commit a670ff578f1f ("drm/msm/dpu: always use mdp device to scale
bandwidth") we fully moved interconnect stuff to the DPU driver. This
had no change for sc7180 but _did_ have an impact for other SoCs. It
made them match the sc7180 scheme.


[skipped the description]



Changes in v2:
- Don't set bandwidth in init.

  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c |  8 
  drivers/gpu/drm/msm/msm_mdss.c  | 57 +
  2 files changed, 57 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 2b9d931474e0..3025184053e0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -49,8 +49,6 @@
  #define DPU_DEBUGFS_DIR "msm_dpu"
  #define DPU_DEBUGFS_HWMASKNAME "hw_log_mask"

-#define MIN_IB_BW  4ULL /* Min ib vote 400MB */
-
  static int dpu_kms_hw_init(struct msm_kms *kms);
  static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms);



[skipped]


diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 0454a571adf7..e13c5c12b775 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -5,6 +5,7 @@

  #include 
  #include 
+#include 
  #include 
  #include 
  #include 
@@ -25,6 +26,8 @@
  #define UBWC_CTRL_20x150
  #define UBWC_PREDICTION_MODE   0x154

+#define MIN_IB_BW  4UL /* Min ib vote 400MB */


As msm_mdss is now used for both DPU and MDP5 devices, could you
please confirm that this value is valid for older devices too? E.g.
db410c or 8974

I need to check with Kalyan on this value (400MB) as I am unable to find 
documentation on this. Will update this thread when I do.


So prior to this change 627dc55c273da ("drm/msm/disp/dpu1: icc path 
needs to be set before dpu runtime resume"), this value was coming from 
the hw catalog


@@ -1191,10 +1193,10 @@ static int __maybe_unused 
dpu_runtime_resume(struct device *dev)


ddev = dpu_kms->dev;

+   WARN_ON(!(dpu_kms->num_paths));
/* Min vote of BW is required before turning on AXI clk */
for (i = 0; i < dpu_kms->num_paths; i++)
-   icc_set_bw(dpu_kms->path[i], 0,
-   dpu_kms->catalog->perf.min_dram_ib);
+   icc_set_bw(dpu_kms->path[i], 0, Bps_to_icc(MIN_IB_BW));

After this, we moved to a hard-coded value, I am not sure why.

So nothing wrong with this change as such, the only question is whether 
this value is correct for older chips.


But the question here is, are older chips even using icc.

It seems like only sc7180, RB3/RB5 are unless i am mistaken.

So is there really any impact to the older chips with this change.

If not, we should probably let this one go ahead and move back to 
catalog based approach while extending ICC for older chips.


Thanks

Abhinav


+
  struct msm_mdss {
 struct device *dev;

[Freedreno] [PATCH v1 3/4] drm/msm/dpu: merge base_off with blk_off in struct dpu_hw_blk_reg_map

2022-06-01 Thread Dmitry Baryshkov

There is little point in keeping a separate MDP address and block offset
in this struct. Merge them to form a new blk_addr field used for all
register access.

Signed-off-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c| 3 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c| 3 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c   | 3 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 3 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c   | 3 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 3 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c| 3 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c   | 5 ++---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c   | 3 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c| 3 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c   | 6 +++---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h   | 7 +++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c   | 3 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 3 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c   | 2 +-
 15 files changed, 20 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 1120ff408dae..e12b7fa48a7b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -58,8 +58,7 @@ static const struct dpu_ctl_cfg *_ctl_offset(enum dpu_ctl ctl,
 
for (i = 0; i < m->ctl_count; i++) {
if (ctl == m->ctl[i].id) {
-   b->base_off = addr;
-   b->blk_off = m->ctl[i].base;
+   b->blk_addr = addr + m->ctl[i].base;
b->log_mask = DPU_DBG_MASK_CTL;
return >ctl[i];
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
index dfe6e4c11917..411689ae6382 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
@@ -166,8 +166,7 @@ static struct dpu_dsc_cfg *_dsc_offset(enum dpu_dsc dsc,
 
for (i = 0; i < m->dsc_count; i++) {
if (dsc == m->dsc[i].id) {
-   b->base_off = addr;
-   b->blk_off = m->dsc[i].base;
+   b->blk_addr = addr + m->dsc[i].base;
b->log_mask = DPU_DBG_MASK_DSC;
return >dsc[i];
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
index 8196ae47dea8..8ab5ace34a2d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
@@ -80,8 +80,7 @@ static const struct dpu_dspp_cfg *_dspp_offset(enum dpu_dspp 
dspp,
 
for (i = 0; i < m->dspp_count; i++) {
if (dspp == m->dspp[i].id) {
-   b->base_off = addr;
-   b->blk_off = m->dspp[i].base;
+   b->blk_addr = addr + m->dspp[i].base;
b->log_mask = DPU_DBG_MASK_DSPP;
return >dspp[i];
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
index d83503ea2419..cf1b6d84c18a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
@@ -401,8 +401,7 @@ u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx)
 static void __intr_offset(const struct dpu_mdss_cfg *m,
void __iomem *addr, struct dpu_hw_blk_reg_map *hw)
 {
-   hw->base_off = addr;
-   hw->blk_off = m->mdp[0].base;
+   hw->blk_addr = addr + m->mdp[0].base;
 }
 
 struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index c7eb314f1d7a..d8aff0f459f8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -77,8 +77,7 @@ static const struct dpu_intf_cfg *_intf_offset(enum dpu_intf 
intf,
for (i = 0; i < m->intf_count; i++) {
if ((intf == m->intf[i].id) &&
(m->intf[i].type != INTF_NONE)) {
-   b->base_off = addr;
-   b->blk_off = m->intf[i].base;
+   b->blk_addr = addr + m->intf[i].base;
b->log_mask = DPU_DBG_MASK_INTF;
return >intf[i];
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
index 87a4a5869b9b..75d55fd65f19 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
@@ -43,8 +43,7 @@ static const struct dpu_lm_cfg *_lm_offset(enum dpu_lm mixer,
 
for (i = 0; i < m->mixer_count; i++) {
if (mixer ==

[Freedreno] [PATCH v1 4/4] drm/msm/dpu: move struct dpu_hw_blk definition to dpu_hw_utils.h

2022-06-01 Thread Dmitry Baryshkov

There is little point in having a separate header just for a single
opaque struct definition. Drop it now and move the struct to the
dpu_hw_util.h header.

Signed-off-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h  |  1 -
 .../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c   |  1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h| 25 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h|  1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h   |  2 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h   |  1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h |  1 -
 .../gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.h|  1 -
 .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h   |  1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h   |  1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h|  1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h   |  7 ++
 12 files changed, 7 insertions(+), 36 deletions(-)
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index b8785c394fcc..da64b0f639a9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -12,7 +12,6 @@
 #include 
 #include "dpu_kms.h"
 #include "dpu_core_perf.h"
-#include "dpu_hw_blk.h"
 
 #define DPU_CRTC_NAME_SIZE 12
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
index 53bb4639c8e9..1db6b75cd1f6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
@@ -12,7 +12,6 @@
 #include "dpu_hw_top.h"
 #include "dpu_hw_wb.h"
 #include "dpu_hw_lm.h"
-#include "dpu_hw_blk.h"
 #include "dpu_hw_merge3d.h"
 #include "dpu_hw_interrupts.h"
 #include "dpu_core_irq.h"
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h
deleted file mode 100644
index 52e92f37eda4..
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
- */
-
-#ifndef _DPU_HW_BLK_H
-#define _DPU_HW_BLK_H
-
-#include 
-#include 
-
-struct dpu_hw_blk;
-
-
-/**
- * struct dpu_hw_blk - definition of hardware block object
- * @list: list of hardware blocks
- * @type: hardware block type
- * @id: instance id
- * @refcount: reference/usage count
- */
-struct dpu_hw_blk {
-   /* opaque */
-};
-
-#endif /*_DPU_HW_BLK_H */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
index 5755307089b5..7d9ad6a3f9f6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
@@ -10,7 +10,6 @@
 #include "dpu_hw_util.h"
 #include "dpu_hw_catalog.h"
 #include "dpu_hw_sspp.h"
-#include "dpu_hw_blk.h"
 
 /**
  * dpu_ctl_mode_sel: Interface mode selection
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h
index 7fa189cfcb06..05ecfdfac93b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h
@@ -5,8 +5,6 @@
 #ifndef _DPU_HW_DSPP_H
 #define _DPU_HW_DSPP_H
 
-#include "dpu_hw_blk.h"
-
 struct dpu_hw_dspp;
 
 /**
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
index 7b2d96ac61e8..c262430e4dbd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
@@ -8,7 +8,6 @@
 #include "dpu_hw_catalog.h"
 #include "dpu_hw_mdss.h"
 #include "dpu_hw_util.h"
-#include "dpu_hw_blk.h"
 
 struct dpu_hw_intf;
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
index d8052fb2d5da..652ddfdedec3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
@@ -8,7 +8,6 @@
 
 #include "dpu_hw_mdss.h"
 #include "dpu_hw_util.h"
-#include "dpu_hw_blk.h"
 
 struct dpu_hw_mixer;
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.h
index 870bdb14613e..81fd1d5f718e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.h
@@ -8,7 +8,6 @@
 #include "dpu_hw_catalog.h"
 #include "dpu_hw_mdss.h"
 #include "dpu_hw_util.h"
-#include "dpu_hw_blk.h"
 
 struct dpu_hw_merge_3d;
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
index 12758468d9ca..c00223441d99 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
@@ -8,7 +8,6 @@
 #include "dpu_hw_catalog.h"
 #include "dpu_hw_mdss.h"
 #include "dpu_hw_util.h"
-#include "dpu_hw_blk.h"
 
 #define DITHER_MATRIX_SZ 16
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h

[Freedreno] [PATCH v1 2/4] drm/msm/dpu: drop length from struct dpu_hw_blk_reg_map

2022-06-01 Thread Dmitry Baryshkov

We (nearly) do not use the length field from struct dpu_hw_blk_reg_map,
so we can drop it safely.

Signed-off-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c  | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c  | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c   | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c  | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c  | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 2 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c   | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +-
 13 files changed, 1 insertion(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 7d416bf4ae91..1120ff408dae 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -60,7 +60,6 @@ static const struct dpu_ctl_cfg *_ctl_offset(enum dpu_ctl ctl,
if (ctl == m->ctl[i].id) {
b->base_off = addr;
b->blk_off = m->ctl[i].base;
-   b->length = m->ctl[i].len;
b->log_mask = DPU_DBG_MASK_CTL;
return >ctl[i];
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
index 184a1b27b13d..dfe6e4c11917 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
@@ -168,7 +168,6 @@ static struct dpu_dsc_cfg *_dsc_offset(enum dpu_dsc dsc,
if (dsc == m->dsc[i].id) {
b->base_off = addr;
b->blk_off = m->dsc[i].base;
-   b->length = m->dsc[i].len;
b->log_mask = DPU_DBG_MASK_DSC;
return >dsc[i];
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
index 3e63bf4fa64e..8196ae47dea8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
@@ -82,7 +82,6 @@ static const struct dpu_dspp_cfg *_dspp_offset(enum dpu_dspp 
dspp,
if (dspp == m->dspp[i].id) {
b->base_off = addr;
b->blk_off = m->dspp[i].base;
-   b->length = m->dspp[i].len;
b->log_mask = DPU_DBG_MASK_DSPP;
return >dspp[i];
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index b2ca8d19fdd7..c7eb314f1d7a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -79,7 +79,6 @@ static const struct dpu_intf_cfg *_intf_offset(enum dpu_intf 
intf,
(m->intf[i].type != INTF_NONE)) {
b->base_off = addr;
b->blk_off = m->intf[i].base;
-   b->length = m->intf[i].len;
b->log_mask = DPU_DBG_MASK_INTF;
return >intf[i];
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
index b41993269d09..87a4a5869b9b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
@@ -45,7 +45,6 @@ static const struct dpu_lm_cfg *_lm_offset(enum dpu_lm mixer,
if (mixer == m->mixer[i].id) {
b->base_off = addr;
b->blk_off = m->mixer[i].base;
-   b->length = m->mixer[i].len;
b->log_mask = DPU_DBG_MASK_LM;
return >mixer[i];
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c
index b053d68d38da..538691f7bf66 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c
@@ -25,7 +25,6 @@ static const struct dpu_merge_3d_cfg *_merge_3d_offset(enum 
dpu_merge_3d idx,
if (idx == m->merge_3d[i].id) {
b->base_off = addr;
b->blk_off = m->merge_3d[i].base;
-   b->length = m->merge_3d[i].len;
b->log_mask = DPU_DBG_MASK_PINGPONG;
return >merge_3d[i];
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
index 6538e195cfe9..0aa63636bc9a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
+++

[Freedreno] [PATCH v1 0/4] drm/msm/dpu: cleanup struct dpu_hw_blk_reg_map

2022-06-01 Thread Dmitry Baryshkov

Cleanup the fields of struct dpu_hw_blk_reg_map, remove unused fields,
merge base_off with blk_off into blk_addr. This patch series depends on
the patch [1].

[1] https://patchwork.freedesktop.org/patch/488001/?series=104613=1

Dmitry Baryshkov (4):
  drm/msm/dpu: drop xin_id from struct dpu_hw_blk_reg_map
  drm/msm/dpu: drop length from struct dpu_hw_blk_reg_map
  drm/msm/dpu: merge base_off with blk_off in struct dpu_hw_blk_reg_map
  drm/msm/dpu: move struct dpu_hw_blk definition to dpu_hw_utils.h

 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h  |  1 -
 .../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c   |  1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h| 25 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c|  4 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h|  1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c|  4 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c   |  4 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h   |  2 --
 .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c |  3 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c   |  4 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h   |  1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c |  4 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h |  1 -
 .../gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c|  4 +--
 .../gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.h|  1 -
 .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c   |  6 ++---
 .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h   |  1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c   |  4 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h   |  1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c|  4 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h|  1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c   |  6 ++---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h   | 18 +++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c   |  4 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c |  4 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c   |  4 +--
 26 files changed, 28 insertions(+), 85 deletions(-)
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h

-- 
2.35.1

[Freedreno] [PATCH v1 1/4] drm/msm/dpu: drop xin_id from struct dpu_hw_blk_reg_map

2022-06-01 Thread Dmitry Baryshkov

Drop the unused field xin_id.

Signed-off-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
index 550b2e2b3e34..e8adb118fa85 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
@@ -20,13 +20,11 @@
  * @base_off: mdp register mapped offset
  * @blk_off:  pipe offset relative to mdss offset
  * @lengthlength of register block offset
- * @xin_idxin id
  */
 struct dpu_hw_blk_reg_map {
void __iomem *base_off;
u32 blk_off;
u32 length;
-   u32 xin_id;
u32 log_mask;
 };
 
-- 
2.35.1

[Freedreno] [PATCH v1 5/5] drm/msm/dpu: make dpu hardware catalog static const

2022-06-01 Thread Dmitry Baryshkov

Replace superfluous cfg_init functions, which just assign a static
config to the struct dpu_mdss_cfg, with static instances of struct
dpu_mdss_cfg.

Signed-off-by: Dmitry Baryshkov 
---
 .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 475 --
 .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h|   5 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c   |   2 +-
 3 files changed, 213 insertions(+), 269 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 28fc11e8da4f..67e3ab0b666d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -1722,283 +1722,228 @@ static const struct dpu_perf_cfg qcm2290_perf_data = {
.bw_inefficiency_factor = 120,
 };
 /*
- * Hardware catalog init
+ * Hardware catalog
  */
 
-/*
- * msm8998_cfg_init(): populate sdm845 dpu sub-blocks reg offsets
- * and instance counts.
- */
-static void msm8998_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
-{
-   *dpu_cfg = (struct dpu_mdss_cfg){
-   .caps = _dpu_caps,
-   .mdp_count = ARRAY_SIZE(msm8998_mdp),
-   .mdp = msm8998_mdp,
-   .ctl_count = ARRAY_SIZE(msm8998_ctl),
-   .ctl = msm8998_ctl,
-   .sspp_count = ARRAY_SIZE(msm8998_sspp),
-   .sspp = msm8998_sspp,
-   .mixer_count = ARRAY_SIZE(msm8998_lm),
-   .mixer = msm8998_lm,
-   .dspp_count = ARRAY_SIZE(msm8998_dspp),
-   .dspp = msm8998_dspp,
-   .pingpong_count = ARRAY_SIZE(sdm845_pp),
-   .pingpong = sdm845_pp,
-   .intf_count = ARRAY_SIZE(msm8998_intf),
-   .intf = msm8998_intf,
-   .vbif_count = ARRAY_SIZE(msm8998_vbif),
-   .vbif = msm8998_vbif,
-   .reg_dma_count = 0,
-   .perf = msm8998_perf_data,
-   .mdss_irqs = IRQ_SM8250_MASK,
-   };
-}
-
-/*
- * sdm845_cfg_init(): populate sdm845 dpu sub-blocks reg offsets
- * and instance counts.
- */
-static void sdm845_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
-{
-   *dpu_cfg = (struct dpu_mdss_cfg){
-   .caps = _dpu_caps,
-   .mdp_count = ARRAY_SIZE(sdm845_mdp),
-   .mdp = sdm845_mdp,
-   .ctl_count = ARRAY_SIZE(sdm845_ctl),
-   .ctl = sdm845_ctl,
-   .sspp_count = ARRAY_SIZE(sdm845_sspp),
-   .sspp = sdm845_sspp,
-   .mixer_count = ARRAY_SIZE(sdm845_lm),
-   .mixer = sdm845_lm,
-   .pingpong_count = ARRAY_SIZE(sdm845_pp),
-   .pingpong = sdm845_pp,
-   .dsc_count = ARRAY_SIZE(sdm845_dsc),
-   .dsc = sdm845_dsc,
-   .intf_count = ARRAY_SIZE(sdm845_intf),
-   .intf = sdm845_intf,
-   .vbif_count = ARRAY_SIZE(sdm845_vbif),
-   .vbif = sdm845_vbif,
-   .reg_dma_count = 1,
-   .dma_cfg = sdm845_regdma,
-   .perf = sdm845_perf_data,
-   .mdss_irqs = IRQ_SDM845_MASK,
-   };
-}
-
-/*
- * sc7180_cfg_init(): populate sc7180 dpu sub-blocks reg offsets
- * and instance counts.
- */
-static void sc7180_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
-{
-   *dpu_cfg = (struct dpu_mdss_cfg){
-   .caps = _dpu_caps,
-   .mdp_count = ARRAY_SIZE(sc7180_mdp),
-   .mdp = sc7180_mdp,
-   .ctl_count = ARRAY_SIZE(sc7180_ctl),
-   .ctl = sc7180_ctl,
-   .sspp_count = ARRAY_SIZE(sc7180_sspp),
-   .sspp = sc7180_sspp,
-   .mixer_count = ARRAY_SIZE(sc7180_lm),
-   .mixer = sc7180_lm,
-   .dspp_count = ARRAY_SIZE(sc7180_dspp),
-   .dspp = sc7180_dspp,
-   .pingpong_count = ARRAY_SIZE(sc7180_pp),
-   .pingpong = sc7180_pp,
-   .intf_count = ARRAY_SIZE(sc7180_intf),
-   .intf = sc7180_intf,
-   .vbif_count = ARRAY_SIZE(sdm845_vbif),
-   .vbif = sdm845_vbif,
-   .reg_dma_count = 1,
-   .dma_cfg = sdm845_regdma,
-   .perf = sc7180_perf_data,
-   .mdss_irqs = IRQ_SC7180_MASK,
-   };
-}
-
-/*
- * sm8150_cfg_init(): populate sm8150 dpu sub-blocks reg offsets
- * and instance counts.
- */
-static void sm8150_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
-{
-   *dpu_cfg = (struct dpu_mdss_cfg){
-   .caps = _dpu_caps,
-   .mdp_count = ARRAY_SIZE(sdm845_mdp),
-   .mdp = sdm845_mdp,
-   .ctl_count = ARRAY_SIZE(sm8150_ctl),
-   .ctl = sm8150_ctl,
-   .sspp_count = ARRAY_SIZE(sdm845_sspp),
-   .sspp = sdm845_sspp,
-   .mixer_count = ARRAY_SIZE(sm8150_lm),
-   .mixer =

[Freedreno] [PATCH v1 3/5] drm/msm/dpu: remove hwversion field from data structures

2022-06-01 Thread Dmitry Baryshkov

The driver should not depend on hw revision for detecting features.
Instead it should use features from the hw catalog. Drop the hwversion
field from struct dpu_mdss_cfg and struct dpu_hw_blk_reg_map.

Signed-off-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 2 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c| 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c| 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c   | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c   | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c| 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c   | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c   | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c| 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h   | 2 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c   | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 1 -
 15 files changed, 17 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index cff6fe3a85ac..367279371e8d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -2002,7 +2002,6 @@ struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev)
for (i = 0; i < ARRAY_SIZE(cfg_handler); i++) {
if (cfg_handler[i].hw_rev == hw_rev) {
cfg_handler[i].cfg_init(dpu_cfg);
-   dpu_cfg->hwversion = hw_rev;
return dpu_cfg;
}
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index f70de97f492a..4225f58d8f97 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -826,8 +826,6 @@ struct dpu_perf_cfg {
  * @mdss_irqs: Bitmap with the irqs supported by the target
  */
 struct dpu_mdss_cfg {
-   u32 hwversion;
-
const struct dpu_caps *caps;
 
u32 mdp_count;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index c33e7ef611a6..7d416bf4ae91 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -61,7 +61,6 @@ static const struct dpu_ctl_cfg *_ctl_offset(enum dpu_ctl ctl,
b->base_off = addr;
b->blk_off = m->ctl[i].base;
b->length = m->ctl[i].len;
-   b->hwversion = m->hwversion;
b->log_mask = DPU_DBG_MASK_CTL;
return >ctl[i];
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
index 4ad8991fc7d9..6f20d6b6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
@@ -169,7 +169,6 @@ static struct dpu_dsc_cfg *_dsc_offset(enum dpu_dsc dsc,
b->base_off = addr;
b->blk_off = m->dsc[i].base;
b->length = m->dsc[i].len;
-   b->hwversion = m->hwversion;
b->log_mask = DPU_DBG_MASK_DSC;
return >dsc[i];
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
index 355894a3b48c..3e63bf4fa64e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
@@ -83,7 +83,6 @@ static const struct dpu_dspp_cfg *_dspp_offset(enum dpu_dspp 
dspp,
b->base_off = addr;
b->blk_off = m->dspp[i].base;
b->length = m->dspp[i].len;
-   b->hwversion = m->hwversion;
b->log_mask = DPU_DBG_MASK_DSPP;
return >dspp[i];
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
index 61284e6c313d..01bb2d84c3a0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
@@ -403,7 +403,6 @@ static void __intr_offset(struct dpu_mdss_cfg *m,
 {
hw->base_off = addr;
hw->blk_off = m->mdp[0].base;
-   hw->hwversion = m->hwversion;
 }
 
 struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 3f4d2c6e1b45..b2ca8d19fdd7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -80,7 +80,6 @@ static const struct dpu_intf_cfg *_intf_offset(enum dpu_intf 
intf,

[Freedreno] [PATCH v1 4/5] drm/msm/dpu: constify struct dpu_mdss_cfg

2022-06-01 Thread Dmitry Baryshkov

Mark struct dpu_mdss_cfg instance as a const pointer. This is mostly a
preparation for the next patch.

Signed-off-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c   |  6 +++---
 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h   |  4 ++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c |  4 ++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c |  4 ++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c  | 11 +++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h  |  9 ++---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c  |  4 ++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h  |  2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c   |  4 ++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h   |  2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c |  4 ++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h |  4 ++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c |  8 +++-
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h |  2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c   |  2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c  |  2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h  |  2 +-
 17 files changed, 31 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index a7492dd6ed65..c4139bc5de23 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
@@ -413,7 +413,7 @@ static ssize_t _dpu_core_perf_mode_write(struct file *file,
const char __user *user_buf, size_t count, loff_t *ppos)
 {
struct dpu_core_perf *perf = file->private_data;
-   struct dpu_perf_cfg *cfg = >catalog->perf;
+   const struct dpu_perf_cfg *cfg = >catalog->perf;
u32 perf_mode = 0;
int ret;
 
@@ -468,7 +468,7 @@ static const struct file_operations dpu_core_perf_mode_fops 
= {
 int dpu_core_perf_debugfs_init(struct dpu_kms *dpu_kms, struct dentry *parent)
 {
struct dpu_core_perf *perf = _kms->perf;
-   struct dpu_mdss_cfg *catalog = perf->catalog;
+   const struct dpu_mdss_cfg *catalog = perf->catalog;
struct dentry *entry;
 
entry = debugfs_create_dir("core_perf", parent);
@@ -517,7 +517,7 @@ void dpu_core_perf_destroy(struct dpu_core_perf *perf)
 
 int dpu_core_perf_init(struct dpu_core_perf *perf,
struct drm_device *dev,
-   struct dpu_mdss_cfg *catalog,
+   const struct dpu_mdss_cfg *catalog,
struct clk *core_clk)
 {
perf->dev = dev;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h
index 8dfcc6db7176..e3795995e145 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h
@@ -68,7 +68,7 @@ struct dpu_core_perf_tune {
 struct dpu_core_perf {
struct drm_device *dev;
struct dentry *debugfs_root;
-   struct dpu_mdss_cfg *catalog;
+   const struct dpu_mdss_cfg *catalog;
struct clk *core_clk;
u64 core_clk_rate;
u64 max_core_clk_rate;
@@ -119,7 +119,7 @@ void dpu_core_perf_destroy(struct dpu_core_perf *perf);
  */
 int dpu_core_perf_init(struct dpu_core_perf *perf,
struct drm_device *dev,
-   struct dpu_mdss_cfg *catalog,
+   const struct dpu_mdss_cfg *catalog,
struct clk *core_clk);
 
 struct dpu_kms;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 52516eb20cb8..460df2a4831c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1207,7 +1207,7 @@ static void dpu_encoder_virt_disable(struct drm_encoder 
*drm_enc)
mutex_unlock(_enc->enc_lock);
 }
 
-static enum dpu_intf dpu_encoder_get_intf(struct dpu_mdss_cfg *catalog,
+static enum dpu_intf dpu_encoder_get_intf(const struct dpu_mdss_cfg *catalog,
enum dpu_intf_type type, u32 controller_id)
 {
int i = 0;
@@ -1224,7 +1224,7 @@ static enum dpu_intf dpu_encoder_get_intf(struct 
dpu_mdss_cfg *catalog,
return INTF_MAX;
 }
 
-static enum dpu_wb dpu_encoder_get_wb(struct dpu_mdss_cfg *catalog,
+static enum dpu_wb dpu_encoder_get_wb(const struct dpu_mdss_cfg *catalog,
enum dpu_intf_type type, u32 controller_id)
 {
int i = 0;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
index 4829d1ce0cf8..53bb4639c8e9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
@@ -103,8 +103,8 @@ static void dpu_encoder_phys_wb_set_qos(struct 
dpu_encoder_phys *phys_enc)
 {
struct dpu_hw_wb *hw_wb;
struct dpu_hw_wb_qos_cfg qos_cfg;
-   struct dpu_mdss_cfg *catalog;
-

[Freedreno] [PATCH v1 2/5] drm/msm/dpu: move VBIF_XINL_QOS_LVL_REMAP size to hw_catalog

2022-06-01 Thread Dmitry Baryshkov

Rather than detecting VBIF_XINL_QOS_LVL_REMAP_000 based on the
hwversion, push the offset to the hw_catalog.

Signed-off-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c| 4 ++--
 3 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 78c7d987c2ca..cff6fe3a85ac 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -1339,6 +1339,7 @@ static const struct dpu_vbif_cfg msm8998_vbif[] = {
.default_ot_wr_limit = 32,
.features = BIT(DPU_VBIF_QOS_REMAP) | BIT(DPU_VBIF_QOS_OTLIM),
.xin_halt_timeout = 0x4000,
+   .qos_rp_remap_size = 0x20,
.dynamic_ot_rd_tbl = {
.count = ARRAY_SIZE(msm8998_ot_rdwr_cfg),
.cfg = msm8998_ot_rdwr_cfg,
@@ -1366,6 +1367,7 @@ static const struct dpu_vbif_cfg sdm845_vbif[] = {
.base = 0, .len = 0x1040,
.features = BIT(DPU_VBIF_QOS_REMAP),
.xin_halt_timeout = 0x4000,
+   .qos_rp_remap_size = 0x40,
.qos_rt_tbl = {
.npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
.priority_lvl = sdm845_rt_pri_lvl,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 80bc09b1f1b3..f70de97f492a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -709,6 +709,7 @@ struct dpu_vbif_qos_tbl {
  * @ot_rd_limitdefault OT read limit
  * @ot_wr_limitdefault OT write limit
  * @xin_halt_timeout   maximum time (in usec) for xin to halt
+ * @qos_rp_remap_size  size of VBIF_XINL_QOS_RP_REMAP register space
  * @dynamic_ot_rd_tbl  dynamic OT read configuration table
  * @dynamic_ot_wr_tbl  dynamic OT write configuration table
  * @qos_rt_tbl real-time QoS priority table
@@ -721,6 +722,7 @@ struct dpu_vbif_cfg {
u32 default_ot_rd_limit;
u32 default_ot_wr_limit;
u32 xin_halt_timeout;
+   u32 qos_rp_remap_size;
struct dpu_vbif_dynamic_ot_tbl dynamic_ot_rd_tbl;
struct dpu_vbif_dynamic_ot_tbl dynamic_ot_wr_tbl;
struct dpu_vbif_qos_tbl qos_rt_tbl;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
index b757054e1c23..046854c3fbed 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
@@ -30,7 +30,7 @@
 #define VBIF_XIN_HALT_CTRL00x0200
 #define VBIF_XIN_HALT_CTRL10x0204
 #define VBIF_XINL_QOS_RP_REMAP_000 0x0550
-#define VBIF_XINL_QOS_LVL_REMAP_000(v) (v < DPU_HW_VER_400 ? 0x570 : 0x0590)
+#define VBIF_XINL_QOS_LVL_REMAP_000(vbif)  (VBIF_XINL_QOS_RP_REMAP_000 + 
(vbif)->cap->qos_rp_remap_size)
 
 static void dpu_hw_clear_errors(struct dpu_hw_vbif *vbif,
u32 *pnd_errors, u32 *src_errors)
@@ -163,7 +163,7 @@ static void dpu_hw_set_qos_remap(struct dpu_hw_vbif *vbif,
 
c = >hw;
 
-   reg_lvl = VBIF_XINL_QOS_LVL_REMAP_000(c->hwversion);
+   reg_lvl = VBIF_XINL_QOS_LVL_REMAP_000(vbif);
reg_high = ((xin_id & 0x8) >> 3) * 4 + (level * 8);
reg_shift = (xin_id & 0x7) * 4;
 
-- 
2.35.1

[Freedreno] [PATCH v1 1/5] drm/msm/dpu: use feature bit for LM combined alpha check

2022-06-01 Thread Dmitry Baryshkov

Rather than checking hwversion, follow the usual patter and add special
bit to the lm->features to check whether the LM has combined or separate
alpha registers. While we are at it, rename
dpu_hw_lm_setup_blend_config_sdm845() to
dpu_hw_lm_setup_blend_config_combined_alpha().

Signed-off-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 17 ++---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |  2 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c  |  6 +++---
 3 files changed, 15 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 400ebceb56bb..78c7d987c2ca 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -50,9 +50,12 @@
 #define DMA_CURSOR_MSM8998_MASK \
(DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR))
 
-#define MIXER_SDM845_MASK \
+#define MIXER_MSM8998_MASK \
(BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER))
 
+#define MIXER_SDM845_MASK \
+   (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER) | 
BIT(DPU_MIXER_COMBINED_ALPHA))
+
 #define MIXER_SC7180_MASK \
(BIT(DPU_DIM_LAYER))
 
@@ -936,17 +939,17 @@ static const struct dpu_lm_sub_blks msm8998_lm_sblk = {
 };
 
 static const struct dpu_lm_cfg msm8998_lm[] = {
-   LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
+   LM_BLK("lm_0", LM_0, 0x44000, MIXER_MSM8998_MASK,
_lm_sblk, PINGPONG_0, LM_2, DSPP_0),
-   LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
+   LM_BLK("lm_1", LM_1, 0x45000, MIXER_MSM8998_MASK,
_lm_sblk, PINGPONG_1, LM_5, DSPP_1),
-   LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
+   LM_BLK("lm_2", LM_2, 0x46000, MIXER_MSM8998_MASK,
_lm_sblk, PINGPONG_2, LM_0, 0),
-   LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
+   LM_BLK("lm_3", LM_3, 0x47000, MIXER_MSM8998_MASK,
_lm_sblk, PINGPONG_MAX, 0, 0),
-   LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK,
+   LM_BLK("lm_4", LM_4, 0x48000, MIXER_MSM8998_MASK,
_lm_sblk, PINGPONG_MAX, 0, 0),
-   LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
+   LM_BLK("lm_5", LM_5, 0x49000, MIXER_MSM8998_MASK,
_lm_sblk, PINGPONG_3, LM_1, 0),
 };
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 8cb6d1f25bf9..80bc09b1f1b3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -145,6 +145,7 @@ enum {
  * @DPU_MIXER_SOURCESPLIT Layer mixer supports source-split configuration
  * @DPU_MIXER_GC  Gamma correction block
  * @DPU_DIM_LAYER Layer mixer supports dim layer
+ * @DPU_MIXER_COMBINED_ALPHA  Layer mixer has combined alpha register
  * @DPU_MIXER_MAX maximum value
  */
 enum {
@@ -152,6 +153,7 @@ enum {
DPU_MIXER_SOURCESPLIT,
DPU_MIXER_GC,
DPU_DIM_LAYER,
+   DPU_MIXER_COMBINED_ALPHA,
DPU_MIXER_MAX
 };
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
index 462f5082099e..25d2eba28e71 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
@@ -148,7 +148,7 @@ static int dpu_hw_lm_collect_misr(struct dpu_hw_mixer *ctx, 
u32 *misr_value)
return 0;
 }
 
-static void dpu_hw_lm_setup_blend_config_sdm845(struct dpu_hw_mixer *ctx,
+static void dpu_hw_lm_setup_blend_config_combined_alpha(struct dpu_hw_mixer 
*ctx,
u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op)
 {
struct dpu_hw_blk_reg_map *c = >hw;
@@ -204,8 +204,8 @@ static void _setup_mixer_ops(const struct dpu_mdss_cfg *m,
unsigned long features)
 {
ops->setup_mixer_out = dpu_hw_lm_setup_out;
-   if (m->hwversion >= DPU_HW_VER_400)
-   ops->setup_blend_config = dpu_hw_lm_setup_blend_config_sdm845;
+   if (test_bit(DPU_MIXER_COMBINED_ALPHA, ))
+   ops->setup_blend_config = 
dpu_hw_lm_setup_blend_config_combined_alpha;
else
ops->setup_blend_config = dpu_hw_lm_setup_blend_config;
ops->setup_alpha_out = dpu_hw_lm_setup_color3;
-- 
2.35.1

[Freedreno] [PATCH v1 0/5] drm/msm: clean up the hw catalog init

2022-06-01 Thread Dmitry Baryshkov

Replace superfluous cfg_init functions, which just assign a static
config to the struct dpu_mdss_cfg, with static instances of struct
dpu_mdss_cfg.

Dmitry Baryshkov (5):
  drm/msm/dpu: use feature bit for LM combined alpha check
  drm/msm/dpu: move VBIF_XINL_QOS_LVL_REMAP size to hw_catalog
  drm/msm/dpu: remove hwversion field from data structures
  drm/msm/dpu: constify struct dpu_mdss_cfg
  drm/msm/dpu: make dpu hardware catalog static const

 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c |   6 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h |   4 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c   |   4 +-
 .../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c   |   4 +-
 .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 500 --
 .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h|  16 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c|   1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c|   5 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h|   2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c   |   1 -
 .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c |   5 +-
 .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h |   2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c   |   1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c |   7 +-
 .../gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c|   1 -
 .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c   |   1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c   |   5 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h   |   4 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c|   1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h   |   2 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c   |   5 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c |   1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c   |   6 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h   |   2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c |   2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c|   2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h|   2 +-
 27 files changed, 258 insertions(+), 334 deletions(-)

-- 
2.35.1

Re: [Freedreno] [PATCH v3] drm/probe-helper: Make 640x480 first if no EDID

2022-06-01 Thread Daniel Vetter

On Thu, May 26, 2022 at 09:01:03AM -0700, Doug Anderson wrote:
> Hi,
> 
> On Thu, May 26, 2022 at 8:42 AM Daniel Vetter  wrote:
> >
> > On Thu, 26 May 2022 at 03:28, Sean Paul  wrote:
> > >
> > > On Wed, May 25, 2022 at 9:26 AM Daniel Vetter  wrote:
> > > >
> > > > On Mon, May 23, 2022 at 05:59:02PM -0700, Doug Anderson wrote:
> > > > > Hi,
> > > > >
> > > > > On Fri, May 20, 2022 at 5:01 PM Doug Anderson  
> > > > > wrote:
> > > > > >
> > > > > > Hi,
> > > > > >
> > > > > > On Mon, May 16, 2022 at 3:28 AM Thomas Zimmermann 
> > > > > >  wrote:
> > > > > > >
> > > > > > > Hi Douglas,
> > > > > > >
> > > > > > > I understand that you're trying to tell userspace that the 
> > > > > > > modelist has
> > > > > > > been made up, but it's not something that should be done via 
> > > > > > > fragile
> > > > > > > heuristics IMHO.
> > > > > > >
> > > > > > > I looked at the Chromium source code that you linked, but I 
> > > > > > > cannot say
> > > > > > > whether it's doing the correct thing. It all depends on what your
> > > > > > > program needs.
> > > > > > >
> > > > > > > In that function, you could also search for 
> > > > > > > 'DRM_MODE_TYPE_USERDEF'.
> > > > > > > It's the mode that the user specified on the kernel command line. 
> > > > > > > If
> > > > > > > Chromium's automatic mode selection fails, you'd give your users 
> > > > > > > direct
> > > > > > > control over it.
> > > > > >
> > > > > > That doesn't really work for Chrome OS. Certainly a kernel hacker
> > > > > > could do this, but it's not something I could imagine us exposing to
> > > > > > an average user of a Chromebook.
> > > > > >
> > > > > >
> > > > > > > When there's no flagged mode or if
> > > > > > > /sys/class/drm/card<...>/status contains "unconnected", you can 
> > > > > > > assume
> > > > > > > that the modelist is artificial and try the modes in an 
> > > > > > > appropriate order.
> > > > > >
> > > > > > So "no flagged" means that nothing is marked as preferred, correct?
> > > > > >
> > > > > > ...so I guess what you're suggesting is that the order that the 
> > > > > > kernel
> > > > > > is presenting the modes to userspace is not ABI. If there are no
> > > > > > preferred modes then userspace shouldn't necessarily assume that the
> > > > > > first mode returned is the best mode. Instead it should assume that 
> > > > > > if
> > > > > > there is no preferred mode then the mode list is made up and it 
> > > > > > should
> > > > > > make its own decisions about the best mode to start with. If this is
> > > > > > the ABI from the kernel then plausibly I could convince people to
> > > > > > change userspace to pick 640x480 first in this case.
> > > > > >
> > > > > > > If we really want the kernel to give additional guarantees, we 
> > > > > > > should
> > > > > > > have a broader discussion about this topic IMHO.
> > > > > >
> > > > > > Sure. I've added Stéphane Marchesin to this thread in case he wants 
> > > > > > to
> > > > > > chime in about anything.
> > > > > >
> > > > > > Overall, my take on the matter:
> > > > > >
> > > > > > * Mostly I got involved because, apparently, a DP compliance test 
> > > > > > was
> > > > > > failing. The compliance test was upset that when it presented us 
> > > > > > with
> > > > > > no EDID that we didn't default to 640x480. There was a push to make 
> > > > > > a
> > > > > > fix for this in the Qualcomm specific driver but that didn't sit 
> > > > > > right
> > > > > > with me.
> > > > > >
> > > > > > * On all devices I'm currently working with (laptops), the DP is a
> > > > > > secondary display. If a user was trying to plug in a display with a
> > > > > > bad EDID and the max mode (1024x768) didn't work, they could just 
> > > > > > use
> > > > > > the primary display to choose a different resolution. It seems
> > > > > > unlikely a user would truly be upset and would probably be happy 
> > > > > > they
> > > > > > could get their broken display to work at all. Even if this is a
> > > > > > primary display, I believe there are documented key combos to change
> > > > > > the resolution of the primary display even if you can't see 
> > > > > > anything.
> > > > > >
> > > > > > * That all being said, defaulting to 640x480 when there's no EDID 
> > > > > > made
> > > > > > sense to me, especially since it's actually defined in the DP spec. 
> > > > > > So
> > > > > > I'm trying to do the right thing and solve this corner case. That
> > > > > > being said, if it's truly controversial I can just drop it.
> > > > > >
> > > > > >
> > > > > > So I guess my plan will be to give Stéphane a little while in case 
> > > > > > he
> > > > > > wants to chime in. If not then I guess I'll try a Chrome patch...
> > > > > > ...and if that doesn't work, I'll just drop it.
> > > > >
> > > > > OK, this userspace code seems to work:
> > > > >
> > > > > https://crrev.com/c/3662501 - ozone/drm: Try 640x480 before picking
> > > > > the first mode if no EDID
> > > > >
> > > > > ...so we'll see how review of that

Re: [Freedreno] [PATCH v2] drm/msm/dpu: Move min BW request and full BW disable back to mdss

2022-06-01 Thread Dmitry Baryshkov

On Wed, 1 Jun 2022 at 02:01, Douglas Anderson  wrote:
>
> In commit a670ff578f1f ("drm/msm/dpu: always use mdp device to scale
> bandwidth") we fully moved interconnect stuff to the DPU driver. This
> had no change for sc7180 but _did_ have an impact for other SoCs. It
> made them match the sc7180 scheme.

[skipped the description]

>
> Changes in v2:
> - Don't set bandwidth in init.
>
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c |  8 
>  drivers/gpu/drm/msm/msm_mdss.c  | 57 +
>  2 files changed, 57 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index 2b9d931474e0..3025184053e0 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -49,8 +49,6 @@
>  #define DPU_DEBUGFS_DIR "msm_dpu"
>  #define DPU_DEBUGFS_HWMASKNAME "hw_log_mask"
>
> -#define MIN_IB_BW  4ULL /* Min ib vote 400MB */
> -
>  static int dpu_kms_hw_init(struct msm_kms *kms);
>  static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms);
>

[skipped]

> diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
> index 0454a571adf7..e13c5c12b775 100644
> --- a/drivers/gpu/drm/msm/msm_mdss.c
> +++ b/drivers/gpu/drm/msm/msm_mdss.c
> @@ -5,6 +5,7 @@
>
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -25,6 +26,8 @@
>  #define UBWC_CTRL_20x150
>  #define UBWC_PREDICTION_MODE   0x154
>
> +#define MIN_IB_BW  4UL /* Min ib vote 400MB */

As msm_mdss is now used for both DPU and MDP5 devices, could you
please confirm that this value is valid for older devices too? E.g.
db410c or 8974

> +
>  struct msm_mdss {
> struct device *dev;
>

-- 
With best wishes
Dmitry

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