Re: [Freedreno] [2/2] drm: Remove struct drm_driver.gem_prime_mmap
Hi
Am 14.06.23 um 04:06 schrieb Sui Jingfeng:
On 2023/6/14 01:27, Sui Jingfeng wrote:
Wow, so many drivers get nuked!
On 2023/6/13 22:51, Thomas Zimmermann wrote:
All drivers initialize this field with drm_gem_prime_mmap(). Call
the function directly and remove the field. Simplifies the code and
resolves a long-standing TODO item.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Alex Deucher
I have tested this patch briefly with drm/amdgpu(RX560), Running
glmark2, the rendered scene looks OK.
But single driver is self-sharing. I think I should test this more
with multiple video card.
No need to test; it's equivalent to removing a wrapper.
Yes, only msm hardware might be affected.
But new DRM (un-upstreamed) drivers cannot be compiled anymore with this
patch applied.
This makes them all out-of-date or going to be outdated; this is
embarrassing!
What do you mean by embarrassing? Simply rebase your driver onto the
change and that's it. This happens regularly for out-of-tree drivers.
But if such a driver would land before this patchset, I'd have to update
the patchset instead.
Best regards
Thomas
---
Documentation/gpu/todo.rst | 9 -
drivers/accel/ivpu/ivpu_drv.c | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 -
drivers/gpu/drm/drm_fbdev_dma.c | 6 +-
drivers/gpu/drm/drm_prime.c | 14 ++
drivers/gpu/drm/etnaviv/etnaviv_drv.c | 1 -
drivers/gpu/drm/exynos/exynos_drm_drv.c | 1 -
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c | 1 -
drivers/gpu/drm/lima/lima_drv.c | 1 -
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 -
drivers/gpu/drm/msm/msm_drv.c | 1 -
drivers/gpu/drm/msm/msm_drv.h | 1 -
drivers/gpu/drm/msm/msm_gem_prime.c | 5 -
drivers/gpu/drm/nouveau/nouveau_drm.c | 1 -
drivers/gpu/drm/panfrost/panfrost_drv.c | 1 -
drivers/gpu/drm/pl111/pl111_drv.c | 1 -
drivers/gpu/drm/radeon/radeon_drv.c | 1 -
drivers/gpu/drm/renesas/rcar-du/rcar_du_drv.c | 1 -
drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 1 -
drivers/gpu/drm/v3d/v3d_drv.c | 1 -
drivers/gpu/drm/virtio/virtgpu_drv.c | 1 -
drivers/gpu/drm/xen/xen_drm_front.c | 1 -
include/drm/drm_drv.h | 14 --
include/drm/drm_gem_dma_helper.h | 6 ++
include/drm/drm_gem_shmem_helper.h | 1 -
include/drm/drm_gem_vram_helper.h | 1 -
26 files changed, 5 insertions(+), 69 deletions(-)
diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst
index 68bdafa0284f5..ca1efad8c89c3 100644
--- a/Documentation/gpu/todo.rst
+++ b/Documentation/gpu/todo.rst
@@ -319,15 +319,6 @@ Contact: Daniel Vetter, Noralf Tronnes
Level: Advanced
-struct drm_gem_object_funcs
-
-GEM objects can now have a function table instead of having the
callbacks on the
-DRM driver struct. This is now the preferred way. Callbacks in
drivers have been
-converted, except for struct drm_driver.gem_prime_mmap.
-
-Level: Intermediate
-
connector register/unregister fixes
---
diff --git a/drivers/accel/ivpu/ivpu_drv.c
b/drivers/accel/ivpu/ivpu_drv.c
index 2df7643b843d5..9f2b9fdcc5498 100644
--- a/drivers/accel/ivpu/ivpu_drv.c
+++ b/drivers/accel/ivpu/ivpu_drv.c
@@ -376,7 +376,6 @@ static const struct drm_driver driver = {
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
.gem_prime_import = ivpu_gem_prime_import,
- .gem_prime_mmap = drm_gem_prime_mmap,
.ioctls = ivpu_drm_ioctls,
.num_ioctls = ARRAY_SIZE(ivpu_drm_ioctls),
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index c9a41c997c6c7..7681f79f462eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -2809,7 +2809,6 @@ static const struct drm_driver
amdgpu_kms_driver = {
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
.gem_prime_import = amdgpu_gem_prime_import,
- .gem_prime_mmap = drm_gem_prime_mmap,
.name = DRIVER_NAME,
.desc = DRIVER_DESC,
diff --git a/drivers/gpu/drm/drm_fbdev_dma.c
b/drivers/gpu/drm/drm_fbdev_dma.c
index d86773fa8ab00..8217f1ddc0075 100644
--- a/drivers/gpu/drm/drm_fbdev_dma.c
+++ b/drivers/gpu/drm/drm_fbdev_dma.c
@@ -54,12 +54,8 @@ static void drm_fbdev_dma_fb_destroy(struct
fb_info *info)
static int drm_fbdev_dma_fb_mmap(struct fb_info *info, struct
vm_area_struct *vma)
{
struct drm_fb_helper *fb_helper = info->par;
- struct drm_device *dev = fb_helper->dev;
-
- if (drm_WARN_ON_ONCE(dev,
[Freedreno] [PATCH 3/3] drm/msm/dsi: Enable DATABUS_WIDEN for DSI command mode
DSI 6G v2.5.x+ supports a data-bus widen mode that allows DSI to send
48 bits of compressed data per pclk instead of 24.
For all chipsets that support this mode, enable it whenever DSC is
enabled as recommend by the hardware programming guide.
Only enable this for command mode as we are currently unable to validate
it for video mode.
Signed-off-by: Jessica Zhang
---
Note: The dsi.xml.h changes were generated using the headergen2 script in
envytools [1], but the changes to the copyright and rules-ng-ng source file
paths were dropped.
[1] https://github.com/freedreno/envytools/
drivers/gpu/drm/msm/dsi/dsi.xml.h | 1 +
drivers/gpu/drm/msm/dsi/dsi_host.c | 19 ++-
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h
b/drivers/gpu/drm/msm/dsi/dsi.xml.h
index a4a154601114..2a7d980e12c3 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.xml.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h
@@ -664,6 +664,7 @@ static inline uint32_t
DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP(enum dsi_rgb_swap v
return ((val) << DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__SHIFT) &
DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__MASK;
}
#define DSI_CMD_MODE_MDP_CTRL2_BURST_MODE 0x0001
+#define DSI_CMD_MODE_MDP_CTRL2_DATABUS_WIDEN 0x0010
#define REG_DSI_CMD_MODE_MDP_STREAM2_CTRL 0x01b8
#define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__MASK 0x003f
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 5d7b4409e4e9..1da5238e7105 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -927,6 +927,9 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host,
bool is_bonded_dsi)
u32 hdisplay = mode->hdisplay;
u32 wc;
int ret;
+ bool widebus_supported = msm_host->cfg_hnd->major ==
MSM_DSI_VER_MAJOR_6G &&
+ msm_host->cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V2_5_0;
+
DBG("");
@@ -973,8 +976,15 @@ static void dsi_timing_setup(struct msm_dsi_host
*msm_host, bool is_bonded_dsi)
*
* hdisplay will be divided by 3 here to account for the fact
* that DPU sends 3 bytes per pclk cycle to DSI.
+*
+* If widebus is supported, set DATABUS_WIDEN register and
divide hdisplay by 6
+* instead of 3
*/
- hdisplay =
DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc), 3);
+ if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) &&
widebus_supported)
+ hdisplay =
DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc), 6);
+ else
+ hdisplay =
DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc), 3);
+
h_total += hdisplay;
ha_end = ha_start + hdisplay;
}
@@ -1027,6 +1037,13 @@ static void dsi_timing_setup(struct msm_dsi_host
*msm_host, bool is_bonded_dsi)
dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_TOTAL,
DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(hdisplay) |
DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(mode->vdisplay));
+
+ if (msm_host->dsc && widebus_supported) {
+ u32 mdp_ctrl2 = dsi_read(msm_host,
REG_DSI_CMD_MODE_MDP_CTRL2);
+
+ mdp_ctrl2 |= DSI_CMD_MODE_MDP_CTRL2_DATABUS_WIDEN;
+ dsi_write(msm_host, REG_DSI_CMD_MODE_MDP_CTRL2,
mdp_ctrl2);
+ }
}
}
--
2.40.1
[Freedreno] [PATCH 2/3] drm/msm/dpu: Set DATABUS_WIDEN on command mode encoders
Add a DPU INTF op to set the DATABUS_WIDEN register to enable the
databus-widen mode datapath.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 3 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 12
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 3 +++
3 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index b856c6286c85..124ba96bebda 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -70,6 +70,9 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg(
if (intf_cfg.dsc != 0 && phys_enc->hw_intf->ops.enable_compression)
phys_enc->hw_intf->ops.enable_compression(phys_enc->hw_intf);
+
+ if (phys_enc->hw_intf->ops.enable_widebus)
+ phys_enc->hw_intf->ops.enable_widebus(phys_enc->hw_intf);
}
static void dpu_encoder_phys_cmd_pp_tx_done_irq(void *arg, int irq_idx)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 5b0f6627e29b..03ba3a1c7a46 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -513,6 +513,15 @@ static void dpu_hw_intf_disable_autorefresh(struct
dpu_hw_intf *intf,
}
+static void dpu_hw_intf_enable_widebus(struct dpu_hw_intf *ctx)
+{
+ u32 intf_cfg2 = DPU_REG_READ(>hw, INTF_CONFIG2);
+
+ intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN;
+
+ DPU_REG_WRITE(>hw, INTF_CONFIG2, intf_cfg2);
+}
+
static void dpu_hw_intf_enable_compression(struct dpu_hw_intf *ctx)
{
u32 intf_cfg2 = DPU_REG_READ(>hw, INTF_CONFIG2);
@@ -545,6 +554,9 @@ static void _setup_intf_ops(struct dpu_hw_intf_ops *ops,
if (cap & BIT(DPU_INTF_DATA_COMPRESS))
ops->enable_compression = dpu_hw_intf_enable_compression;
+
+ if (cap & BIT(DPU_INTF_DATABUS_WIDEN))
+ ops->enable_widebus = dpu_hw_intf_enable_widebus;
}
struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
index 99e21c4137f9..64a17b99d3d1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
@@ -71,6 +71,7 @@ struct intf_status {
* Return: 0 on success, -ETIMEDOUT on timeout
* @vsync_sel: Select vsync signal for tear-effect
configuration
* @enable_compression: Enable data compression
+ * @enable_widebus: Enable widebus
*/
struct dpu_hw_intf_ops {
void (*setup_timing_gen)(struct dpu_hw_intf *intf,
@@ -109,6 +110,8 @@ struct dpu_hw_intf_ops {
void (*disable_autorefresh)(struct dpu_hw_intf *intf, uint32_t
encoder_id, u16 vdisplay);
void (*enable_compression)(struct dpu_hw_intf *intf);
+
+ void (*enable_widebus)(struct dpu_hw_intf *intf);
};
struct dpu_hw_intf {
--
2.40.1
[Freedreno] [PATCH 1/3] drm/msm/dpu: Add DPU_INTF_DATABUS_WIDEN feature flag for DPU >= 5.0
DPU 5.x+ supports a databus widen mode that allows more data to be sent
per pclk. Enable this feature flag on all relevant chipsets.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 36ba3f58dcdf..0be7bf0bfc41 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -103,7 +103,8 @@
(BIT(DPU_INTF_INPUT_CTRL) | \
BIT(DPU_INTF_TE) | \
BIT(DPU_INTF_STATUS_SUPPORTED) | \
-BIT(DPU_DATA_HCTL_EN))
+BIT(DPU_DATA_HCTL_EN) | \
+BIT(DPU_INTF_DATABUS_WIDEN))
#define INTF_SC7280_MASK (INTF_SC7180_MASK | BIT(DPU_INTF_DATA_COMPRESS))
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index b860784ade72..b9939e00f5e0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -182,6 +182,7 @@ enum {
* than video timing
* @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register
* @DPU_INTF_DATA_COMPRESS INTF block has DATA_COMPRESS register
+ * @DPU_INTF_DATABUS_WIDEN INTF block has DATABUS_WIDEN register
* @DPU_INTF_MAX
*/
enum {
@@ -190,6 +191,7 @@ enum {
DPU_DATA_HCTL_EN,
DPU_INTF_STATUS_SUPPORTED,
DPU_INTF_DATA_COMPRESS,
+ DPU_INTF_DATABUS_WIDEN,
DPU_INTF_MAX
};
--
2.40.1
[Freedreno] [PATCH 0/3] Add support for databus widen mode
DPU 5.x+ and DSI 6G 2.5.x+ support a databus-widen mode that allows for more compressed data to be transferred per pclk. This series adds support for enabling this feature for both DPU and DSI by doing the following: 1. Add a DPU_INTF_DATABUS_WIDEN feature flag 2. Add a DPU INTF op to set the DATABUS_WIDEN register 3. Set the DATABUS_WIDEN register and do the proper hdisplay calculations in DSI when applicable Note: This series will only enable the databus-widen mode for command mode as we are currently unable to validate it on video mode. Depends on: "Add DSC v1.2 Support for DSI" [1] [1] https://patchwork.freedesktop.org/series/117219/ Signed-off-by: Jessica Zhang --- Jessica Zhang (3): drm/msm/dpu: Add DPU_INTF_DATABUS_WIDEN feature flag for DPU >= 5.0 drm/msm/dpu: Set DATABUS_WIDEN on command mode encoders drm/msm/dsi: Enable DATABUS_WIDEN for DSI command mode drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 3 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 12 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 3 +++ drivers/gpu/drm/msm/dsi/dsi.xml.h| 1 + drivers/gpu/drm/msm/dsi/dsi_host.c | 19 ++- 7 files changed, 41 insertions(+), 2 deletions(-) --- base-commit: 1981c2c0c05f5d7fe4d4552d4f352cb46840e51e change-id: 20230525-add-widebus-support-f785546ee751 Best regards, -- Jessica Zhang
Re: [Freedreno] [PATCH v2 05/22] drm/msm/dpu: always use MSM_DP/DSI_CONTROLLER_n
On 6/12/2023 5:09 PM, Dmitry Baryshkov wrote: In several catalog entries we did not use existing MSM_DP_CONTROLLER_n constants. Fill them in. Also use freshly defined MSM_DSI_CONTROLLER_n for DSI interfaces. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 6 +++--- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 8 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 8 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 8 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 4 ++-- 13 files changed, 29 insertions(+), 29 deletions(-) Patch itself is fine. But sm6375 and sm6350 are missing as this needs to be rebased on top of the tip of msm-next-lumag.
Re: [Freedreno] [PATCH v3 2/2] drm/msm/dpu: remove struct drm_dsc_config from struct msm_display_info
On 6/13/2023 3:19 PM, Kuogee Hsieh wrote:
ince struct drm_dsc_config is stored at atomic_enable() instead
S got cut off in since
of display setup time during boot up, saving struct drm_dsc_config
at struct msm_display_info is not necessary. Lets drop the dsc member
from struct msm_display_info.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 --
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 2 --
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 --
3 files changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index e00cd39..50ce2ef 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -2309,8 +2309,6 @@ static int dpu_encoder_setup_display(struct
dpu_encoder_virt *dpu_enc,
dpu_enc->idle_pc_supported =
dpu_kms->catalog->caps->has_idle_pc;
- dpu_enc->dsc = disp_info->dsc;
-
mutex_lock(_enc->enc_lock);
for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
/*
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index 90e1925..4c05fd5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -28,7 +28,6 @@
* @is_cmd_mode Boolean to indicate if the CMD mode is requested
* @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is
* used instead of panel TE in cmd mode panels
- * @dsc: DSC configuration data for DSC-enabled displays
*/
struct msm_display_info {
enum dpu_intf_type intf_type;
@@ -36,7 +35,6 @@ struct msm_display_info {
uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
bool is_cmd_mode;
bool is_te_using_watchdog_timer;
- struct drm_dsc_config *dsc;
};
/**
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 613384b..5e77e09 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -544,8 +544,6 @@ static int _dpu_kms_initialize_dsi(struct drm_device *dev,
info.is_cmd_mode = msm_dsi_is_cmd_mode(priv->dsi[i]);
- info.dsc = msm_dsi_get_dsc_config(priv->dsi[i]);
-
encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_DSI, );
if (IS_ERR(encoder)) {
DPU_ERROR("encoder init failed for dsi display\n");
Re: [Freedreno] [PATCH v3 0/2] retrieve DSI DSC through priv-dsi[0]
On 6/13/2023 3:19 PM, Kuogee Hsieh wrote: moving retrieving struct drm_dsc_cofnig from setup_display to atomic_enable() and delete struct drm_dsc_config from struct msm_display_info. This needs re-wording. Currently, struct drm_dsc_config is retrieved from DSI driver in dpu_encoder_setup_display() and this model works for non-pluggable displays. However this does not scale for pluggable displays because the struct drm_dsc_config is no longer valid after a disconnect and needs to be retrieved from the sink again. Move retrieval of struct drm_dsc_config from dpu_encoder_setup_display() to dpu_encoder_virt_atomic_enable() to make the code path common between pluggable and non-pluggable displays. And also delete struct drm_dsc_config from struct msm_display_info as it will now be unused. Kuogee Hsieh (2): drm/msm/dpu: retrieve DSI DSC struct through priv->dsi[0] drm/msm/dpu: remove struct drm_dsc_config from struct msm_display_info drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 44 - drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 -- 3 files changed, 30 insertions(+), 18 deletions(-)
Re: [Freedreno] [PATCH v4 0/2] arm64: dts: qcom: add DP Controller to SM8550 DTS
On Tue, 13 Jun 2023 09:30:11 +0200, Neil Armstrong wrote: > The DP output is shared with the USB3 SuperSpeed lanes and is > usually connected to an USB-C port which Altmode is controlled > by the PMIC Glink infrastructure. > > DT changes tying the DP controller to the USB-C port on the QRD > board will be sent later. > > [...] Applied, thanks! [1/2] arm64: dts: qcom: sm8550: fix low_svs RPMhPD labels commit: bbde65f9da9291a77636e1467b28f27ced1b4ece [2/2] arm64: dts: qcom: sm8550: add display port nodes commit: 66adfbc4d33993865a180016db73520a15e754c9 Best regards, -- Bjorn Andersson
[Freedreno] [PATCH v3 0/2] retrieve DSI DSC through priv-dsi[0]
moving retrieving struct drm_dsc_cofnig from setup_display to atomic_enable() and delete struct drm_dsc_config from struct msm_display_info. Kuogee Hsieh (2): drm/msm/dpu: retrieve DSI DSC struct through priv->dsi[0] drm/msm/dpu: remove struct drm_dsc_config from struct msm_display_info drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 44 - drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 -- 3 files changed, 30 insertions(+), 18 deletions(-) -- 2.7.4
[Freedreno] [PATCH v3 2/2] drm/msm/dpu: remove struct drm_dsc_config from struct msm_display_info
ince struct drm_dsc_config is stored at atomic_enable() instead
of display setup time during boot up, saving struct drm_dsc_config
at struct msm_display_info is not necessary. Lets drop the dsc member
from struct msm_display_info.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 --
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 2 --
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 --
3 files changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index e00cd39..50ce2ef 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -2309,8 +2309,6 @@ static int dpu_encoder_setup_display(struct
dpu_encoder_virt *dpu_enc,
dpu_enc->idle_pc_supported =
dpu_kms->catalog->caps->has_idle_pc;
- dpu_enc->dsc = disp_info->dsc;
-
mutex_lock(_enc->enc_lock);
for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
/*
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index 90e1925..4c05fd5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -28,7 +28,6 @@
* @is_cmd_modeBoolean to indicate if the CMD mode is requested
* @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is
* used instead of panel TE in cmd mode panels
- * @dsc: DSC configuration data for DSC-enabled displays
*/
struct msm_display_info {
enum dpu_intf_type intf_type;
@@ -36,7 +35,6 @@ struct msm_display_info {
uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
bool is_cmd_mode;
bool is_te_using_watchdog_timer;
- struct drm_dsc_config *dsc;
};
/**
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 613384b..5e77e09 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -544,8 +544,6 @@ static int _dpu_kms_initialize_dsi(struct drm_device *dev,
info.is_cmd_mode = msm_dsi_is_cmd_mode(priv->dsi[i]);
- info.dsc = msm_dsi_get_dsc_config(priv->dsi[i]);
-
encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_DSI, );
if (IS_ERR(encoder)) {
DPU_ERROR("encoder init failed for dsi display\n");
--
2.7.4
[Freedreno] [PATCH v3 1/2] drm/msm/dpu: retrieve DSI DSC struct through priv->dsi[0]
Currently struct drm_dsc_config for DSI is populated at display
setup during system boot up. This mechanism works fine with
embedded display but not for pluggable displays as the
struct drm_dsc_config will become stale once external display
is unplugged.
Move storing of DSI DSC struct to atomic_enable() so that same
mechanism will work for both embedded display and pluggable
displays.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 42 -
1 file changed, 30 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 2e1873d..e00cd39 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -543,11 +543,24 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder
*drm_enc)
return (num_dsc > 0) && (num_dsc > intf_count);
}
+static struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder
*drm_enc)
+{
+ struct msm_drm_private *priv = drm_enc->dev->dev_private;
+ struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
+ int index = dpu_enc->disp_info.h_tile_instance[0];
+
+if (dpu_enc->disp_info.intf_type == INTF_DSI)
+ return msm_dsi_get_dsc_config(priv->dsi[index]);
+
+ return NULL;
+}
+
static struct msm_display_topology dpu_encoder_get_topology(
struct dpu_encoder_virt *dpu_enc,
struct dpu_kms *dpu_kms,
struct drm_display_mode *mode,
- struct drm_crtc_state *crtc_state)
+ struct drm_crtc_state *crtc_state,
+ struct drm_dsc_config *dsc)
{
struct msm_display_topology topology = {0};
int i, intf_count = 0;
@@ -579,7 +592,7 @@ static struct msm_display_topology dpu_encoder_get_topology(
topology.num_intf = intf_count;
- if (dpu_enc->dsc) {
+ if (dsc) {
/*
* In case of Display Stream Compression (DSC), we would use
* 2 DSC encoders, 2 layer mixers and 1 interface
@@ -605,6 +618,7 @@ static int dpu_encoder_virt_atomic_check(
struct drm_display_mode *adj_mode;
struct msm_display_topology topology;
struct dpu_global_state *global_state;
+ struct drm_dsc_config *dsc;
int i = 0;
int ret = 0;
@@ -640,7 +654,9 @@ static int dpu_encoder_virt_atomic_check(
}
}
- topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode,
crtc_state);
+ dsc = dpu_encoder_get_dsc_config(drm_enc);
+
+ topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode,
crtc_state, dsc);
/*
* Release and Allocate resources on every modeset
@@ -1072,14 +1088,12 @@ static void dpu_encoder_virt_atomic_mode_set(struct
drm_encoder *drm_enc,
dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i])
: NULL;
- if (dpu_enc->dsc) {
- num_dsc = dpu_rm_get_assigned_resources(_kms->rm,
global_state,
- drm_enc->base.id,
DPU_HW_BLK_DSC,
- hw_dsc,
ARRAY_SIZE(hw_dsc));
- for (i = 0; i < num_dsc; i++) {
- dpu_enc->hw_dsc[i] = to_dpu_hw_dsc(hw_dsc[i]);
- dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0);
- }
+ num_dsc = dpu_rm_get_assigned_resources(_kms->rm, global_state,
+ drm_enc->base.id,
DPU_HW_BLK_DSC,
+ hw_dsc, ARRAY_SIZE(hw_dsc));
+ for (i = 0; i < num_dsc; i++) {
+ dpu_enc->hw_dsc[i] = to_dpu_hw_dsc(hw_dsc[i]);
+ dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0);
}
dpu_enc->dsc_mask = dsc_mask;
@@ -1187,6 +1201,8 @@ static void dpu_encoder_virt_atomic_enable(struct
drm_encoder *drm_enc,
dpu_enc = to_dpu_encoder_virt(drm_enc);
+ dpu_enc->dsc = dpu_encoder_get_dsc_config(drm_enc);
+
mutex_lock(_enc->enc_lock);
cur_mode = _enc->base.crtc->state->adjusted_mode;
@@ -2109,8 +2125,10 @@ void dpu_encoder_helper_phys_cleanup(struct
dpu_encoder_phys *phys_enc)
phys_enc->hw_pp->merge_3d->idx);
}
- if (dpu_enc->dsc)
+ if (dpu_enc->dsc) {
dpu_encoder_unprep_dsc(dpu_enc);
+ dpu_enc->dsc = NULL;
+ }
intf_cfg.stream_sel = 0; /* Don't care value for video mode */
intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
--
2.7.4
Re: [Freedreno] [PATCH v2 04/22] drm/msm: enumerate DSI interfaces
On 6/12/2023 5:09 PM, Dmitry Baryshkov wrote: Follow the DP example and define MSM_DSI_CONTROLLER_n enumeration. Signed-off-by: Dmitry Baryshkov --- Reviewed-by: Abhinav Kumar
Re: [Freedreno] [PATCH v2 03/22] drm/msm/dpu: remove unused INTF_NONE interfaces
On 6/12/2023 5:09 PM, Dmitry Baryshkov wrote: sm6115 and qcm2290 do not have INTF_0. Drop corresponding interface definitions. And sm6375 as you are touching that too Signed-off-by: Dmitry Baryshkov --- You can fix that while applying. Reviewed-by: Abhinav Kumar
Re: [Freedreno] [PATCH v2 02/22] drm/msm/dpu: correct MERGE_3D length
On 6/12/2023 5:09 PM, Dmitry Baryshkov wrote:
Each MERGE_3D block has just two registers. Correct the block length
accordingly.
Fixes: 4369c93cf36b ("drm/msm/dpu: initial support for merge3D hardware block")
Signed-off-by: Dmitry Baryshkov
---
LGTM,
Reviewed-by: Abhinav Kumar
Re: [Freedreno] [PATCH v2 01/22] drm/msm/dpu: fix sc7280 and sc7180 PINGPONG done interrupts
On 6/12/2023 5:09 PM, Dmitry Baryshkov wrote:
During IRQ conversion we have lost the PP_DONE interrupts for sc7280
platform. This was left unnoticed, because this interrupt is only used
for CMD outputs and probably no sc7[12]80 systems use DSI CMD panels.
Fixes: 667e9985ee24 ("drm/msm/dpu: replace IRQ lookup with the data in hw
catalog")
Signed-off-by: Dmitry Baryshkov
---
Yes, was indeed a mistake
Reviewed-by: Abhinav Kumar
Re: [Freedreno] [PATCH] drm/msm/dp: Drop aux devices together with DP controller
Hi Doug On 6/13/2023 12:33 PM, Doug Anderson wrote: Hi, On Mon, Jun 12, 2023 at 3:40 PM Dmitry Baryshkov wrote: On 13/06/2023 01:01, Bjorn Andersson wrote: Using devres to depopulate the aux bus made sure that upon a probe deferral the EDP panel device would be destroyed and recreated upon next attempt. But the struct device which the devres is tied to is the DPUs (drm_dev->dev), which may be happen after the DP controller is torn down. Indications of this can be seen in the commonly seen EDID-hexdump full of zeros in the log, or the occasional/rare KASAN fault where the panel's attempt to read the EDID information causes a use after free on DP resources. It's tempting to move the devres to the DP controller's struct device, but the resources used by the device(s) on the aux bus are explicitly torn down in the error path. I hoped that proper usage of of_dp_aux_populate_bus(), with the callback function being non-NULL would have solved at least this part. But it seems I'll never see this patch. Agreed. This has been pending for > 1 year now with no significant progress. Abhinav: Is there anything that can be done about this? Not following up on agreed-to cleanups in a timely manner doesn't set a good precedent. Next time the Qualcomm display wants to land something and promises to land a followup people will be less likely to believe them... Both QC and Google know there were other factors which delayed this last 3-4 months. But, I do not have any concrete justification to give you for the delays before that apart from perhaps other higher priority chrome and upstream bugs which kept cropping up. Hence, all I can offer is my apologies for the delay. After seeing this patch on the list, we have revived this effort now and re-assigned this within our team to take over from where that was left off. It will need some time to transition but this will see the end of the tunnel soon. Thanks Abhinav
Re: [Freedreno] [PATCH] drm/msm/dp: Drop aux devices together with DP controller
Hi,
On Mon, Jun 12, 2023 at 3:40 PM Dmitry Baryshkov
wrote:
>
> On 13/06/2023 01:01, Bjorn Andersson wrote:
> > Using devres to depopulate the aux bus made sure that upon a probe
> > deferral the EDP panel device would be destroyed and recreated upon next
> > attempt.
> >
> > But the struct device which the devres is tied to is the DPUs
> > (drm_dev->dev), which may be happen after the DP controller is torn
> > down.
> >
> > Indications of this can be seen in the commonly seen EDID-hexdump full
> > of zeros in the log, or the occasional/rare KASAN fault where the
> > panel's attempt to read the EDID information causes a use after free on
> > DP resources.
> >
> > It's tempting to move the devres to the DP controller's struct device,
> > but the resources used by the device(s) on the aux bus are explicitly
> > torn down in the error path.
>
> I hoped that proper usage of of_dp_aux_populate_bus(), with the callback
> function being non-NULL would have solved at least this part. But it
> seems I'll never see this patch.
Agreed. This has been pending for > 1 year now with no significant
progress. Abhinav: Is there anything that can be done about this? Not
following up on agreed-to cleanups in a timely manner doesn't set a
good precedent. Next time the Qualcomm display wants to land something
and promises to land a followup people will be less likely to believe
them...
> > The KASAN-reported use-after-free also
> > remains, as the DP aux "module" explicitly frees its devres-allocated
> > memory in this code path.
> >
> > As such, explicitly depopulate the aux bus in the error path, and in the
> > component unbind path, to avoid these issues.
> >
> > Fixes: 2b57f726611e ("drm/msm/dp: fix aux-bus EP lifetime")
> > Signed-off-by: Bjorn Andersson
>
> Reviewed-by: Dmitry Baryshkov
Reviewed-by: Douglas Anderson
Re: [Freedreno] [PATCH v6 4/6] drm/msm/dpu: Set DATA_COMPRESS on command mode for DCE/DSC 1.2
On 2023-06-09 15:57:16, Jessica Zhang wrote:
> Add a DPU INTF op to set the DCE_DATA_COMPRESS bit to enable the
> DCE/DSC 1.2 datapath
>
> Note: For now, this op is called for command mode encoders only. Changes to
> set DATA_COMPRESS for video mode encoders will be posted along with DSC
> v1.2 support for DP.
>
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 3 +++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 13 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 3 +++
> 3 files changed, 19 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> index 63ba0082b6ee..b856c6286c85 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> @@ -67,6 +67,9 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg(
> phys_enc->hw_intf->ops.bind_pingpong_blk(
> phys_enc->hw_intf,
> phys_enc->hw_pp->idx);
> +
> + if (intf_cfg.dsc != 0 && phys_enc->hw_intf->ops.enable_compression)
> + phys_enc->hw_intf->ops.enable_compression(phys_enc->hw_intf);
It was probably not necessary to drop this after adding dsc!=0:
Reviewed-by: Marijn Suijten
> }
>
> static void dpu_encoder_phys_cmd_pp_tx_done_irq(void *arg, int irq_idx)
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> index 530f82e34c1e..5b0f6627e29b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> @@ -91,6 +91,7 @@
>
> #define INTF_CFG2_DATABUS_WIDEN BIT(0)
> #define INTF_CFG2_DATA_HCTL_EN BIT(4)
> +#define INTF_CFG2_DCE_DATA_COMPRESS BIT(12)
>
>
> static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
> @@ -512,6 +513,15 @@ static void dpu_hw_intf_disable_autorefresh(struct
> dpu_hw_intf *intf,
>
> }
>
> +static void dpu_hw_intf_enable_compression(struct dpu_hw_intf *ctx)
> +{
> + u32 intf_cfg2 = DPU_REG_READ(>hw, INTF_CONFIG2);
> +
> + intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS;
> +
> + DPU_REG_WRITE(>hw, INTF_CONFIG2, intf_cfg2);
> +}
> +
> static void _setup_intf_ops(struct dpu_hw_intf_ops *ops,
> unsigned long cap)
> {
> @@ -532,6 +542,9 @@ static void _setup_intf_ops(struct dpu_hw_intf_ops *ops,
> ops->vsync_sel = dpu_hw_intf_vsync_sel;
> ops->disable_autorefresh = dpu_hw_intf_disable_autorefresh;
> }
> +
> + if (cap & BIT(DPU_INTF_DATA_COMPRESS))
> + ops->enable_compression = dpu_hw_intf_enable_compression;
> }
>
> struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
> index 33895eca1211..99e21c4137f9 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
> @@ -70,6 +70,7 @@ struct intf_status {
> * @get_autorefresh:Retrieve autorefresh config from hardware
> * Return: 0 on success, -ETIMEDOUT on timeout
> * @vsync_sel: Select vsync signal for tear-effect
> configuration
> + * @enable_compression: Enable data compression
> */
> struct dpu_hw_intf_ops {
> void (*setup_timing_gen)(struct dpu_hw_intf *intf,
> @@ -106,6 +107,8 @@ struct dpu_hw_intf_ops {
>* Disable autorefresh if enabled
>*/
> void (*disable_autorefresh)(struct dpu_hw_intf *intf, uint32_t
> encoder_id, u16 vdisplay);
> +
> + void (*enable_compression)(struct dpu_hw_intf *intf);
> };
>
> struct dpu_hw_intf {
>
> --
> 2.40.1
>
Re: [Freedreno] [PATCH] drm/msm/dpu: Configure DP INTF/PHY selector
On Tue, Jun 13, 2023 at 01:31:40AM +0300, Dmitry Baryshkov wrote:
> On 13/06/2023 01:10, Bjorn Andersson wrote:
> > From: Bjorn Andersson
> >
> > Some platforms provides a mechanism for configuring the mapping between
> > (one or two) DisplayPort intfs and their PHYs.
> >
> > In particular SC8180X provides this functionality, without a default
> > configuration, resulting in no connection between its two external
> > DisplayPort controllers and any PHYs.
> >
> > The change implements the logic for optionally configuring which phy
> > each of the intfs should be connected to, provides a new entry in the
> > DPU catalog for specifying how many intfs to configure and marks the
> > SC8180X DPU to program 2 entries.
> >
> > For now the request is simply to program the mapping 1:1, any support
> > for alternative mappings is left until the use case arrise.
> >
> > Note that e.g. msm-4.14 unconditionally maps intf 0 to phy 0 on all
> > rlatforms, so perhaps this is needed in order to get DisplayPort working
> > on some other platforms as well.
> >
> > Signed-off-by: Bjorn Andersson
> > Signed-off-by: Bjorn Andersson
> > ---
> > .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 1 +
> > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 2 ++
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c| 23 +++
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h| 8 +++
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h | 1 +
> > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 10
> > 6 files changed, 45 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> > b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> > index 8ed2b263c5ea..9da952692a69 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> > @@ -19,6 +19,7 @@ static const struct dpu_caps sc8180x_dpu_caps = {
> > .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> > .max_hdeci_exp = MAX_HORZ_DECIMATION,
> > .max_vdeci_exp = MAX_VERT_DECIMATION,
> > + .num_dp_intf_sel = 2,
> > };
> > static const struct dpu_ubwc_cfg sc8180x_ubwc_cfg = {
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > index ac4a9e73705c..4cb8d096d8ec 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > @@ -357,6 +357,7 @@ struct dpu_rotation_cfg {
> >* @pixel_ram_size size of latency hiding and de-tiling buffer in
> > bytes
> >* @max_hdeci_exp max horizontal decimation supported (max is
> > 2^value)
> >* @max_vdeci_exp max vertical decimation supported (max is 2^value)
> > + * @num_dp_intf_selnumber of DP intfs to configure PHY selection for
> >*/
> > struct dpu_caps {
> > u32 max_mixer_width;
> > @@ -371,6 +372,7 @@ struct dpu_caps {
> > u32 pixel_ram_size;
> > u32 max_hdeci_exp;
> > u32 max_vdeci_exp;
> > + u32 num_dp_intf_sel;
> > };
> > /**
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
> > index 963bdb5e0252..5afa99cb148c 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
> > @@ -250,6 +250,27 @@ static void dpu_hw_intf_audio_select(struct dpu_hw_mdp
> > *mdp)
> > DPU_REG_WRITE(c, HDMI_DP_CORE_SELECT, 0x1);
> > }
> > +static void dpu_hw_dp_phy_intf_sel(struct dpu_hw_mdp *mdp, unsigned int
> > *phys,
> > + unsigned int num_intfs)
> > +{
> > + struct dpu_hw_blk_reg_map *c = >hw;
> > + unsigned int intf;
> > + u32 sel = 0;
> > +
> > + if (!num_intfs)
> > + return;
> > +
> > + for (intf = 0; intf < num_intfs; intf++) {
> > + /* Specify the PHY (1-indexed) for @intf */
> > + sel |= (phys[intf] + 1) << (intf * 3);
> > +
> > + /* Specify the @intf (1-indexed) of targeted PHY */
> > + sel |= (intf + 1) << (6 + phys[intf] * 3);
>
> From what I can see, phys[intf] is const. What about defining indexed masks
> instead?
>
intf is the loop variable. What am I missing?
> > + }
> > +
> > + DPU_REG_WRITE(c, DP_PHY_INTF_SEL, sel);
> > +}
> > +
> > static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops,
> > unsigned long cap)
> > {
> > @@ -264,6 +285,8 @@ static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops,
> > ops->get_safe_status = dpu_hw_get_safe_status;
> > + ops->dp_phy_intf_sel = dpu_hw_dp_phy_intf_sel;
>
> Should this be gated for DPU < 4.0? Or 5.0?
>
> > +
> > if (cap & BIT(DPU_MDP_AUDIO_SELECT))
> > ops->intf_audio_select = dpu_hw_intf_audio_select;
> > }
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
> > index a1a9e44bed36..8446d74d59b0 100644
> > ---
Re: [Freedreno] [PATCH 2/2] drm: Remove struct drm_driver.gem_prime_mmap
On Tue, Jun 13, 2023 at 11:05 AM Thomas Zimmermann wrote:
>
> All drivers initialize this field with drm_gem_prime_mmap(). Call
> the function directly and remove the field. Simplifies the code and
> resolves a long-standing TODO item.
>
> Signed-off-by: Thomas Zimmermann
Series is:
Reviewed-by: Alex Deucher
> ---
> Documentation/gpu/todo.rst | 9 -
> drivers/accel/ivpu/ivpu_drv.c | 1 -
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 -
> drivers/gpu/drm/drm_fbdev_dma.c | 6 +-
> drivers/gpu/drm/drm_prime.c | 14 ++
> drivers/gpu/drm/etnaviv/etnaviv_drv.c | 1 -
> drivers/gpu/drm/exynos/exynos_drm_drv.c | 1 -
> drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c | 1 -
> drivers/gpu/drm/lima/lima_drv.c | 1 -
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 -
> drivers/gpu/drm/msm/msm_drv.c | 1 -
> drivers/gpu/drm/msm/msm_drv.h | 1 -
> drivers/gpu/drm/msm/msm_gem_prime.c | 5 -
> drivers/gpu/drm/nouveau/nouveau_drm.c | 1 -
> drivers/gpu/drm/panfrost/panfrost_drv.c | 1 -
> drivers/gpu/drm/pl111/pl111_drv.c | 1 -
> drivers/gpu/drm/radeon/radeon_drv.c | 1 -
> drivers/gpu/drm/renesas/rcar-du/rcar_du_drv.c | 1 -
> drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 1 -
> drivers/gpu/drm/v3d/v3d_drv.c | 1 -
> drivers/gpu/drm/virtio/virtgpu_drv.c| 1 -
> drivers/gpu/drm/xen/xen_drm_front.c | 1 -
> include/drm/drm_drv.h | 14 --
> include/drm/drm_gem_dma_helper.h| 6 ++
> include/drm/drm_gem_shmem_helper.h | 1 -
> include/drm/drm_gem_vram_helper.h | 1 -
> 26 files changed, 5 insertions(+), 69 deletions(-)
>
> diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst
> index 68bdafa0284f5..ca1efad8c89c3 100644
> --- a/Documentation/gpu/todo.rst
> +++ b/Documentation/gpu/todo.rst
> @@ -319,15 +319,6 @@ Contact: Daniel Vetter, Noralf Tronnes
>
> Level: Advanced
>
> -struct drm_gem_object_funcs
>
> -
> -GEM objects can now have a function table instead of having the callbacks on
> the
> -DRM driver struct. This is now the preferred way. Callbacks in drivers have
> been
> -converted, except for struct drm_driver.gem_prime_mmap.
> -
> -Level: Intermediate
> -
> connector register/unregister fixes
> ---
>
> diff --git a/drivers/accel/ivpu/ivpu_drv.c b/drivers/accel/ivpu/ivpu_drv.c
> index 2df7643b843d5..9f2b9fdcc5498 100644
> --- a/drivers/accel/ivpu/ivpu_drv.c
> +++ b/drivers/accel/ivpu/ivpu_drv.c
> @@ -376,7 +376,6 @@ static const struct drm_driver driver = {
> .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
> .gem_prime_import = ivpu_gem_prime_import,
> - .gem_prime_mmap = drm_gem_prime_mmap,
>
> .ioctls = ivpu_drm_ioctls,
> .num_ioctls = ARRAY_SIZE(ivpu_drm_ioctls),
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index c9a41c997c6c7..7681f79f462eb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -2809,7 +2809,6 @@ static const struct drm_driver amdgpu_kms_driver = {
> .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
> .gem_prime_import = amdgpu_gem_prime_import,
> - .gem_prime_mmap = drm_gem_prime_mmap,
>
> .name = DRIVER_NAME,
> .desc = DRIVER_DESC,
> diff --git a/drivers/gpu/drm/drm_fbdev_dma.c b/drivers/gpu/drm/drm_fbdev_dma.c
> index d86773fa8ab00..8217f1ddc0075 100644
> --- a/drivers/gpu/drm/drm_fbdev_dma.c
> +++ b/drivers/gpu/drm/drm_fbdev_dma.c
> @@ -54,12 +54,8 @@ static void drm_fbdev_dma_fb_destroy(struct fb_info *info)
> static int drm_fbdev_dma_fb_mmap(struct fb_info *info, struct vm_area_struct
> *vma)
> {
> struct drm_fb_helper *fb_helper = info->par;
> - struct drm_device *dev = fb_helper->dev;
> -
> - if (drm_WARN_ON_ONCE(dev, !fb_helper->dev->driver->gem_prime_mmap))
> - return -ENODEV;
>
> - return fb_helper->dev->driver->gem_prime_mmap(fb_helper->buffer->gem,
> vma);
> + return drm_gem_prime_mmap(fb_helper->buffer->gem, vma);
> }
>
> static const struct fb_ops drm_fbdev_dma_fb_ops = {
> diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c
> index d29dafce9bb0a..6bcf324ef81c9 100644
> --- a/drivers/gpu/drm/drm_prime.c
> +++ b/drivers/gpu/drm/drm_prime.c
> @@ -715,8 +715,6 @@ EXPORT_SYMBOL(drm_gem_dmabuf_vunmap);
> * the same codepath that is used for regular GEM buffer mapping on the DRM
> fd.
> * The fake GEM offset is added to vma->vm_pgoff
[Freedreno] [PATCH 2/2] drm: Remove struct drm_driver.gem_prime_mmap
All drivers initialize this field with drm_gem_prime_mmap(). Call
the function directly and remove the field. Simplifies the code and
resolves a long-standing TODO item.
Signed-off-by: Thomas Zimmermann
---
Documentation/gpu/todo.rst | 9 -
drivers/accel/ivpu/ivpu_drv.c | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 -
drivers/gpu/drm/drm_fbdev_dma.c | 6 +-
drivers/gpu/drm/drm_prime.c | 14 ++
drivers/gpu/drm/etnaviv/etnaviv_drv.c | 1 -
drivers/gpu/drm/exynos/exynos_drm_drv.c | 1 -
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c | 1 -
drivers/gpu/drm/lima/lima_drv.c | 1 -
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 -
drivers/gpu/drm/msm/msm_drv.c | 1 -
drivers/gpu/drm/msm/msm_drv.h | 1 -
drivers/gpu/drm/msm/msm_gem_prime.c | 5 -
drivers/gpu/drm/nouveau/nouveau_drm.c | 1 -
drivers/gpu/drm/panfrost/panfrost_drv.c | 1 -
drivers/gpu/drm/pl111/pl111_drv.c | 1 -
drivers/gpu/drm/radeon/radeon_drv.c | 1 -
drivers/gpu/drm/renesas/rcar-du/rcar_du_drv.c | 1 -
drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 1 -
drivers/gpu/drm/v3d/v3d_drv.c | 1 -
drivers/gpu/drm/virtio/virtgpu_drv.c| 1 -
drivers/gpu/drm/xen/xen_drm_front.c | 1 -
include/drm/drm_drv.h | 14 --
include/drm/drm_gem_dma_helper.h| 6 ++
include/drm/drm_gem_shmem_helper.h | 1 -
include/drm/drm_gem_vram_helper.h | 1 -
26 files changed, 5 insertions(+), 69 deletions(-)
diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst
index 68bdafa0284f5..ca1efad8c89c3 100644
--- a/Documentation/gpu/todo.rst
+++ b/Documentation/gpu/todo.rst
@@ -319,15 +319,6 @@ Contact: Daniel Vetter, Noralf Tronnes
Level: Advanced
-struct drm_gem_object_funcs
-
-GEM objects can now have a function table instead of having the callbacks on
the
-DRM driver struct. This is now the preferred way. Callbacks in drivers have
been
-converted, except for struct drm_driver.gem_prime_mmap.
-
-Level: Intermediate
-
connector register/unregister fixes
---
diff --git a/drivers/accel/ivpu/ivpu_drv.c b/drivers/accel/ivpu/ivpu_drv.c
index 2df7643b843d5..9f2b9fdcc5498 100644
--- a/drivers/accel/ivpu/ivpu_drv.c
+++ b/drivers/accel/ivpu/ivpu_drv.c
@@ -376,7 +376,6 @@ static const struct drm_driver driver = {
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
.gem_prime_import = ivpu_gem_prime_import,
- .gem_prime_mmap = drm_gem_prime_mmap,
.ioctls = ivpu_drm_ioctls,
.num_ioctls = ARRAY_SIZE(ivpu_drm_ioctls),
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index c9a41c997c6c7..7681f79f462eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -2809,7 +2809,6 @@ static const struct drm_driver amdgpu_kms_driver = {
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
.gem_prime_import = amdgpu_gem_prime_import,
- .gem_prime_mmap = drm_gem_prime_mmap,
.name = DRIVER_NAME,
.desc = DRIVER_DESC,
diff --git a/drivers/gpu/drm/drm_fbdev_dma.c b/drivers/gpu/drm/drm_fbdev_dma.c
index d86773fa8ab00..8217f1ddc0075 100644
--- a/drivers/gpu/drm/drm_fbdev_dma.c
+++ b/drivers/gpu/drm/drm_fbdev_dma.c
@@ -54,12 +54,8 @@ static void drm_fbdev_dma_fb_destroy(struct fb_info *info)
static int drm_fbdev_dma_fb_mmap(struct fb_info *info, struct vm_area_struct
*vma)
{
struct drm_fb_helper *fb_helper = info->par;
- struct drm_device *dev = fb_helper->dev;
-
- if (drm_WARN_ON_ONCE(dev, !fb_helper->dev->driver->gem_prime_mmap))
- return -ENODEV;
- return fb_helper->dev->driver->gem_prime_mmap(fb_helper->buffer->gem,
vma);
+ return drm_gem_prime_mmap(fb_helper->buffer->gem, vma);
}
static const struct fb_ops drm_fbdev_dma_fb_ops = {
diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c
index d29dafce9bb0a..6bcf324ef81c9 100644
--- a/drivers/gpu/drm/drm_prime.c
+++ b/drivers/gpu/drm/drm_prime.c
@@ -715,8 +715,6 @@ EXPORT_SYMBOL(drm_gem_dmabuf_vunmap);
* the same codepath that is used for regular GEM buffer mapping on the DRM fd.
* The fake GEM offset is added to vma->vm_pgoff and _driver->fops->mmap is
* called to set up the mapping.
- *
- * Drivers can use this as their _driver.gem_prime_mmap callback.
*/
int drm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma)
{
@@ -772,25 +770,17 @@ EXPORT_SYMBOL(drm_gem_prime_mmap);
* @vma: virtual address
[Freedreno] [PATCH 1/2] drm/msm: Initialize mmap offset after constructing the buffer object
Only the msm driver provides its own implementation of gem_prime_mmap
from struct drm_driver. All other drivers use the drm_gem_prime_mmap()
helper.
Initialize the mmap offset when constructing the buffer object in msm
and reduce the gem_prime_mmap code to the generic helper. Prepares
msm for the removal of struct drm_driver.gem_prime_mmap.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/msm/msm_gem.c | 8
drivers/gpu/drm/msm/msm_gem_prime.c | 10 --
2 files changed, 8 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
index 20cfd86d2b324..635744bc4765f 100644
--- a/drivers/gpu/drm/msm/msm_gem.c
+++ b/drivers/gpu/drm/msm/msm_gem.c
@@ -1234,6 +1234,10 @@ struct drm_gem_object *msm_gem_new(struct drm_device
*dev, uint32_t size, uint32
list_add_tail(_obj->node, >objects);
mutex_unlock(>obj_lock);
+ ret = drm_gem_create_mmap_offset(obj);
+ if (ret)
+ goto fail;
+
return obj;
fail:
@@ -1290,6 +1294,10 @@ struct drm_gem_object *msm_gem_import(struct drm_device
*dev,
list_add_tail(_obj->node, >objects);
mutex_unlock(>obj_lock);
+ ret = drm_gem_create_mmap_offset(obj);
+ if (ret)
+ goto fail;
+
return obj;
fail:
diff --git a/drivers/gpu/drm/msm/msm_gem_prime.c
b/drivers/gpu/drm/msm/msm_gem_prime.c
index c1d91863df055..2c846afe049e4 100644
--- a/drivers/gpu/drm/msm/msm_gem_prime.c
+++ b/drivers/gpu/drm/msm/msm_gem_prime.c
@@ -13,16 +13,6 @@
int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma)
{
- int ret;
-
- /* Ensure the mmap offset is initialized. We lazily initialize it,
-* so if it has not been first mmap'd directly as a GEM object, the
-* mmap offset will not be already initialized.
-*/
- ret = drm_gem_create_mmap_offset(obj);
- if (ret)
- return ret;
-
return drm_gem_prime_mmap(obj, vma);
}
--
2.41.0
[Freedreno] [PATCH 0/2] drm: Remove gem_prime_mmap callback
Remove the gem_prime_mmap callback from struct drm_driver. Rework msm, which has its own implementation. Then remove the callback and call drm_gem_prime_mmap() directly. This closes a long-standing item on the TODO list. The change removes the last GEM callback from the driver structure. GEM memory managers should implement the callbacks in struct dma_buf_ops and struct drm_gem_object_funcs to adapt the DRM to their needs. Thomas Zimmermann (2): drm/msm: Initialize mmap offset after constructing the buffer object drm: Remove struct drm_driver.gem_prime_mmap Documentation/gpu/todo.rst | 9 - drivers/accel/ivpu/ivpu_drv.c | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 - drivers/gpu/drm/drm_fbdev_dma.c | 6 +- drivers/gpu/drm/drm_prime.c | 14 ++ drivers/gpu/drm/etnaviv/etnaviv_drv.c | 1 - drivers/gpu/drm/exynos/exynos_drm_drv.c | 1 - drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c | 1 - drivers/gpu/drm/lima/lima_drv.c | 1 - drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 - drivers/gpu/drm/msm/msm_drv.c | 1 - drivers/gpu/drm/msm/msm_drv.h | 1 - drivers/gpu/drm/msm/msm_gem.c | 8 drivers/gpu/drm/msm/msm_gem_prime.c | 15 --- drivers/gpu/drm/nouveau/nouveau_drm.c | 1 - drivers/gpu/drm/panfrost/panfrost_drv.c | 1 - drivers/gpu/drm/pl111/pl111_drv.c | 1 - drivers/gpu/drm/radeon/radeon_drv.c | 1 - drivers/gpu/drm/renesas/rcar-du/rcar_du_drv.c | 1 - drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 1 - drivers/gpu/drm/v3d/v3d_drv.c | 1 - drivers/gpu/drm/virtio/virtgpu_drv.c| 1 - drivers/gpu/drm/xen/xen_drm_front.c | 1 - include/drm/drm_drv.h | 14 -- include/drm/drm_gem_dma_helper.h| 6 ++ include/drm/drm_gem_shmem_helper.h | 1 - include/drm/drm_gem_vram_helper.h | 1 - 27 files changed, 13 insertions(+), 79 deletions(-) base-commit: 63a468ec7c7652afa80e3fa6ad203f9e64d04e83 -- 2.41.0
[Freedreno] [PATCH v4 2/2] arm64: dts: qcom: sm8550: add display port nodes
Add the Display Port controller subnode to the MDSS node.
Reviewed-by: Konrad Dybcio
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 89 +++-
1 file changed, 87 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi
b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 972df1ef86ee..b41b3981b3ce 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -2495,6 +2495,13 @@ dpu_intf2_out: endpoint {
remote-endpoint =
<_dsi1_in>;
};
};
+
+ port@2 {
+ reg = <2>;
+ dpu_intf0_out: endpoint {
+ remote-endpoint =
<_dp0_in>;
+ };
+ };
};
mdp_opp_table: opp-table {
@@ -2522,6 +2529,84 @@ opp-51400 {
};
};
+ mdss_dp0: displayport-controller@ae9 {
+ compatible = "qcom,sm8550-dp", "qcom,sm8350-dp";
+ reg = <0 0xae9 0 0x200>,
+ <0 0xae90200 0 0x200>,
+ <0 0xae90400 0 0xc00>,
+ <0 0xae91000 0 0x400>,
+ <0 0xae91400 0 0x400>;
+ interrupt-parent = <>;
+ interrupts = <12>;
+ clocks = < DISP_CC_MDSS_AHB_CLK>,
+< DISP_CC_MDSS_DPTX0_AUX_CLK>,
+< DISP_CC_MDSS_DPTX0_LINK_CLK>,
+<
DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
+<
DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel";
+
+ assigned-clocks = <
DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
+ <
DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+ assigned-clock-parents = <_dp_qmpphy
QMP_USB43DP_DP_LINK_CLK>,
+<_dp_qmpphy
QMP_USB43DP_DP_VCO_DIV_CLK>;
+
+ phys = <_dp_qmpphy QMP_USB43DP_DP_PHY>;
+ phy-names = "dp";
+
+ #sound-dai-cells = <0>;
+
+ operating-points-v2 = <_opp_table>;
+ power-domains = < SM8550_MMCX>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss_dp0_in: endpoint {
+ remote-endpoint =
<_intf0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ mdss_dp0_out: endpoint {
+ };
+ };
+ };
+
+ dp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-16200 {
+ opp-hz = /bits/ 64 <16200>;
+ required-opps =
<_opp_low_svs_d1>;
+ };
+
+ opp-27000 {
+ opp-hz = /bits/ 64 <27000>;
+ required-opps =
<_opp_low_svs>;
+ };
+
+ opp-54000 {
+ opp-hz = /bits/ 64 <54000>;
+ required-opps =
<_opp_svs_l1>;
+ };
[Freedreno] [PATCH v4 1/2] arm64: dts: qcom: sm8550: fix low_svs RPMhPD labels
"low" was written "lov", fix this.
Fixes: 99d33ee61cb0 ("arm64: dts: qcom: sm8550: Add missing RPMhPD OPP levels")
Reviewed-by: Konrad Dybcio
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi
b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 75cd374943eb..972df1ef86ee 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -3649,15 +3649,15 @@ rpmhpd_opp_min_svs: opp-48 {
opp-level =
;
};
- rpmhpd_opp_lov_svs_d2: opp-52 {
+ rpmhpd_opp_low_svs_d2: opp-52 {
opp-level =
;
};
- rpmhpd_opp_lov_svs_d1: opp-56 {
+ rpmhpd_opp_low_svs_d1: opp-56 {
opp-level =
;
};
- rpmhpd_opp_lov_svs_d0: opp-60 {
+ rpmhpd_opp_low_svs_d0: opp-60 {
opp-level =
;
};
--
2.34.1
[Freedreno] [PATCH v4 0/2] arm64: dts: qcom: add DP Controller to SM8550 DTS
The DP output is shared with the USB3 SuperSpeed lanes and is usually connected to an USB-C port which Altmode is controlled by the PMIC Glink infrastructure. DT changes tying the DP controller to the USB-C port on the QRD board will be sent later. Signed-off-by: Neil Armstrong --- Changes in v4: - Added review tags from v2 - Link to v3: https://lore.kernel.org/r/20230601-topic-sm8550-upstream-dp-v3-0-5f9ffdcb8...@linaro.org Changes in v3: - Rebased on next-20230609 - Dropped applied bindings - Link to v2: https://lore.kernel.org/r/20230601-topic-sm8550-upstream-dp-v2-0-e8778109c...@linaro.org Changes in v2: - Added review tags - s/lov_svs/low_svs/ - Applied fixes suggested from Konrad - Link to v1: https://lore.kernel.org/r/20230601-topic-sm8550-upstream-dp-v1-0-29efe2689...@linaro.org --- Neil Armstrong (2): arm64: dts: qcom: sm8550: fix low_svs RPMhPD labels arm64: dts: qcom: sm8550: add display port nodes arch/arm64/boot/dts/qcom/sm8550.dtsi | 95 ++-- 1 file changed, 90 insertions(+), 5 deletions(-) --- base-commit: 53ab6975c12d1ad86c599a8927e8c698b144d669 change-id: 20230601-topic-sm8550-upstream-dp-b713ba275d7c Best regards, -- Neil Armstrong
Re: [Freedreno] [PATCH v3 1/2] arm64: dts: qcom: sm8550: fix low_svs RPMhPD labels
On 12/06/2023 18:50, Konrad Dybcio wrote:
On 12.06.2023 17:26, Neil Armstrong wrote:
"low" was written "lov", fix this.
Fixes: 99d33ee61cb0 ("arm64: dts: qcom: sm8550: Add missing RPMhPD OPP levels")
Signed-off-by: Neil Armstrong
---
https://lore.kernel.org/linux-arm-msm/1d3c05f5-c1bd-6844-1788-8df0b863a...@linaro.org/
somebody forgot to run `b4 trailers -u` :P
Damn, resending a v4 now :-)
Thanks,
Neil
Konrad
arch/arm64/boot/dts/qcom/sm8550.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi
b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 75cd374943eb..972df1ef86ee 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -3649,15 +3649,15 @@ rpmhpd_opp_min_svs: opp-48 {
opp-level =
;
};
- rpmhpd_opp_lov_svs_d2: opp-52 {
+ rpmhpd_opp_low_svs_d2: opp-52 {
opp-level =
;
};
- rpmhpd_opp_lov_svs_d1: opp-56 {
+ rpmhpd_opp_low_svs_d1: opp-56 {
opp-level =
;
};
- rpmhpd_opp_lov_svs_d0: opp-60 {
+ rpmhpd_opp_low_svs_d0: opp-60 {
opp-level =
;
};
