Hi,
On Mon, Jun 12, 2023 at 11:25 AM Dmitry Baryshkov
wrote:
>
> Change adreno_is_a690() prototype to accept the const struct adreno_gpu
> pointer instead of a non-const one. This fixes the following warning:
>
> In file included from drivers/gpu/drm/msm/msm_drv.c:33:
>
On Mon, Jun 12, 2023 at 11:25 AM Dmitry Baryshkov
wrote:
>
> Change adreno_is_a690() prototype to accept the const struct adreno_gpu
> pointer instead of a non-const one. This fixes the following warning:
>
> In file included from drivers/gpu/drm/msm/msm_drv.c:33:
>
On 2023-06-15 01:44:02, Dmitry Baryshkov wrote:
> It makes no sense to pass NULL parameters to dsi_ctrl_config() in the
> disable case. Split dsi_ctrl_config() into enable and disable parts and
> drop unused params.
>
> Signed-off-by: Dmitry Baryshkov
Indeed, it makes much more sense to split
On 2023-06-15 01:44:01, Dmitry Baryshkov wrote:
> Several source clocks are not used anymore, so stop handling them.
>
> Signed-off-by: Dmitry Baryshkov
Indeed, we were not using these parent clocks for anything.
Reviewed-by: Marijn Suijten
> ---
> drivers/gpu/drm/msm/dsi/dsi_host.c | 33
On 2023-06-14 14:23:38, Marijn Suijten wrote:
> Tested this on SM8350 which actually has DSI 2.5, and it is also
> corrupted with this series so something else on this series might be
> broken.
Never mind, this was a bad conflict-resolve. Jessica's original
BURST_MODE patch was RMW'ing
On 13/06/2023 02:37, Jessica Zhang wrote:
During a frame transfer in command mode, there could be frequent
LP11 <-> HS transitions when multiple DCS commands are sent mid-frame or
if the DSI controller is running on slow clock and is throttled. To
minimize frame latency due to these transitions,
It makes no sense to pass NULL parameters to dsi_ctrl_config() in the
disable case. Split dsi_ctrl_config() into enable and disable parts and
drop unused params.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 18 +-
1 file changed, 9 insertions(+), 9
Several source clocks are not used anymore, so stop handling them.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 33 --
1 file changed, 33 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
On Wed, Jun 14, 2023 at 09:03:34AM -0700, Bjorn Andersson wrote:
> On Mon, 22 May 2023 18:15:19 -0700, Bjorn Andersson wrote:
> > This series introduces support for A690 in the DRM/MSM driver and
> > enables it for the two SC8280XP laptops.
> >
> > Bjorn Andersson (3):
> > drm/msm/adreno: Add
On 2023-06-14 13:39:57, Abhinav Kumar wrote:
> On 6/14/2023 12:54 PM, Abhinav Kumar wrote:
> > On 6/14/2023 12:35 PM, Abhinav Kumar wrote:
> >> On 6/14/2023 5:23 AM, Marijn Suijten wrote:
> >>> On 2023-06-14 15:01:59, Dmitry Baryshkov wrote:
> On 14/06/2023 14:42, Marijn Suijten wrote:
>
On 14/06/2023 23:39, Abhinav Kumar wrote:
On 6/14/2023 12:54 PM, Abhinav Kumar wrote:
On 6/14/2023 12:35 PM, Abhinav Kumar wrote:
On 6/14/2023 5:23 AM, Marijn Suijten wrote:
On 2023-06-14 15:01:59, Dmitry Baryshkov wrote:
On 14/06/2023 14:42, Marijn Suijten wrote:
On 2023-06-13
On 6/14/2023 12:54 PM, Abhinav Kumar wrote:
On 6/14/2023 12:35 PM, Abhinav Kumar wrote:
On 6/14/2023 5:23 AM, Marijn Suijten wrote:
On 2023-06-14 15:01:59, Dmitry Baryshkov wrote:
On 14/06/2023 14:42, Marijn Suijten wrote:
On 2023-06-13 18:57:11, Jessica Zhang wrote:
DPU 5.x+ supports
On 6/13/2023 9:07 AM, Bjorn Andersson wrote:
On Tue, Jun 13, 2023 at 01:31:40AM +0300, Dmitry Baryshkov wrote:
On 13/06/2023 01:10, Bjorn Andersson wrote:
From: Bjorn Andersson
Some platforms provides a mechanism for configuring the mapping between
(one or two) DisplayPort intfs and their
On Mon, May 29, 2023 at 03:52:37PM +0200, Konrad Dybcio wrote:
>
> A610 is implemented on at least three SoCs: SM6115 (bengal), SM6125
> (trinket) and SM6225 (khaje). Trinket does not support speed binning
> (only a single SKU exists) and we don't yet support khaje upstream.
> Hence, add a fuse
On Mon, May 29, 2023 at 03:52:36PM +0200, Konrad Dybcio wrote:
>
> A619_holi is implemented on at least two SoCs: SM4350 (holi) and SM6375
> (blair). This is what seems to be a first occurrence of this happening,
> but it's easy to overcome by guarding the SoC-specific fuse values with
>
On 6/14/2023 12:35 PM, Abhinav Kumar wrote:
On 6/14/2023 5:23 AM, Marijn Suijten wrote:
On 2023-06-14 15:01:59, Dmitry Baryshkov wrote:
On 14/06/2023 14:42, Marijn Suijten wrote:
On 2023-06-13 18:57:11, Jessica Zhang wrote:
DPU 5.x+ supports a databus widen mode that allows more data to
On Mon, May 29, 2023 at 03:52:35PM +0200, Konrad Dybcio wrote:
>
> Before transitioning to using per-SoC and not per-Adreno speedbin
> fuse values (need another patchset to land elsewhere), a good
> improvement/stopgap solution is to use adreno_is_aXYZ macros in
> place of explicit revision
On Mon, May 29, 2023 at 03:52:34PM +0200, Konrad Dybcio wrote:
>
> The GPU can only be one at a time. Turn a series of ifs into if +
> elseifs to save some CPU cycles.
>
> Reviewed-by: Dmitry Baryshkov
> Signed-off-by: Konrad Dybcio
Reviewed-by: Akhil P Oommen
-Akhil
> ---
>
On Mon, May 29, 2023 at 03:52:33PM +0200, Konrad Dybcio wrote:
>
> Adreno 619 expects some tunables to be set differently. Make up for it.
>
> Fixes: b7616b5c69e6 ("drm/msm/adreno: Add A619 support")
> Reviewed-by: Dmitry Baryshkov
> Signed-off-by: Konrad Dybcio
> ---
>
On Mon, May 29, 2023 at 03:52:32PM +0200, Konrad Dybcio wrote:
>
> A610 is one of (if not the) lowest-tier SKUs in the A6XX family. It
> features no GMU, as it's implemented solely on SoCs with SMD_RPM.
> What's more interesting is that it does not feature a VDDGX line
> either, being powered
On 6/14/2023 5:23 AM, Marijn Suijten wrote:
On 2023-06-14 15:01:59, Dmitry Baryshkov wrote:
On 14/06/2023 14:42, Marijn Suijten wrote:
On 2023-06-13 18:57:11, Jessica Zhang wrote:
DPU 5.x+ supports a databus widen mode that allows more data to be sent
per pclk. Enable this feature flag on
On Tue, 7 Feb 2023 19:40:49 -0800, Bjorn Andersson wrote:
> This series introduces support for A690 in the DRM/MSM driver and
> enables it for the two SC8280XP laptops.
>
> Bjorn Andersson (3):
> drm/msm/adreno: Add Adreno A690 support
> arm64: dts: qcom: sc8280xp: Add GPU related nodes
>
On Wed, 14 Jun 2023 07:22:02 -0700, Bjorn Andersson wrote:
> With the A690 support merged in the drm/msm driver, this series adds the
> DeviceTree pieces to make it go on sc8280xp.
>
> Note that in order for the GPU driver to probe, the last change
> requires (which is now in linux-next):
>
On Mon, 22 May 2023 18:15:19 -0700, Bjorn Andersson wrote:
> This series introduces support for A690 in the DRM/MSM driver and
> enables it for the two SC8280XP laptops.
>
> Bjorn Andersson (3):
> drm/msm/adreno: Add Adreno A690 support
> arm64: dts: qcom: sc8280xp: Add GPU related nodes
>
On Wed, Jun 14, 2023 at 05:27:24PM +0200, Konrad Dybcio wrote:
> On 14.06.2023 16:22, Bjorn Andersson wrote:
> > From: Bjorn Andersson
> >
> > Add memory reservation for the zap-shader and enable the Adreno SMMU,
> > GPU clock controller, GMU and the GPU nodes for the SC8280XP CRD and the
> >
On 14.06.2023 16:22, Bjorn Andersson wrote:
> From: Bjorn Andersson
>
> Add memory reservation for the zap-shader and enable the Adreno SMMU,
> GPU clock controller, GMU and the GPU nodes for the SC8280XP CRD and the
> Lenovo ThinkPad X13s.
>
> Tested-by: Steev Klimaszewski
> Signed-off-by:
On 14.06.2023 16:22, Bjorn Andersson wrote:
> From: Bjorn Andersson
>
> Add Adreno SMMU, GPU clock controller, GMU and GPU nodes for the
> SC8280XP.
>
> Tested-by: Steev Klimaszewski
> Signed-off-by: Bjorn Andersson
> Tested-by: Johan Hovold
> Signed-off-by: Bjorn Andersson
> ---
From: Bjorn Andersson
Add memory reservation for the zap-shader and enable the Adreno SMMU,
GPU clock controller, GMU and the GPU nodes for the SC8280XP CRD and the
Lenovo ThinkPad X13s.
Tested-by: Steev Klimaszewski
Signed-off-by: Bjorn Andersson
Tested-by: Johan Hovold
Signed-off-by: Bjorn
From: Bjorn Andersson
Add Adreno SMMU, GPU clock controller, GMU and GPU nodes for the
SC8280XP.
Tested-by: Steev Klimaszewski
Signed-off-by: Bjorn Andersson
Tested-by: Johan Hovold
Signed-off-by: Bjorn Andersson
---
arch/arm64/boot/dts/qcom/sa8540p.dtsi | 8 ++
With the A690 support merged in the drm/msm driver, this series adds the
DeviceTree pieces to make it go on sc8280xp.
Note that in order for the GPU driver to probe, the last change
requires (which is now in linux-next):
On 2023-06-14 15:01:59, Dmitry Baryshkov wrote:
> On 14/06/2023 14:42, Marijn Suijten wrote:
> > On 2023-06-13 18:57:11, Jessica Zhang wrote:
> >> DPU 5.x+ supports a databus widen mode that allows more data to be sent
> >> per pclk. Enable this feature flag on all relevant chipsets.
> >>
> >>
On 14/06/2023 14:42, Marijn Suijten wrote:
On 2023-06-13 18:57:11, Jessica Zhang wrote:
DPU 5.x+ supports a databus widen mode that allows more data to be sent
per pclk. Enable this feature flag on all relevant chipsets.
Signed-off-by: Jessica Zhang
---
Hi
Am 14.06.23 um 13:29 schrieb Christian König:
Am 30.05.23 um 17:02 schrieb Thomas Zimmermann:
For framebuffers in I/O and system memory, add macros that set
struct fb_ops to the respective callback functions.
For deferred I/O, add macros that generate callback functions with
damage
On 2023-06-13 18:57:11, Jessica Zhang wrote:
> DPU 5.x+ supports a databus widen mode that allows more data to be sent
> per pclk. Enable this feature flag on all relevant chipsets.
>
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 ++-
>
Am 30.05.23 um 17:02 schrieb Thomas Zimmermann:
For framebuffers in I/O and system memory, add macros that set
struct fb_ops to the respective callback functions.
For deferred I/O, add macros that generate callback functions with
damage handling. Add initializer macros that set struct fb_ops
On 2023-06-14 12:39:13, Marijn Suijten wrote:
> > > > - /* add register dump support */
> > > > - dpu_debugfs_create_regset32("src_blk", 0400,
> > > > - debugfs_root,
> > > > - sblk->src_blk.base + cfg->base,
> > > > -
Hi
Am 14.06.23 um 10:26 schrieb Sui Jingfeng:
Hi,
On 2023/6/14 13:34, Thomas Zimmermann wrote:
Hi
Am 14.06.23 um 04:06 schrieb Sui Jingfeng:
On 2023/6/14 01:27, Sui Jingfeng wrote:
Wow, so many drivers get nuked!
On 2023/6/13 22:51, Thomas Zimmermann wrote:
All drivers initialize this
On 2023-05-21 21:16:39, Marijn Suijten wrote:
> On 2023-05-21 20:12:00, Marijn Suijten wrote:
> > On 2023-05-21 20:21:46, Dmitry Baryshkov wrote:
> > > Drop SSPP-specifig debugfs register dumps in favour of using
> > > debugfs/dri/0/kms or devcoredump.
> > >
> > > Signed-off-by: Dmitry Baryshkov
On 2023-06-13 18:57:10, Jessica Zhang wrote:
> DPU 5.x+ and DSI 6G 2.5.x+ support a databus-widen mode that allows for
> more compressed data to be transferred per pclk.
>
> This series adds support for enabling this feature for both DPU and DSI
> by doing the following:
>
> 1. Add a
On 2023-06-14 10:49:31, Dmitry Baryshkov wrote:
> On 14/06/2023 04:57, Jessica Zhang wrote:
> > DSI 6G v2.5.x+ supports a data-bus widen mode that allows DSI to send
> > 48 bits of compressed data per pclk instead of 24.
> >
> > For all chipsets that support this mode, enable it whenever DSC is
>
On 2023-06-13 18:57:13, Jessica Zhang wrote:
> DSI 6G v2.5.x+ supports a data-bus widen mode that allows DSI to send
> 48 bits of compressed data per pclk instead of 24.
>
> For all chipsets that support this mode, enable it whenever DSC is
> enabled as recommend by the hardware programming
On 2023-06-12 16:37:36, Jessica Zhang wrote:
> During a frame transfer in command mode, there could be frequent
> LP11 <-> HS transitions when multiple DCS commands are sent mid-frame or
> if the DSI controller is running on slow clock and is throttled. To
> minimize frame latency due to these
On 14/06/2023 04:57, Jessica Zhang wrote:
Add a DPU INTF op to set the DATABUS_WIDEN register to enable the
databus-widen mode datapath.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 3 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 12
On Mon, 12 Jun 2023 at 23:55, Dmitry Baryshkov
wrote:
>
> Add definitions of DSPP blocks present on the sdm845 platform. This
> should enable color-management on sdm845-bassed devices.
>
> Signed-off-by: Dmitry Baryshkov
> ---
> .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h| 21
On 14/06/2023 04:57, Jessica Zhang wrote:
DPU 5.x+ supports a databus widen mode that allows more data to be sent
per pclk. Enable this feature flag on all relevant chipsets.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 ++-
On Mon, 12 Jun 2023 at 23:55, Dmitry Baryshkov
wrote:
>
> We can not support color management without DSPP blocks being provided
> in the HW catalog. Do not enable color management for CRTCs if num_dspps
> is 0.
>
> Fixes: 4259ff7ae509 ("drm/msm/dpu: add support for pcc color block in dpu
>
On 14/06/2023 04:57, Jessica Zhang wrote:
DSI 6G v2.5.x+ supports a data-bus widen mode that allows DSI to send
48 bits of compressed data per pclk instead of 24.
For all chipsets that support this mode, enable it whenever DSC is
enabled as recommend by the hardware programming guide.
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