On 7/7/2023 4:12 PM, Dmitry Baryshkov wrote:
Drop the dpu_encoder_phys_ops' destroy() callback. No phys backend
implements it anymore, so it is useless.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 18
On 7/7/2023 4:12 PM, Dmitry Baryshkov wrote:
The field dpu_plane::lock was never used for protecting any kind of
data. Drop it now.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 6 --
1 file changed, 6 deletions(-)
On 7/7/2023 4:12 PM, Dmitry Baryshkov wrote:
Change struct allocation of encoder's phys backend data to use
drmm_kzalloc(). This removes the need to perform any actions on encoder
destruction.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
---
On 7/7/2023 4:12 PM, Dmitry Baryshkov wrote:
Change struct dpu_crtc allocation to use drmm_crtc_alloc_with_planes().
This removes the need to perform any actions on CRTC destruction.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
---
On 7/7/2023 4:12 PM, Dmitry Baryshkov wrote:
Change struct dpu_plane allocation to use drmm_universal_plane_alloc().
This removes the need to perform any actions on plane destruction.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Jessica Zhang
---
On 7/7/2023 4:12 PM, Dmitry Baryshkov wrote:
Use devm_kzalloc to create HW block structure. This allows us to remove
corresponding kfree and drop all dpu_hw_*_destroy() functions as well as
dpu_rm_destroy(), which becomes empty afterwards.
Signed-off-by: Dmitry Baryshkov
Reviewed-by:
On 28/07/2023 20:02, Jessica Zhang wrote:
Add solid_fill property data to the atomic plane state dump.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/drm_atomic.c | 4
drivers/gpu/drm/drm_plane.c | 10 ++
include/drm/drm_plane.h | 3 +++
3 files changed, 17
On 28/07/2023 20:02, Jessica Zhang wrote:
Add pixel source to the atomic plane state dump
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/drm_atomic.c| 1 +
drivers/gpu/drm/drm_crtc_internal.h | 2 ++
drivers/gpu/drm/drm_plane.c | 12
3 files changed, 15
On 27/07/2023 23:03, Marijn Suijten wrote:
On 2023-07-27 19:20:58, Dmitry Baryshkov wrote:
The DPU_PINGPONG_TE bit is set for all PINGPONG blocks on DPU < 5.0.
Rather than checking for the flag, check for the presense of the
corresponding interrupt line.
Signed-off-by: Dmitry Baryshkov
On 27/07/2023 23:05, Marijn Suijten wrote:
On 2023-07-27 19:20:58, Dmitry Baryshkov wrote:
The DPU_PINGPONG_TE bit is set for all PINGPONG blocks on DPU < 5.0.
Rather than checking for the flag, check for the presense of the
corresponding interrupt line.
Signed-off-by: Dmitry Baryshkov
---
On 27/07/2023 23:10, Marijn Suijten wrote:
On 2023-07-27 19:21:00, Dmitry Baryshkov wrote:
Inline the _setup_intf_ops() function, it makes it easier to handle
different conditions involving INTF configuration.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
---
In order to simplify IRQ declarations, shift IRQ indices by 1. This
makes 0 the 'no IRQ' value. Thanks to this change, we do no longer have
to explicitly set the 'no interrupt' fields in catalog structures.
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 4
In preparation to reworking the IRQ indices, move irq_idx validation to
the separate helper.
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 22 +--
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git
In preparation to reworking IRQ indcies, stop using raw indices in
kernel output (both printk and debugfs). Instead use a pair of register
index and bit. This corresponds closer to the values in HW catalog.
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 49
In preparation to reworking the IRQ indices, move irq_tbl access to
separate helper.
Reviewed-by: Marijn Suijten
Signed-off-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 48 +--
.../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 12 +++--
2 files
The size of the irq table is static, it has MDP_INTR_MAX * 32 interrupt
entries. Provide the fixed length and drop struct_size() statement.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 13 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
There is no point in passing the IRQ index to IRQ callbacks, no function
uses that. Drop it at last.
Reviewed-by: Marijn Suijten
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 ++--
Having an explicit init of interrupt fields to -1 for not existing IRQs
makes it easier to forget and/or miss such initialisation, resulting in
a wrong interrupt definition.
Instead shift all IRQ indices to turn '0' to be the non-existing IRQ.
Dependencies: [1]
[1]
On 29/07/2023 00:44, Jessica Zhang wrote:
On 7/28/2023 2:37 AM, Dmitry Baryshkov wrote:
On Fri, 28 Jul 2023 at 04:26, Paloma Arellano
wrote:
Enable display compression (DSC v1.2) and CMD mode for 1080x2400
Visionox
VTDR6130 AMOLED DSI panel. In addition, this patch will set the default
On 7/28/2023 2:39 PM, Dmitry Baryshkov wrote:
On 29/07/2023 00:36, Abhinav Kumar wrote:
On 7/28/2023 2:33 PM, Dmitry Baryshkov wrote:
Switch to using data from MDSS driver to program the SSPP fetch and UBWC
configuration. As a side-effect, this also swithes the DPU driver from
On 7/28/2023 2:37 AM, Dmitry Baryshkov wrote:
On Fri, 28 Jul 2023 at 04:26, Paloma Arellano wrote:
Enable display compression (DSC v1.2) and CMD mode for 1080x2400 Visionox
VTDR6130 AMOLED DSI panel. In addition, this patch will set the default
to command mode with DSC enabled.
Note: This
On 29/07/2023 00:36, Abhinav Kumar wrote:
On 7/28/2023 2:33 PM, Dmitry Baryshkov wrote:
Switch to using data from MDSS driver to program the SSPP fetch and UBWC
configuration. As a side-effect, this also swithes the DPU driver from
DPU_HW_UBWC_VER_xx values to the UBWC_x_y enum, which
On 7/28/2023 2:33 PM, Dmitry Baryshkov wrote:
Switch to using data from MDSS driver to program the SSPP fetch and UBWC
configuration. As a side-effect, this also swithes the DPU driver from
DPU_HW_UBWC_VER_xx values to the UBWC_x_y enum, which reflects
the hardware register values.
As the DPU driver has switched to fetching data from MDSS driver, we can
now drop the UBWC and highest_bank_bit parts of the DPU hw catalog.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 6 -
The feature bits DPU_MDP_BWC, DPU_MDP_UBWC_1_0, and DPU_MDP_UBWC_1_5 are
not used by the driver, drop them completely as a followup cleanup.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 7 ---
1 file changed, 7 deletions(-)
diff --git
As we are going to use MDSS data for DPU programming, populate missing
MDSS data. The UBWC 1.0 and no UBWC cases do not require MDSS
programming, so skip them.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 21 +++--
1 file changed, 19 insertions(+), 2
DPU programming requires knowledge of some of UBWC parameters. This
results in duplication of UBWC data between MDSS and DPU drivers. Export
the required data from MDSS driver.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 30
Switch to using data from MDSS driver to program the SSPP fetch and UBWC
configuration. As a side-effect, this also swithes the DPU driver from
DPU_HW_UBWC_VER_xx values to the UBWC_x_y enum, which reflects
the hardware register values.
Signed-off-by: Dmitry Baryshkov
---
Rename the ubwc_version field to ubwc_enc_version, it denotes the
version of the UBWC encoder, not the "UBWC version".
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 30 +++---
1 file changed, 15 insertions(+), 15
The SM8550 platform employs newer UBWC decoder, which requires slightly
different programming.
Fixes: a2f33995c19d ("drm/msm: mdss: add support for SM8550")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 19 +--
1 file changed, 17 insertions(+), 2
Both DPU and MDSS programming requires knowledge of some of UBWC
parameters. This results in duplication of UBWC data between MDSS and
DPU drivers. To remove such duplication and make the driver more
error-prone, export respective configuration from the MDSS driver and
make DPU use it, instead of
On 2023-07-09 23:25:11 +0300, Dmitry Baryshkov wrote:
> Implement the oob_hotplug_event() callback. Translate it to the HPD
> notification sent to the HPD bridge in the chain.
>
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Janne Grunau
> ---
> drivers/gpu/drm/drm_bridge_connector.c | 29
On Fri, 28 Jul 2023 at 22:25, Abhinav Kumar wrote:
>
>
>
> On 7/27/2023 8:26 AM, Dmitry Baryshkov wrote:
> > On 27/07/2023 18:24, Abhinav Kumar wrote:
> >>
> >>
> >> On 7/27/2023 1:39 AM, Dmitry Baryshkov wrote:
> >>> On Thu, 27 Jul 2023 at 02:20, Abhinav Kumar
> >>> wrote:
>
>
>
On 7/27/2023 8:26 AM, Dmitry Baryshkov wrote:
On 27/07/2023 18:24, Abhinav Kumar wrote:
On 7/27/2023 1:39 AM, Dmitry Baryshkov wrote:
On Thu, 27 Jul 2023 at 02:20, Abhinav Kumar
wrote:
On 5/21/2023 10:10 AM, Dmitry Baryshkov wrote:
Switch to using data from MDSS driver to program the
The of_find_device_by_node() takes a reference to the underlying device
structure, we should release that reference.
Detected by coccinelle with the following ERROR:
./drivers/gpu/drm/msm/dsi/dsi.c:50:1-7: ERROR: missing put_device; call
of_find_device_by_node on line 32, but without a
The of_find_device_by_node() takes a reference to the underlying device
structure, we should release that reference.
Detected by coccinelle with the following ERROR:
./drivers/gpu/drm/msm/dsi/dsi.c:50:1-7: ERROR: missing put_device; call
of_find_device_by_node on line 32, but without a
On 2023-07-09 23:25:10 +0300, Dmitry Baryshkov wrote:
> In some cases the bridge drivers would like to receive hotplug events
> even in the case new status is equal to the old status. In the DP case
> this is used to deliver "attention" messages to the DP host. Stop
> filtering the events in the
On Fri, 28 Jul 2023 at 20:03, Jessica Zhang wrote:
>
> Add support for pixel_source property to drm_plane and related
> documentation. In addition, force pixel_source to
> DRM_PLANE_PIXEL_SOURCE_FB in DRM_IOCTL_MODE_SETPLANE as to not break
> legacy userspace.
>
> This enum property will allow
Loosen the requirements for atomic and legacy commit so that, in cases
where pixel_source != FB, the commit can still go through.
This includes adding framebuffer NULL checks in other areas to account
for FB being NULL when non-FB pixel sources are enabled.
To disable a plane, the pixel_source
Currently framebuffer checks happen directly in
drm_atomic_plane_check(). Move these checks into their own helper
method.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/drm_atomic.c | 130 ---
1 file changed, 73 insertions(+), 57 deletions(-)
diff
Add pixel source to the atomic plane state dump
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/drm_atomic.c| 1 +
drivers/gpu/drm/drm_crtc_internal.h | 2 ++
drivers/gpu/drm/drm_plane.c | 12
3 files changed, 15 insertions(+)
diff --git
Document and add support for solid_fill property to drm_plane. In
addition, add support for setting and getting the values for solid_fill.
To enable solid fill planes, userspace must assign a property blob to
the "solid_fill" plane property containing the following information:
struct
Since solid fill planes allow for a NULL framebuffer in a valid commit,
add NULL framebuffer checks to atomic commit calls within DPU.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 9 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 41
Add solid_fill and pixel_source properties to DPU plane
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
Add solid_fill property data to the atomic plane state dump.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/drm_atomic.c | 4
drivers/gpu/drm/drm_plane.c | 10 ++
include/drm/drm_plane.h | 3 +++
3 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic.c
Drop DPU_PLANE_COLOR_FILL_FLAG and check the DRM solid_fill property to
determine if the plane is solid fill. In addition drop the DPU plane
color_fill field as we can now use drm_plane_state.solid_fill instead,
and pass in drm_plane_state.alpha to _dpu_plane_color_fill_pipe() to
allow userspace
Add support for pixel_source property to drm_plane and related
documentation. In addition, force pixel_source to
DRM_PLANE_PIXEL_SOURCE_FB in DRM_IOCTL_MODE_SETPLANE as to not break
legacy userspace.
This enum property will allow user to specify a pixel source for the
plane. Possible pixel
Some drivers support hardware that have optimizations for solid fill
planes. This series aims to expose these capabilities to userspace as
some compositors have a solid fill flag (ex. SOLID_COLOR in the Android
hardware composer HAL) that can be set by apps like the Android Gears
app.
In order to
Add "SOLID_FILL" as a valid pixel source. If the pixel_source property is
set to "SOLID_FILL", it will display data from the drm_plane "solid_fill"
blob property.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/drm_blend.c | 10 +-
include/drm/drm_plane.h | 1 +
2 files changed,
On Thu, Jul 27, 2023 at 3:12 PM Dmitry Baryshkov
wrote:
>
> On Fri, 28 Jul 2023 at 00:23, Rob Clark wrote:
> >
> > From: Rob Clark
> >
> > There are cases where there are differences due to SoC integration.
> > Such as cache-coherency support, and (in the next patch) e-fuse to
> > speedbin
On Fri, Jul 28, 2023 at 12:27 AM Krzysztof Kozlowski
wrote:
>
> On 27/07/2023 23:20, Rob Clark wrote:
> > From: Rob Clark
> >
> > Upcoming GPUs use an opaque chip-id for identifying the GPU.
>
> Examples?
We'll know when we bring up the hw. But the main point is that we
shouldn't expect, for
On Thu, 27 Jul 2023 at 22:58, Marijn Suijten
wrote:
>
> Title nit: How about making this "UP by 1"?
>
> On 2023-07-27 18:04:55, Dmitry Baryshkov wrote:
> > In order to simplify IRQ declarations, shift IRQ indices by 1. This
>
> Same here, UP by one.
>
> > makes 0 the 'no IRQ' value. Thanks to
On Fri, 28 Jul 2023 at 17:43, Rob Clark wrote:
>
> On Thu, Jul 27, 2023 at 3:02 PM Dmitry Baryshkov
> wrote:
> >
> > On Fri, 28 Jul 2023 at 00:13, Rob Clark wrote:
> > >
> > > On Wed, Jul 26, 2023 at 3:33 PM Dmitry Baryshkov
> > > wrote:
> > > >
> > > > On Thu, 27 Jul 2023 at 01:04, Rob Clark
On Thu, Jul 27, 2023 at 3:02 PM Dmitry Baryshkov
wrote:
>
> On Fri, 28 Jul 2023 at 00:13, Rob Clark wrote:
> >
> > On Wed, Jul 26, 2023 at 3:33 PM Dmitry Baryshkov
> > wrote:
> > >
> > > On Thu, 27 Jul 2023 at 01:04, Rob Clark wrote:
> > > >
> > > > On Wed, Jul 26, 2023 at 2:43 PM Dmitry
On Fri, 28 Jul 2023 at 04:26, Paloma Arellano wrote:
>
> Enable display compression (DSC v1.2) and CMD mode for 1080x2400 Visionox
> VTDR6130 AMOLED DSI panel. In addition, this patch will set the default
> to command mode with DSC enabled.
>
> Note: This patch has only been validated DSC over
On 27/07/2023 23:20, Rob Clark wrote:
> From: Rob Clark
>
> Upcoming GPUs use an opaque chip-id for identifying the GPU.
Examples?
Anyway, I think we should insist here of using something human-readable,
even if Qualcomm/Adreno internally use some weird numbers.
>
> Signed-off-by: Rob Clark
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