ile changed, 8 insertions(+), 8 deletions(-)
Assuming that someone has already validated OR will validate this,
Reviewed-by: Abhinav Kumar
perspective
it makes sense to tie them together.
Plus everyone introduces bugs. If you're not introducing bugs, then
you're probably not writing a lot of code.
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
LGTM,
Reviewed-by: Abhinav Kumar
On 10/31/2023 1:19 AM, Dmitry Baryshkov wrote:
On Mon, 30 Oct 2023 at 22:24, Abhinav Kumar wrote:
On 10/6/2023 6:14 AM, Dmitry Baryshkov wrote:
Three different features, DPU_SSPP_SCALER_QSEED3, QSEED3LITE and QSEED4
are all related to different versions of the same HW scaling block
On 10/31/2023 1:16 AM, Dmitry Baryshkov wrote:
On Mon, 30 Oct 2023 at 21:52, Abhinav Kumar wrote:
On 10/6/2023 6:14 AM, Dmitry Baryshkov wrote:
As we have dropped the variadic parts of SSPP sub-blocks declarations,
deduplicate them now, reducing memory cruft.
Signed-off-by: Dmitry
On 10/6/2023 6:14 AM, Dmitry Baryshkov wrote:
Three different features, DPU_SSPP_SCALER_QSEED3, QSEED3LITE and QSEED4
are all related to different versions of the same HW scaling block.
Corresponding driver parts use scaler_blk.version to identify the
correct way to program the hardware. In
in order to be able to drop those
two macros.
funcion ---> function
Suggested-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 15 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 ++--
2 files changed, 2 insertions(+),
On 10/6/2023 6:14 AM, Dmitry Baryshkov wrote:
As we have dropped the variadic parts of SSPP sub-blocks declarations,
deduplicate them now, reducing memory cruft.
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 16 +--
disconnect places preferably in
dp_display_send_hpd_notification().
That way, we would have had to make this change only in one location.
If you want to pursue that as a separate patch, I am fine as well.
Hence,
Reviewed-by: Abhinav Kumar
On 10/23/2023 4:03 PM, Dmitry Baryshkov wrote:
On Tue, 24 Oct 2023 at 01:36, Rob Clark wrote:
On Mon, Oct 23, 2023 at 3:30 PM Dmitry Baryshkov
wrote:
On Tue, 24 Oct 2023 at 01:12, Rob Clark wrote:
From: Rob Clark
Seems like we need to pick INPUT_SEL=1 when CTM is enabled. But not
that support,
Hence,
Reviewed-by: Abhinav Kumar
Overall, nice cleanup!
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 8 ---
drivers/gpu/drm/msm/dp/dp_debug.c | 69 ++---
drivers/gpu/drm/msm/dp/dp_debug.h | 23 +++--
drivers/gpu/drm/msm/dp/dp_display.c | 5
drm/msm/dp/dp_display.c:604)
hpd_event_thread (drivers/gpu/drm/msm/dp/dp_display.c:1110)
kthread (kernel/kthread.c:388)
ret_from_fork (arch/arm64/kernel/entry.S:858)
Fixes: bfcc3d8f94f4 ("drm/msm/dp: support setting the DP subconnector type")
Signed-off-by: Dmitry Baryshkov
---
Review
: Add a common function to free kernel buffer
objects")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
Reviewed-by: Abhinav Kumar
On 10/9/2023 1:53 PM, Dmitry Baryshkov wrote:
On 09/10/2023 22:21, Dmitry Baryshkov wrote:
On 09/10/2023 22:19, Abhinav Kumar wrote:
On 10/9/2023 11:10 AM, Dmitry Baryshkov wrote:
Make MSM HDMI driver use devm_drm_bridge_add() instead of plain
drm_bridge_add(). As the driver doesn't
---
drivers/gpu/drm/msm/msm_drv.c | 1 -
1 file changed, 1 deletion(-)
Reviewed-by: Abhinav Kumar
insertions(+), 6 deletions(-)
Reviewed-by: Abhinav Kumar
/msm/disp/mdp4/mdp4_kms.c | 4 ++--
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 4 ++--
drivers/gpu/drm/msm/msm_drv.c| 4 ++--
drivers/gpu/drm/msm/msm_drv.h| 4 ++--
5 files changed, 10 insertions(+), 10 deletions(-)
Reviewed-by: Abhinav Kumar
try Baryshkov
---
drivers/gpu/drm/msm/msm_drv.c | 6 --
1 file changed, 6 deletions(-)
Reviewed-by: Abhinav Kumar
On 10/9/2023 12:21 PM, Dmitry Baryshkov wrote:
On 09/10/2023 22:19, Abhinav Kumar wrote:
On 10/9/2023 11:10 AM, Dmitry Baryshkov wrote:
Make MSM HDMI driver use devm_drm_bridge_add() instead of plain
drm_bridge_add(). As the driver doesn't require any additional cleanup,
stop adding
On 10/9/2023 11:10 AM, Dmitry Baryshkov wrote:
Make MSM HDMI driver use devm_drm_bridge_add() instead of plain
drm_bridge_add(). As the driver doesn't require any additional cleanup,
stop adding created bridge to the priv->bridges array.
Reviewed-by: Rob Clark
Signed-off-by: Dmitry
On 10/9/2023 12:01 PM, Dmitry Baryshkov wrote:
On 09/10/2023 21:51, Abhinav Kumar wrote:
On 10/9/2023 11:46 AM, Dmitry Baryshkov wrote:
On 09/10/2023 21:39, Abhinav Kumar wrote:
On 10/9/2023 11:10 AM, Dmitry Baryshkov wrote:
Make MSM DSI driver use devm_drm_bridge_add() instead
On 10/9/2023 11:46 AM, Dmitry Baryshkov wrote:
On 09/10/2023 21:39, Abhinav Kumar wrote:
On 10/9/2023 11:10 AM, Dmitry Baryshkov wrote:
Make MSM DSI driver use devm_drm_bridge_add() instead of plain
drm_bridge_add(). As the driver doesn't require any additional cleanup,
stop adding
On 10/9/2023 11:10 AM, Dmitry Baryshkov wrote:
Make MSM DSI driver use devm_drm_bridge_add() instead of plain
drm_bridge_add(). As the driver doesn't require any additional cleanup,
stop adding created bridge to the priv->bridges array.
Reviewed-by: Rob Clark
Signed-off-by: Dmitry Baryshkov
On 10/2/2023 3:58 PM, Stephen Boyd wrote:
Quoting Abhinav Kumar (2023-09-28 17:46:11)
On 9/27/2023 3:01 PM, Stephen Boyd wrote:
Quoting Kuogee Hsieh (2023-09-25 09:07:18)
However for external DP case, link training can not be guarantee always
success without link rate or lane being
On 9/27/2023 3:01 PM, Stephen Boyd wrote:
Quoting Kuogee Hsieh (2023-09-25 09:07:18)
On 9/22/2023 6:35 PM, Abhinav Kumar wrote:
Doing link training when we get hpd instead of atomic_enable() is a
design choice we have been following for a while because for the case
when link training
On 9/27/2023 2:41 PM, Stephen Boyd wrote:
Quoting Abhinav Kumar (2023-09-22 18:35:27)
On 9/22/2023 2:54 PM, Stephen Boyd wrote:
Quoting Dmitry Baryshkov (2023-09-19 02:50:12)
This should be hpd_notify, who starts link training, not some event.
I think this driver should train the link
Hi Stephen
On 9/22/2023 2:54 PM, Stephen Boyd wrote:
Quoting Dmitry Baryshkov (2023-09-19 02:50:12)
On Mon, 18 Sept 2023 at 20:48, Kuogee Hsieh wrote:
On 9/15/2023 6:21 PM, Dmitry Baryshkov wrote:
On Sat, 16 Sept 2023 at 00:38, Kuogee Hsieh wrote:
Add pm_runtime_force_suspend()/resume()
On 9/20/2023 3:46 PM, Konrad Dybcio wrote:
Commit e550ad0e5c3d ("drm/msm/dpu: fix DSC 1.2 block lengths") changed
the block length from a wrong value to another wrong value.
Use the correct one this time.
No that change is correct as well.
After we moved to sub-blk parsing, we have enc
On 9/20/2023 3:46 PM, Konrad Dybcio wrote:
DPU_DSC_OUTPUT_CTRL should be enabled for all platforms with a CTL
CFG 1.0.0. SC7280 is one of them. Add it.
sc7280 and all other chipsets using DSC 1.2 use dpu_hw_dsc_init_1_2 and
not dpu_hw_dsc_init.
dpu_hw_dsc_init_1_2 assigns the
On 9/20/2023 3:46 PM, Konrad Dybcio wrote:
Commit 194347df5844 ("drm/msm/dpu: inline DSC_BLK and DSC_BLK_1_2
macros") unrolled a macro incorrectly. Fix that.
No, its correct from what i can tell.
Before inlining it was using PP_BLK_DITHER macro and not PP_BLK.
PP_BLK_DITHER has a len of
| 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Abhinav Kumar
of these calls to make sure these calls are
balanced is handled by the DRM core and we should keep it that way
to minimize the overhead in the drivers which implement these ops.
[1]: https://patchwork.freedesktop.org/patch/558387/
Signed-off-by: Abhinav Kumar
---
include/drm
Hi Laurent
On 9/19/2023 11:12 AM, Laurent Pinchart wrote:
Hi Abhinav,
Thank you for the patch.
On Tue, Sep 19, 2023 at 10:48:12AM -0700, Abhinav Kumar wrote:
drm_bridge_hpd_enable()/drm_bridge_hpd_disable() callbacks call into
the respective driver's hpd_enable()/hpd_disable() ops. These ops
() balance be maintained by the
corresponding drm_bridge_connector_enable_hpd() /
drm_bridge_connector_disable_hpd() APIs which should get called by
drm_kms_helper_disable_hpd().
changes in v2:
- minor change in commit text (Dmitry)
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
rm/msm/dsi/dsi_host.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
Reviewed-by: Abhinav Kumar
Will queue it up for -fixes
On 9/11/2023 2:45 PM, Dmitry Baryshkov wrote:
Three different features, DPU_SSPP_SCALER_QSEED3, QSEED3LITE and QSEED4
are all related to different versions of the same HW scaling block.
Corresponding driver parts use scaler_blk.version to identify the
correct way to program the hardware. In
(-)
Reviewed-by: Abhinav Kumar
On 9/11/2023 2:45 PM, Dmitry Baryshkov wrote:
As we have dropped the variadic parts of SSPP sub-blocks declarations,
deduplicate them now, reducing memory cruft.
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 16 +--
:
- move the reg read below the video mode check
- minor fixes in commit text
Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/34
Fixes: a689554ba6ed ("drm/msm: Initial add DSI connector support")
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dsi/dsi_h
: a689554ba6ed ("drm/msm: Initial add DSI connector support")
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 0c4ec0530efc..31
lock_valid() with hopes the
function can be removed altogether in the future.
(*) drm_get_edid() ignores checksum errors on CTA extensions.
Cc: Abhinav Kumar
Cc: Dmitry Baryshkov
Cc: Kuogee Hsieh
Cc: Marijn Suijten
Cc: Rob Clark
Cc: Sean Paul
Cc: Stephen Boyd
Cc: linux-arm-...@vger.kernel.org
Cc:
-by: Dmitry Baryshkov
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 112 +++---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 2 -
2 files changed, 40 insertions(+), 74 deletions(-)
Alright, if we need it later, we can add it to the SSPP itself
Reviewed-by: Abhinav Kumar
+--
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 2 -
2 files changed, 36 insertions(+), 42 deletions(-)
Reviewed-by: Abhinav Kumar
| 2 --
15 files changed, 16 deletions(-)
Reviewed-by: Abhinav Kumar
-by: Abhinav Kumar
the dpu_plane_atomic_check() if the SSPP cannot process the
image without exceeding the MDP clock limits.
changes in v2:
- use crtc_state's adjusted_mode instead of mode
Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support")
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_pl
- fix the UBWC condition to check maxlinewidth
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index
On 9/8/2023 4:30 PM, Dmitry Baryshkov wrote:
On Fri, 8 Sept 2023 at 21:55, Abhinav Kumar wrote:
It's certainly possible that for large resolutions a single DPU SSPP
cannot process the image without exceeding the MDP clock limits but
it can still process it in multirect mode because
On 9/8/2023 4:06 PM, Dmitry Baryshkov wrote:
On Fri, 8 Sept 2023 at 21:56, Abhinav Kumar wrote:
Currently, dpu_plane_atomic_check() does not check whether the
plane can process the image without exceeding the per chipset
limits for MDP clock. This leads to underflow issues because the
SSPP
To support high resolutions on sm8350, enable smartdma
in its catalog.
Signed-off-by: Abhinav Kumar
---
Notes:
only compile tested, to be landed after sufficient testing
.../drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 16
1 file changed, 8 insertions(+), 8 deletions
the dpu_plane_atomic_check() if the SSPP cannot process the
image without exceeding the MDP clock limits.
Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support")
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
the image even in multirect mode, then it
will be rejected in dpu_plane_atomic_check_pipe().
Hence try using multirect for resolutions which cannot be processed
by a single SSPP without exceeding the MDP clock limits.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4
overflow.
changes in v2:
- change to u64 where actually needed in the math
Fixes: c33b7c0389e1 ("drm/msm/dpu: add support for clk and bw scaling for
display")
Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/32
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm
On 9/7/2023 5:35 PM, Dmitry Baryshkov wrote:
On 08/09/2023 03:32, Abhinav Kumar wrote:
_dpu_plane_calc_bw() uses integer variables to calculate the bandwidth
used during plane bandwidth calculations. However for high resolution
displays this overflows easily and leads to below errors
Can
overflow.
Fixes: c33b7c0389e1 ("drm/msm/dpu: add support for clk and bw scaling for
display")
Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/32
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
DRM.debug calls
already comport with this".
No functional changes.
Signed-off-by: Jim Cromie
---
drivers/gpu/drm/msm/msm_fb.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
The change itself LGTM, hence
Reviewed-by: Abhinav Kumar
Now that CDM block support has been added to DPU lets also add its
entry to the DPU snapshot to help debugging.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu
On chipsets where CDM block is not available OR where support has
not been added yet do not allow YUV formats for writeback block.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/msm
Reserve CDM blocks for writeback if the format of the output fb
is YUV. At the moment, the reservation is done only for writeback
but can easily be extended by relaxing the checks once other
interfaces are ready to output YUV.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1
To setup and enable CDM block for the writeback pipeline, lets
add the pieces together to set the active bits and the flush
bits for the CDM block.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 10 ++
1 file changed, 10 insertions(+)
diff --git
CDM block will need its own logic to program the flush and active
bits in the dpu_hw_ctl layer.
Make necessary changes in dpu_hw_ctl to support CDM programming.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 34 ++
drivers/gpu/drm/msm/disp
Since CDM block support has now been added for writeback blocks
add NV12 in the list of supported WB formats.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b
In preparation of setting up CDM block, add the logic to disable it
properly during encoder cleanup.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 8
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 2 ++
2 files changed, 10 insertions(+)
diff
Add the RM APIs necessary to initialize and allocate CDM
blocks by the rest of the DPU pipeline.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 17 +
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 2 ++
2 files changed, 19 insertions(+)
diff --git
interfaces.
Until those modifications are planned and made, keep it local to
writeback.
Signed-off-by: Abhinav Kumar
---
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 3 +
.../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 123 +-
2 files changed, 125 insertions(+), 1 deletion
Add CDM blocks to the sm8250 dpu_hw_catalog to support
YUV format output from writeback block.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog
Even though there is usually only one CDM block, it can be
used by either HDMI, DisplayPort OR Writeback interfaces.
Hence its allocation needs to be tracked properly by the
resource manager to ensure appropriate availability of the
block.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm
CDM block comes with its own set of registers and operations
which can be done. In-line with other hardware sub-blocks, this
change adds the dpu_hw_cdm abstraction for the CDM block.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/Makefile| 1 +
drivers/gpu/drm/msm/disp
Add CDM blocks to the sc7280 dpu_hw_catalog to support
YUV format output from writeback block.
Signed-off-by: Abhinav Kumar
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 9 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 13 +
drivers/gpu/drm/msm/disp
phys_* for
writeback")
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
index 6a
In preparation of adding more formats to dpu writeback add
format validation to it to fail any unsupported formats.
Fixes: d7d0e73f7de3 ("drm/msm/dpu: introduce the dpu_encoder_phys_* for
writeback")
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phy
For YUV cases, setting the required format bits was missed
out in the register programming. Lets fix it now in preparation
of adding YUV formats support for writeback.
Fixes: 84a33d0fd921 ("drm/msm/dpu: add dpu_hw_wb abstraction for writeback
blocks")
Signed-off-by: Abhinav Kumar
--
for NV12, this can be verified with the below command:
./kms_writeback -d -f NV12
[1] : https://patchwork.freedesktop.org/series/122125/
Abhinav Kumar (16):
drm/msm/dpu: fix writeback programming for YUV cases
drm/msm/dpu: add formats check for writeback encoder
drm/msm/dpu: rename
On 8/17/2023 12:27 PM, Abhinav Kumar wrote:
On 8/17/2023 11:50 AM, Dmitry Baryshkov wrote:
On 08/08/2023 02:49, Abhinav Kumar wrote:
On 6/4/2023 7:45 AM, Dmitry Baryshkov wrote:
The atomic_mode_set() callback only sets the phys_enc's IRQ data. As
the
INTF and WB are statically
On 6/4/2023 7:45 AM, Dmitry Baryshkov wrote:
Follow the _dpu_encoder_irq_control() change and split the
_dpu_encoder_resource_control_helper() into enable and disable parts.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 45 +
1 file
On 6/4/2023 7:45 AM, Dmitry Baryshkov wrote:
The single helper for both enable and disable cases is too complicated,
especially if we start adding more code to these helpers. Split it into
irq_enable and irq_disable cases.
Signed-off-by: Dmitry Baryshkov
---
| 2 +-
drivers/gpu/drm/msm/dsi/dsi.h | 1 +
drivers/gpu/drm/msm/dsi/dsi_host.c | 31 +++
3 files changed, 29 insertions(+), 5 deletions(-)
Reviewed-by: Abhinav Kumar
+
6 files changed, 25 insertions(+), 2 deletions(-)
I am fine with this, thanks for working through the comments.
Reviewed-by: Abhinav Kumar
break.
But thats a very minor comment, otherwise LGTM
Reviewed-by: Abhinav Kumar
return ret;
}
base-commit: 706a741595047797872e669b3101429ab8d378ef
this spam atleast
once per reboot but after this patch, I have not seen this for 5
consecutive reboots.
Hence,
Tested-by: Abhinav Kumar # sc7280
Looking at the code flow, the dp_ctrl_reinitialize_mainlink() certainly
looks redundant where it is, considering that the clks were enabled just
On 8/17/2023 11:50 AM, Dmitry Baryshkov wrote:
On 08/08/2023 02:49, Abhinav Kumar wrote:
On 6/4/2023 7:45 AM, Dmitry Baryshkov wrote:
The atomic_mode_set() callback only sets the phys_enc's IRQ data. As the
INTF and WB are statically allocated to each encoder/phys_enc, drop
/disp/dpu1/dpu_crtc.c | 2 +-
drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Abhinav Kumar
On 5/18/2023 7:30 PM, Dmitry Baryshkov wrote:
dpu_encoder_phys_wb is the only user of encoder's atomic_check callback.
Move corresponding checks to drm_writeback_connector's implementation
and drop the dpu_encoder_phys_wb_atomic_check() function.
Signed-off-by: Dmitry Baryshkov
---
I dont
On 6/4/2023 7:45 AM, Dmitry Baryshkov wrote:
The atomic_mode_set() callback only sets the phys_enc's IRQ data. As the
INTF and WB are statically allocated to each encoder/phys_enc, drop the
atomic_mode_set callback and set the IRQs during encoder init.
For the CMD panel usecase some of IRQ
es). Its used
only for the trace in dpu_encoder_helper_wait_event_timeout(). So this
was not really breaking writeback as such because the encoder kickoff /
wait mechanism largely relies on the kickoff_cnt increment/decrement.
Nonetheless, the patch LGTM and works fine, hence
Reviewed-by:
: 6a4bc73915af ("drm/msm/dpu: drop separate dpu_core_perf_tune overrides")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 1 +
1 file changed, 1 insertion(+)
Reviewed-by: Abhinav Kumar
.")
Fix it by using the right helpers.
Fixes: 21a01abbe32a ("drm/atomic: Fix freeing connector/plane state too early by
tracking commits, v3.")
Cc: Maarten Lankhorst
Cc: Daniel Vetter
Cc: Rob Clark
Cc: Abhinav Kumar
Cc: Dmitry Baryshkov
Cc: linux-arm-...@vger.kernel.org
Cc: freedren
space from being
dumped.
Fixes: 0d1b10c63346 ("drm/msm/dpu: add DSC 1.2 hw blocks for relevant chipsets")
Reviewed-by: Abhinav Kumar
Reviewed-by: Marijn Suijten
Signed-off-by: Dmitry Baryshkov
---
Changes since v1:
- Rebased on top of the catalog changes
---
drivers/gpu/drm/msm
Hi Marek
On 8/2/2023 10:25 AM, Marek Vasut wrote:
On 8/2/23 15:08, neil.armstr...@linaro.org wrote:
Hi Marek,
On 02/08/2023 14:25, Marek Vasut wrote:
On 8/2/23 10:39, neil.armstr...@linaro.org wrote:
Hi Marek,
Hi,
On 13/07/2023 20:28, Marek Vasut wrote:
MIPI_DSI_MODE_VIDEO_NO_HFP
-by: Abhinav Kumar
deletions(-)
Reviewed-by: Abhinav Kumar
On 7/29/2023 5:19 PM, Dmitry Baryshkov wrote:
On 30/07/2023 03:00, Abhinav Kumar wrote:
On 7/13/2023 6:55 PM, Dmitry Baryshkov wrote:
As we have dropped the variadic parts of SSPP sub-blocks declarations,
deduplicate them now, reducing memory cruft.
Signed-off-by: Dmitry Baryshkov
On 7/13/2023 6:55 PM, Dmitry Baryshkov wrote:
As we have dropped the variadic parts of SSPP sub-blocks declarations,
deduplicate them now, reducing memory cruft.
Signed-off-by: Dmitry Baryshkov
---
Perhaps I am missing something here, so wanted to clarify.
The first change drops the id
h. You can stop at "Drop them completely"
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 7 ---
1 file changed, 7 deletions(-)
With that fixed,
Reviewed-by: Abhinav Kumar
On 7/28/2023 2:39 PM, Dmitry Baryshkov wrote:
On 29/07/2023 00:36, Abhinav Kumar wrote:
On 7/28/2023 2:33 PM, Dmitry Baryshkov wrote:
Switch to using data from MDSS driver to program the SSPP fetch and UBWC
configuration. As a side-effect, this also swithes the DPU driver from
On 7/28/2023 2:33 PM, Dmitry Baryshkov wrote:
Switch to using data from MDSS driver to program the SSPP fetch and UBWC
configuration. As a side-effect, this also swithes the DPU driver from
DPU_HW_UBWC_VER_xx values to the UBWC_x_y enum, which reflects
the hardware register values.
On 7/27/2023 8:26 AM, Dmitry Baryshkov wrote:
On 27/07/2023 18:24, Abhinav Kumar wrote:
On 7/27/2023 1:39 AM, Dmitry Baryshkov wrote:
On Thu, 27 Jul 2023 at 02:20, Abhinav Kumar
wrote:
On 5/21/2023 10:10 AM, Dmitry Baryshkov wrote:
Switch to using data from MDSS driver to program
On 7/27/2023 1:39 AM, Dmitry Baryshkov wrote:
On Thu, 27 Jul 2023 at 02:20, Abhinav Kumar wrote:
On 5/21/2023 10:10 AM, Dmitry Baryshkov wrote:
Switch to using data from MDSS driver to program the SSPP fetch and UBWC
configuration.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu
-by: Abhinav Kumar
On 5/21/2023 10:10 AM, Dmitry Baryshkov wrote:
Switch to using data from MDSS driver to program the SSPP fetch and UBWC
configuration.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 18 +++---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 7
On 7/26/2023 3:58 PM, Dmitry Baryshkov wrote:
On Thu, 27 Jul 2023 at 01:30, Abhinav Kumar wrote:
On 5/21/2023 10:10 AM, Dmitry Baryshkov wrote:
As we are going to use MDSS data for DPU programming, populate missing
MDSS data. The UBWC 1.0 and no UBWC cases do not require MDSS
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