On Tue, Nov 06, 2018 at 12:38:28PM +0530, Sharat Masetty wrote:
> Build a6xx_gpu_state.c only if either of CONFIG_DEBUG_FS, CONFIG_DEV_COREDUMP
> is defined.
Can you do the same for the other targets too? With that,
Reviewed-by: Jordan Crouse
> Signed-off-by: Sharat Masetty
> --
On Tue, Nov 06, 2018 at 12:38:29PM +0530, Sharat Masetty wrote:
> This patch simply fixes a typo for the name of an indexed register.
> CP_MEMPOOOL -> CP_MEMPOOL.
>
> Signed-off-by: Sharat Masetty
Reviewed by: Jordan Crouse
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu_sta
On Tue, Nov 06, 2018 at 02:36:30PM -0800, Jeykumar Sankaran wrote:
> msm maintains a separate structure to define vblank
> work definitions and a list to track events submitted
> to the workqueue. We can avoid this redundant list
> and its protection mechanism, if we subclass the
> work object to e
Do some cleanup in the static inline functions defined in
dpu_media_info.h by cleaning up gotos and unneeded local
variables.
v3: Added spaces between operators per Seal Paul and Sam Ravnborg
Signed-off-by: Jordan Crouse
---
.../gpu/drm/msm/disp/dpu1/msm_media_info.h| 164
usefulness.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 12 +++-
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 10 --
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 2 +-
.../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 11
sticks out like a sore thumb when debugging.
Jordan Crouse (9):
drm/msm: Add a common function to free kernel buffer objects
drm/msm: Remove sgt from the mmu unmap function
drm/msm: Split msm_gem_get_iova into two steps
drm/msm: Clean up and enhance the output of the 'gem' debugfs
The scatter gather table doesn't need to be passed in for the
MMU unmap function.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.h | 2 +-
drivers/gpu/drm/msm/msm_gem.c | 2 +-
drivers/gpu/drm/msm/msm_gem_vma.c | 4 ++--
drivers/gpu/drm/msm/msm_iommu.c | 3 +--
dr
Buffer objects allocated with msm_gem_kernel_new() are mostly
freed the same way so we can save a few lines of code with a
common function.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 13 ++---
drivers/gpu/drm/msm/adreno/a5xx_power.c | 13
Split the operation of msm_gem_get_iova into two operations:
1) allocate an iova and 2) map (pin) the backing memory int the
iommu. This is the first step toward allowing memory pinning
to occur independently of the iova management.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.h
Add a name field to struct drm_msm_gem_new to allow userspace
to specify a name/description for gem buffers to improve
debugging and tracking.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.c | 5 +++--
drivers/gpu/drm/msm/msm_drv.h | 2 +-
drivers/gpu/drm/msm/msm_gem.c | 16
that the memory be immediately available.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 ++-
drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c | 4 ++--
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 2 +-
drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 2 +-
drivers/gpu/drm
, we're just focusing on getting
the counting right and setting ourselves up to be ready
for the future.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_debugfs.c | 6 +--
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 9 ++--
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
ng is always around) but
it did make the debug output look odd. Allocate and pin the iova
at create time instead.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 9 -
drivers/gpu/drm/msm/msm_ringbuffer.c| 4 ++--
2 files changed, 2 insertions(+), 11 dele
Add headers for the 'gem' debugfs file to make it easier to remember
what all the values mean and move the list of virtual address regions
to the next line and add the name and map status to make it clearer
what we are looking at.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm
size madv name
0004: I 0 ( 1) 70b79eca 4096 memptrs
vmas: [gpu: 0100,mapped,inuse=1]
0002: I 0 ( 1) 31ed4074 00032768 ring0
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c
Thanks for the patch. Perhaps a small blurb here for the commit log to let
folks know what your intent was.
On Wed, Nov 14, 2018 at 05:24:12PM -0500, Jonathan Marek wrote:
> Signed-off-by: Jonathan Marek
> ---
> drivers/gpu/drm/msm/Kconfig | 4 ++--
> drivers/gpu/drm/msm/msm_debugfs.c |
that:
Reviewed-by: Jordan Crouse
> Signed-off-by: Jonathan Marek
> ---
> drivers/gpu/drm/msm/Makefile | 1 +
> drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 445 +
> drivers/gpu/drm/msm/adreno/a2xx_gpu.h | 21 +
> drivers/gpu/d
.c:459:1-6:
> WARNING: invalid free of devm_ allocated data
I had partial fix of this in my ill-fated patch from a few weeks ago but this
is better.
Reviewed-by: Jordan Crouse
> Signed-off-by: YueHaibing
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 --
> 1 file changed, 2
On Fri, Nov 16, 2018 at 11:22:22AM -0800, Jeykumar Sankaran wrote:
> Add display port support in DPU by creating hooks
> for DP encoder enumeration and encoder mode
> initialization.
>
> This change is based on the SDM845 Display port
> driver changes[1].
>
> [1] https://lwn.net/Articles/768265/
power domain and does
the magic to "enable" and disable it at the right points.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 41 ++-
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 2 ++
2 files changed, 42 insertions(+), 1 deletion(-)
di
: Jordan Crouse
---
drivers/clk/qcom/gpucc-sdm845.c | 30 ++
1 file changed, 26 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/qcom/gpucc-sdm845.c b/drivers/clk/qcom/gpucc-sdm845.c
index 7a11b70b33f4..06254329ea33 100644
--- a/drivers/clk/qcom/gpucc-sdm845.c
+++ b
In very extreme cases an individual gdsc may wish to override the
power domain enable or disable callback functions for their own
purposes. Only set the generic gdsc callback if the function pointers
are not already set.
Signed-off-by: Jordan Crouse
---
drivers/clk/qcom/gdsc.c | 6 --
1
The GMU code currently has some misguided code to try to work around
a hardware quirk that requires the power domains on the GPU be
collapsed in a certain order. Upcoming patches will do this the
right way so get rid of the unused and unwanted regulator
code.
Signed-off-by: Jordan Crouse
://patchwork.kernel.org/patch/10563887/
Jordan Crouse (4):
drm/msm/a6xx: Remove unwanted regulator code
clk: qcom: gdsc: Don't override existing gdsc pd functions
clk: qcom: Add a dummy enable function for GX gdsc
drm/msm/gpu: Attach to the GPU GX power domain
drivers/clk/qcom/g
On Tue, Nov 20, 2018 at 03:24:37PM +0530, Vivek Gautam wrote:
> dma_map_sg() expects a DMA domain. However, the drm devices
> have been traditionally using unmanaged iommu domain which
> is non-dma type. Using dma mapping APIs with that domain is bad.
>
> Replace dma_map_sg() calls with dma_sync_s
> Signed-off-by: Sharat Masetty
Reviewed-by: Jordan Crouse
> ---
> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> b/drivers/gpu/drm/msm/adreno/adreno_gpu.
On Tue, Nov 20, 2018 at 05:07:29PM +0530, Sharat Masetty wrote:
> The current implementation of ascii85_encode() does not copy the encoded
> buffer 'z' to the output buffer in case the input is zero. This patch
> simply adds this missing piece. This makes it easier to use this
> function to encode
;
> Signed-off-by: Sharat Masetty
Looks okay. There might be some code consolidation to be had here but perhaps
you've already addressed this in a future patch or we can do it as a rainy day
cleanup.
Reviewed-by: Jordan Crouse
> ---
> drivers/gpu/drm
th. With this there
> is an immediate >10X speed improvement in crashstate save time.
>
> Signed-off-by: Sharat Masetty
Reviewed-by: Jordan Crouse
I like this a lot.
> ---
> Changes from v1:
> Addressed comments from Jordan Crouse
&g
On Tue, Nov 20, 2018 at 11:54:46PM -0800, Stephen Boyd wrote:
> Quoting Jordan Crouse (2018-11-19 15:47:06)
> > 99.999% of the time during normal operation the GMU is responsible
> > for power and clock control on the GX domain and the CPU remains
> > blissfully unaware.
On Wed, Nov 21, 2018 at 12:00:51AM -0800, Stephen Boyd wrote:
> Quoting Jordan Crouse (2018-11-19 15:47:02)
> > The GPU GX domain on SDM845 is nominally managed by the GMU microcontroller
> > but there are certain circumstances when the CPU needs to be sure that the
> >
On Wed, Nov 21, 2018 at 08:52:31PM -0500, Jonathan Marek wrote:
> This patch allows using drm/msm without qcom display hardware. This is
> especially useful for iMX5 hardware, which has a a2xx GPU but uses the
> imx-drm driver for display.
>
> Signed-off-by: Jonathan Marek
> ---
> v2: added commi
On Thu, Nov 22, 2018 at 03:37:54PM +0530, Vivek Gautam wrote:
> Hi Tomasz, Jordan,
>
>
> On 11/21/2018 9:18 AM, Tomasz Figa wrote:
> >
> >>>+ for_each_sg(msm_obj->sgt->sgl, s,
> >>>+ msm_obj->sgt->nents, i)
> >>>+ s
On Mon, Nov 26, 2018 at 07:31:48PM +, Will Deacon wrote:
> Hi Rob,
>
> On Tue, Nov 13, 2018 at 08:12:35AM -0500, Rob Clark wrote:
> > On Tue, Nov 13, 2018 at 1:32 AM Will Deacon wrote:
> > > On Fri, Nov 09, 2018 at 01:01:55PM -0500, Rob Clark wrote:
> > > > On Mon, Oct 29, 2018 at 3:09 PM Wil
On Tue, Nov 27, 2018 at 03:58:13PM -0800, Jeykumar Sankaran wrote:
> Specify geometry for DPU iommu domain which sets
> the address space for gem allocations.
>
> Signed-off-by: Jeykumar Sankaran
> Suggested-by: Jordan Crouse
> Suggested-by: Vivek Gautam
There is
01287/
Jordan Crouse (1):
drm/msm/a6xx: Add support for an interconnect path
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 20
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 9 +
drivers/gpu/drm/msm/msm_gpu.h | 3 +++
3 files changed, 32 insertions(+)
--
2
not yet exist.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 20
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 9 +
drivers/gpu/drm/msm/msm_gpu.h | 3 +++
3 files changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno
On Thu, Nov 01, 2018 at 07:25:23PM -0700, Jeykumar Sankaran wrote:
> DPU is short for the Display Processing Unit. It is the display
> controller on Qualcomm SDM845 chips.
>
> This change adds MDSS and DSI nodes to enable display on the
> target device.
>
> Changes in v2:
>- Beefed up com
://lists.freedesktop.org/archives/freedreno/2018-November/004347.html
v2: Make sure to pass values in correct units
Jordan Crouse (1):
drm/msm/a6xx: Add support for an interconnect path
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 20
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 9 +
drivers
not yet exist.
v2: Absolute bandwidth values should be in KBps
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 20
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 9 +
drivers/gpu/drm/msm/msm_gpu.h | 3 +++
3 files changed, 32
not yet exist.
v3: Absolute bandwidth values should be specified in KBps
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 20
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 9 +
drivers/gpu/drm/msm/msm_gpu.h | 3 +++
3 files changed, 32
s and
passed a value that overflowed the API. Correct bandwidth
values are now passed.
[1] https://lists.freedesktop.org/archives/freedreno/2018-November/004347.html
v3: Actually send correct patch with correct units
v2: Make sure to pass values in correct units
Jordan Crouse (1):
drm/msm/a6xx
On Thu, Nov 29, 2018 at 01:48:15PM -0500, Rob Clark wrote:
> On Thu, Nov 29, 2018 at 10:54 AM Christoph Hellwig wrote:
> >
> > On Thu, Nov 29, 2018 at 09:42:50AM -0500, Rob Clark wrote:
> > > Maybe the thing we need to do is just implement a blacklist of
> > > compatible strings for devices which
dadb36b7ec42 ("drm/msm: Add a common function to free kernel buffer objects")
missed freeing the crashdumper state for a6xx.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 11 +--
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/d
Add a buffer object name for the a6xx crashdumper so it can be
seen with the changes introduced by 7799a98edd
("drm/msm: Add a name field for gem objects").
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 5 -
1 file changed, 4 insertions(+),
The GMU code currently has some misguided code to try to work around
a hardware quirk that requires the power domains on the GPU be
collapsed in a certain order. Future changes will do this the
right way so get rid of the unused and unwanted regulator
code.
Signed-off-by: Jordan Crouse
On Mon, Dec 03, 2018 at 04:18:16PM -0500, Jonathan Marek wrote:
> Signed-off-by: Jonathan Marek
> ---
> arch/arm/boot/dts/imx51.dtsi | 17 +
> arch/arm/boot/dts/imx53.dtsi | 17 +
> 2 files changed, 34 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx51.dtsi b/
ntire path.
v3: No changes
Reviewed-by: Sean Paul
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/Makefile | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 15 +
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h | 7 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_irq.c
Remove some unused container_of() helper functions.
v3: No changes
v2: Retained still used helper functions in the name of readability
Reviewed-by: Sean Paul
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 10 --
drivers/gpu/drm/msm/disp/dpu1
I dropped
("drm/msm/dpu: Use DEFINE_SHOW_ATTRIBUTE") in favor of
https://patchwork.freedesktop.org/patch/265159/
Which does the same thing but is a little bit more tree-wide in its efforts.
Jordan Crouse (10):
drm/msm/dpu: Remove dpu_dbg
drm/msm/dpu: Remove dpu_crtc_get_mixer_he
e.
v3: No changes
v2: Removed a cleanup intended for a different patch
Reviewed-by: Sean Paul
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c | 10 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
away too.
Also, use standard API functions where applicable instead of
using hand written code.
v3: No changes
v2: Add more code; most of the dpu debugfs files should be
addressed now.
Reviewed-by: Sean Paul
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 30
ther patch
Reviewed-by: Sean Paul
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/Makefile |3 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.c | 2393 -
drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.h | 103 -
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.
.
Reviewed-by: Sean Paul
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 12 +++-
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 10 --
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 2 +-
.../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 11
The static inline function dpu_crtc_enabled() is only called once
and the function that calls it in turn is only called once and
the return value can be easily checked in the calling functions
so collapse everything down.
v3: No changes
Reviewed-by: Sean Paul
Signed-off-by: Jordan Crouse
Do some cleanup in the static inline functions defined in
dpu_media_info.h by cleaning up gotos and unneeded local
variables.
v3: Added spaces between operators per Seal Paul and Sam Ravnborg
Reviewed-by: Sean Paul
Signed-off-by: Jordan Crouse
---
.../gpu/drm/msm/disp/dpu1/msm_media_info.h
dpu_crtc_get_mixer_height() is only used once and the value it
returns can be easily derived from the calling function.
v3: No changes
Reviewed-by: Sean Paul
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 3 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 13
Allow the KMS operation 'irq_postinstall' to be optional
so that the target display drivers don't need to define
a dummy function if they don't need one.
v3: No changes
Reviewed-by: Sean Paul
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.c | 6 +
not yet exist.
v3: Use macros and change port string per Georgi Djakov
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/Kconfig | 1 +
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 20
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 9 +
drivers/gpu/drm/msm
On Fri, Dec 07, 2018 at 10:06:56AM -0700, Jordan Crouse wrote:
> Try to get the interconnect path for the GPU and vote for the maximum
> bandwidth to support all frequencies. This is needed for performance.
> Later we will want to scale the bandwidth based on the frequency to
> also
On Mon, Dec 10, 2018 at 05:34:22PM +0530, Sharat Masetty wrote:
> The gpu crashstate's base objects registers pointer can be NULL if the
> target implementation decides to capture the register dump on its own.
> This patch simply checks for NULL before dereferencing.
>
> Signed-off-by: Sharat Mase
On Mon, Dec 10, 2018 at 05:34:21PM +0530, Sharat Masetty wrote:
> We are not really checking the state of the adreno_gpu_state_get()
> function at the callers and in addition the state capture is mostly a
> best effort service, so make the function return void.
Reviewed-by: Jord
On Mon, Dec 10, 2018 at 05:34:22PM +0530, Sharat Masetty wrote:
> The gpu crashstate's base objects registers pointer can be NULL if the
> target implementation decides to capture the register dump on its own.
> This patch simply checks for NULL before dereferencing.
Hi Sharat - this doesn't apply
respective nodes and rename
the iommu device.
v4: Rebase
v3: Split GMU PDC region into two GPU specific sections, fix indentation,
really use qcom,gmu for the phandle name
v2: changed qcom,arc-level to qcom,level following discussion with Viresh;
change gmu phandle to qcom,gmu per Rob
Jordan
Add the nodes to describe the Adreno GPU and GMU devices.
Signed-off-by: Jordan Crouse
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 123 +++
1 file changed, 123 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index
Document the device tree bindings for the Adreno GMU device
available on Adreno a6xx targets.
Reviewed-by: Rob Herring
Signed-off-by: Jordan Crouse
---
.../devicetree/bindings/display/msm/gmu.txt | 54 +++
.../devicetree/bindings/display/msm/gpu.txt | 2 +
2 files changed
On Wed, Dec 12, 2018 at 11:26:46AM -0800, Doug Anderson wrote:
> Hi,
>
> On Wed, Dec 12, 2018 at 9:31 AM Jordan Crouse wrote:
> >
> > Document the device tree bindings for the Adreno GMU device
> > available on Adreno a6xx targets.
> >
> > Reviewed-by:
Add the nodes to describe the Adreno GPU and GMU devices.
Signed-off-by: Jordan Crouse
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 123 +++
1 file changed, 123 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index
Update the GPU bindings and document the new bindings for the GMU
device found with Adreno a6xx targets.
Signed-off-by: Jordan Crouse
---
.../devicetree/bindings/display/msm/gmu.txt | 56 +++
.../devicetree/bindings/display/msm/gpu.txt | 41 +-
2 files changed
device.
v4: Rebase
v3: Split GMU PDC region into two GPU specific sections, fix indentation,
really use qcom,gmu for the phandle name
v2: changed qcom,arc-level to qcom,level following discussion with Viresh;
change gmu phandle to qcom,gmu per Rob
*** BLURB HERE ***
Jordan Crouse (2):
dt
Two quick patches to document and add an interconnect port definition
for the sdm845 GPU.
This is based on the base GPU DT changes:
https://patchwork.freedesktop.org/series/39308/
As well as the DT nodes from Georgi:
https://patchwork.kernel.org/patch/10719483/
Jordan Crouse (2):
dt-bindings
Define an interconnect port for the GPU to set bus
capabilities.
Signed-off-by: Jordan Crouse
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 0a5ddfc4c59b
Add documentation for the interconnect and interconnect-names bindings
for the GPU node as detailed by bindings/interconnect/interconnect.txt.
Signed-off-by: Jordan Crouse
---
Documentation/devicetree/bindings/display/msm/gpu.txt | 6 ++
1 file changed, 6 insertions(+)
diff --git a
v2:
> - rebase on [2] (Sean Paul)
> - remove unwanted error checks and
> switch cases (Jordan Crouse)
> changes in v3:
> - add dp support after fixing
> the current code base for error logging (Sean Paul)
>
> [1] https://lwn.net/Articles/7
On Fri, Dec 14, 2018 at 02:19:12PM +0530, Jayant Shekhar wrote:
> Remove unused functions and macros from dpu hw interrupts
> file.
>
> Signed-off-by: Jayant Shekhar
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 30
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interr
On Thu, Dec 13, 2018 at 10:51:03AM -0800, Jeykumar Sankaran wrote:
> Bail out KMS hw init on display initialization failures with
> proper error logging.
>
> changes in v3:
> - introduced in the series
>
> Signed-off-by: Jeykumar Sankaran
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c |
match latest per Doug Anderson
*** BLURB HERE ***
Jordan Crouse (2):
dt-bindings: drm/msm/a6xx: Document interconnect properties for GPU
arm64: dts: sdm845: Add interconnect for GPU
Documentation/devicetree/bindings/display/msm/gpu.txt | 6 ++
arch/arm64/boot/dts/qcom/sdm845.dtsi
Add documentation for the interconnect and interconnect-names bindings
for the GPU node as detailed by bindings/interconnect/interconnect.txt.
Signed-off-by: Jordan Crouse
---
Documentation/devicetree/bindings/display/msm/gpu.txt | 6 ++
1 file changed, 6 insertions(+)
diff --git a
Define an interconnect port for the GPU to set bus
capabilities.
Signed-off-by: Jordan Crouse
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 0a5ddfc4c59b
On Mon, Dec 17, 2018 at 03:20:10PM -0600, Rob Herring wrote:
> On Wed, Dec 12, 2018 at 02:18:47PM -0700, Jordan Crouse wrote:
> > Update the GPU bindings and document the new bindings for the GMU
> > device found with Adreno a6xx targets.
> >
> > S
On Tue, Dec 18, 2018 at 06:50:38PM +0530, Jayant Shekhar wrote:
> Remove unused functions from dpu plane interface
> and unused variables from dpu plane state structure.
>
> Signed-off-by: Jayant Shekhar
Reviewed-by: Jordan Crouse
> ---
> drivers/gpu/drm/msm/disp/dpu
On Tue, Dec 18, 2018 at 11:22:01AM -0600, Rob Herring wrote:
> On Fri, Dec 14, 2018 at 03:16:39PM -0700, Jordan Crouse wrote:
> > Add documentation for the interconnect and interconnect-names bindings
> > for the GPU node as detailed by bindings/interconnect/interconnect.txt.
>
indentation,
really use qcom,gmu for the phandle name
v2: changed qcom,arc-level to qcom,level following discussion with Viresh;
change gmu phandle to qcom,gmu per Rob
Jordan Crouse (6):
drm/msm/gpu: Remove hardcoded interrupt name
drm/msm: drop interrupt-names
ARM: dts: qcom: Removed unused
Every GPU core only has one interrupt so there isn't any
value in looking up the interrupt by name. Remove the name (which
is legacy anyway) and use platform_get_irq() instead.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 1 -
drivers/gpu/drm/msm/msm_
'interrupt-names' shouldn't be used in cases when there is only
one interrupt and it is not otherwise used in the driver.
Signed-off-by: Jordan Crouse
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi
Add the nodes to describe the Adreno GPU and GMU devices.
Signed-off-by: Jordan Crouse
---
v7: Updated the GMU compatible string and removed interrupt-names
arch/arm64/boot/dts/qcom/sdm845.dtsi | 122 +++
1 file changed, 122 insertions(+)
diff --git a/arch/arm64/boot
'interrupt-names' shouldn't be used in cases when there is only
one interrupt and it is not otherwise used in the driver.
Signed-off-by: Jordan Crouse
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dts
Update the GPU bindings and document the new bindings for the GMU
device found with Adreno a6xx targets.
Signed-off-by: Jordan Crouse
---
v7: Updated the GMU compatible string and clarified details about when clocks
can be optional on the GPU
.../devicetree/bindings/display/msm/gmu.txt | 59
Each GPU core only uses one interrupt so we don't to look up
an interrupt by name and thereby we don't need interrupt-names.
Signed-off-by: Jordan Crouse
---
Documentation/devicetree/bindings/display/msm/gpu.txt | 1 -
1 file changed, 1 deletion(-)
diff --git a/Documentation/
On Tue, Dec 18, 2018 at 02:29:25PM -0800, Doug Anderson wrote:
> Hi,
>
> On Tue, Dec 18, 2018 at 10:32 AM Jordan Crouse wrote:
> >
> > 'interrupt-names' shouldn't be used in cases when there is only
> > one interrupt and it is not otherwise used in
interconnect name from driver and bindings
Jordan Crouse (3):
drm/msm/a6xx: Add support for an interconnect path
dt-bindings: drm/msm/a6xx: Document interconnect properties for GPU
arm64: dts: sdm845: Add interconnect for GPU
.../devicetree/bindings/display/msm/gpu.txt | 4
arch/arm64
Add documentation for the interconnect and interconnect-names bindings
for the GPU node as detailed by bindings/interconnect/interconnect.txt.
Signed-off-by: Jordan Crouse
---
Documentation/devicetree/bindings/display/msm/gpu.txt | 4
1 file changed, 4 insertions(+)
diff --git a
Define an interconnect port for the GPU to set bus
capabilities.
Signed-off-by: Jordan Crouse
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 1005f1eb1920
not yet exist.
v5: Remove hardcoded interconnect name and just use the default
v4: Don't use a port string at all to skip the need for names in the DT
v3: Use macros and change port string per Georgi Djakov
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/Kconfig | 1 +
dr
On Thu, Dec 20, 2018 at 10:46:45AM -0800, Chia-I Wu wrote:
> It gets the generic states from the adreno core.
>
> This also adds a missing NULL check in msm_gpu_open.
>
> Signed-off-by: Chia-I Wu
Thanks for the patch. We have an expanded version of the 6xx gpu state in
msm-next [1]. You can l
On Thu, Dec 20, 2018 at 10:47:02AM -0800, Chia-I Wu wrote:
> memptrs_bo is used to store msm_rbmemptrs. Size it correctly.
>
> Signed-off-by: Chia-I Wu
Thanks for your patch. I'm really glad somebody is looking seriously at this
code. We have this in msm-next:
https://cgit.freedesktop.org/~ro
and will need to
> land in a tree that contains that patch.
>
> This patch needs to land before the patch ("arm64: dts: sdm845: Add
> gpu and gmu device nodes") since if a tree contains the device tree
> patch but not this one you'll get a crash at bootup.
>
Add the nodes to describe the Adreno GPU and GMU devices for sdm845.
Signed-off-by: Jordan Crouse
Reviewed-by: Douglas Anderson
Tested-by: Douglas Anderson
---
This has the following dependencies:
[v11,1/9] dt-bindings: opp: Introduce opp-level bindings
https://patchwork.kernel.org/patch
mu device nodes") since if a tree contains the device tree
> patch but not this one you'll get a crash at bootup.
>
> Fixes: 4b565ca5a2cb ("drm/msm: Add A6XX device support")
> Signed-off-by: Douglas Anderson
I agree that splitting these out make sense for the workfl
Commit 24937c540917 ("dt-bindings: drm/msm/a6xx: Document GMU and update
GPU bindings") mistakenly omitted the GMU bindings as seen in [1].
Return them to their rightful place.
[1] https://patchwork.freedesktop.org/patch/268679/
Signed-off-by: Jordan Crouse
Reviewed-by: R
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