Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 70
1 file changed, 70 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
index e3c4c250238b7..1c7de7d6870cf 100644
--- a/drivers/gpu
>Is the "| 0" really adding value here?
As far as I can see, it is present in every other config.
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@ 0x47000
- adjust .max_width
- write a more descriptive commit message
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 76
1 file changed, 76 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
b/drivers/gpu/drm/msm/disp/mdp5
Hi Greg, thanks for your review!
>Why do we need this noise in the kernel log?
I guess it could be left there as a debug print? Knowing your hardware
revision seems like a good, but yeah, not a necessary thing.
>You can drop the GPL boilerplate text and add a proper SPDX line at the
>top.
Add missing halt_check, hwcg_reg and hwcg_bit properties.
These were likely omitted when porting the driver upstream.
Signed-off-by: Konrad Dybcio
---
drivers/clk/qcom/gcc-sdm660.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660
From: Xiaozhe Shi
Add the REVID device driver. The REVID driver will print out the PMIC
revision at probe time.
Signed-off-by: Xiaozhe Shi
[konradyb...@gmail.com: Fast-forward the driver from kernel 4.14 to 5.8,
convert binding to yaml]
Signed-off-by: Konrad Dybcio
---
.../bindings/soc/qcom
This commit adds support for the MDP5 IP on Snapdragon
636/660.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 105 +++
1 file changed, 105 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
b/drivers/gpu/drm/msm/disp/mdp5
/konradybcio/linux/commits/ninges_labs
Konrad Dybcio (8):
clk: qcom: gcc-sdm660: Add missing modem reset
phy: qcom-qusb2: Add support for SDM630/660
drivers: usb: dwc3-qcom: Add sdm660 compatible
drm/msm/dsi: Add phy configuration for SDM630/636/660
drm/msm/mdp5: Add MDP5 configuration
These SoCs make use of the 14nm phy, but at different
addresses than other 14nm units.
Signed-off-by: Konrad Dybcio
---
.../devicetree/bindings/display/msm/dsi.txt| 1 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 +
drivers
QUSB on these SoCs actually uses *almost* the same
configuration that msm8996 does, so we can reuse
the phy_cfg from there with just a single change
(se clock scheme).
Signed-off-by: Konrad Dybcio
---
Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml | 1 +
drivers/phy/qualcomm/phy-qcom
This will be required in order to support the
modem upstream.
Signed-off-by: Konrad Dybcio
---
drivers/clk/qcom/gcc-sdm660.c | 1 +
include/dt-bindings/clock/qcom,gcc-sdm660.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom
Signed-off-by: Konrad Dybcio
---
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml | 1 +
drivers/usb/dwc3/dwc3-qcom.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
b/Documentation/devicetree/bindings/usb
This also applies to sdm630/636 and their SDA
counterparts.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 21 +
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
2 files changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
b/drivers/gpu
This commit adds support for the MDP5 IP on Snapdragon
630. The configuration is different from SDM660's, as
the latter one has two DSI outputs.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 93
1 file changed, 93 insertions(+)
diff --git
Fixes: f2a76a2955c0 (clk: qcom: Add Global Clock controller (GCC)
driver for SDM660)
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>Fixes tag?
Can I add it here? I supose I can.
Fixes: f2a76a2955c0 (clk: qcom: Add Global Clock controller (GCC)
driver for SDM660)
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> Konrad, can you please test this below change without your change?
This brings no difference, a BUG still happens. We're still calling to_a6xx_gpu
on ANY device that's probed! Too bad it won't turn my A330 into an A640..
Also, relying on disabling LLCC in the config is out of question as it
The previous registers were *almost* correct, but instead of
PHYs, they were pointing at DSI PLLs, resulting in the PHY id
autodetection failing miserably.
Fixes: dcefc117cc19 ("drm/msm/dsi: Add support for msm8x94")
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/dsi/phy/dsi_
Using this code on A5xx (and probably older too) causes a
smmu bug.
Fixes: 474dadb8b0d5 ("drm/msm/a6xx: Add support for using system cache(LLC)")
Signed-off-by: Konrad Dybcio
Tested-by: AngeloGioacchino Del Regno
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 21
Kind reminder that MSM8974, 8994, 8992 and friends are held back by the lack of
IOMMU support upstream. There has been an attempt back in 2014(!) [1], but it
was either overlooked or forgotten about ever since. I'd be more than happy to
see someone look into this, as I have some other bits
The maximum mdp clock rate on msm8974v2 is 320MHz. Fix it.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
index
While passing the A530-specific lm_setup func to A530 and A540
to !A530 was fine back when only these two were supported, it
certainly is not a good idea to send A540 specifics to smaller
GPUs like A508 and friends.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a5xx_power.c | 2
Del Regno
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
index b2ff68a15791..f3f1c03c7db9 100644
--- a/drivers/gpu/drm/msm/dsi
VDDA is not present and the specified load value is wrong. Fix it.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 1 -
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 2 +-
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi
There are various SKUs of A619, ranging from 565 MHz to 850 MHz, depending
on the bin. Add support for distinguishing them, so that proper frequency
ranges can be applied, depending on the HW.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 18 ++
1 file
Add support for the Adreno 619 GPU, as found in Snapdragon 690 (SM6350),
480 (SM4350) and 750G (SM7225).
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 11 ++--
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 70 +-
drivers/gpu/drm/msm/adreno
Leading spaces are not something checkpatch likes, and it says so when
they are present. Use tabs consistently to indent function body and
unwrap a 83-char-long line, as 100 is cool nowadays.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 17 -
1 file
There is *almost no reason* to keep separate compatibles for different
SoCs utilizing the DPU1 driver, as it checks the HW version at runtime.
Introduce a common compatible, while not removing the old ones to keep
old DT compatibility.
Signed-off-by: Konrad Dybcio
---
Bar some very very very
Leading spaces are not something checkpatch likes, and it says so when
they are present. Use tabs consistently to indent function body and
unwrap a 83-char-long line, as 100 is cool nowadays.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 17 -
1 file
There are various SKUs of A619, ranging from 565 MHz to 850 MHz, depending
on the bin. Add support for distinguishing them, so that proper frequency
ranges can be applied, depending on the HW.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 +-
drivers/gpu/drm/msm
Add support for the Adreno 619 GPU, as found in Snapdragon 690 (SM6350),
480 (SM4350) and 750G (SM7225).
Signed-off-by: Konrad Dybcio
---
Changes in v2:
- Don't reserve icache/dcache regions on legacy GMUs, as that
is apparently not necessary and simply a downstream leftover.
drivers/gpu/drm
On 15.09.2023 14:59, Dan Carpenter wrote:
> The irq_of_parse_and_map() function returns zero on error. It
> never returns negative error codes. Fix the check.
>
> Fixes: a689554ba6ed ("drm/msm: Initial add DSI connector support")
> Signed-off-by: Dan Carpenter
> --
Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 96 +--
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 451
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 1 +
drivers/gpu/drm
QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 21 +
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 3 +++
2 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
b/drivers/gpu/drm/
Provide the necessary alternations to mostly support state dumping on
A7xx. Newer GPUs will probably require more changes here. Crashdumper
and debugbus remain untested.
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu
Allow A7xx SKUs, such as the A730 GPU found on SM8450 and friends.
They use GMU for all things DVFS, just like most A6xx GPUs.
Reviewed-by: Krzysztof Kozlowski
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
Documentation
# on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 88 +-
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 82 +---
drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 27
Add support for Adreno 730, also known as GEN7_0_x, found on SM8450.
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 126 -
drivers/gpu/drm/msm/adreno
that can't receive data on its end of the bus.
Failing to do this will result in inexplicable GMU timeouts or worse.
This is a rather ugly hack which introduces a whole lot of latency.
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
MESA_LOADER_DRIVER_OVERRIDE=zink kmscube
[1]
https://lore.kernel.org/linux-arm-msm/20230517-topic-a7xx_prep-v4-0-b16f273a9...@linaro.org/
[2] https://github.com/SoMainline/linux/commits/topic/a7xx_dt
[3] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217
Signed-off-by: Konrad Dybcio
Reviewed-by: Krzysztof Kozlowski
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
.../devicetree/bindings/display/msm/gmu.yaml | 40 +-
1 file changed, 39 insertions(+), 1 deletion(-)
diff --git a/Documentation/
-by: Krzysztof Kozlowski
Signed-off-by: Konrad Dybcio
---
Documentation/devicetree/bindings/display/msm/gmu.yaml | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml
b/Documentation/devicetree/bindings/display/msm/gmu.yaml
index 20ddb89a4500
Add some missing definitions required for A7 support.
This may be substituted with a mesa header sync.
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 9 +
drivers/gpu/drm/msm
On 23.08.2023 14:56, Konrad Dybcio wrote:
> A740 builds upon the A730 IP, shuffling some values and registers
> around. More differences will appear when things like BCL are
> implemented.
>
> adreno_is_a740_family is added in preparation for more A7xx GPUs,
> the logic ch
On 13.09.2023 21:19, Danila Tikhonov wrote:
> SM7150 has 5 power levels which correspond to 5 speed-bin values: 0,
> 128, 146, 167, 172. Speed-bin value is calulated as FMAX/4.8MHz round up
> to zero decimal places.
>
> The vendor's FW GMU is called a618_gmu.bin. And also a618 on SM7150 uses
>
On 10/13/23 08:57, Dan Carpenter wrote:
On Thu, Oct 12, 2023 at 06:33:20PM +0200, Konrad Dybcio wrote:
@@ -1810,8 +1816,8 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct
device_node *node)
return 0;
- if (!IS_ERR_OR_NULL(gmu->qmp))
- qmp_put(gmu-&
'
Add the usual dependency that still allows compiling without QMP but
otherwise avoids the broken combination of options.
Fixes: 88a0997f2f949 ("drm/msm/a6xx: Send ACD state to QMP at GMU resume")
Signed-off-by: Arnd Bergmann
---
Right, thanks!
Reviewed-by: Konrad Dybcio
Konrad
On 10/17/23 09:33, Rob Clark wrote:
On Mon, Oct 16, 2023 at 1:12 PM Akhil P Oommen wrote:
On Tue, Sep 26, 2023 at 08:24:37PM +0200, Konrad Dybcio wrote:
Some (many?) devices with A635 expect a ZAP shader to be loaded.
Set the file name to allow for that.
Signed-off-by: Konrad Dybcio
On 9/28/23 13:16, Dmitry Baryshkov wrote:
Add the driver for pre-QMP Qualcomm HDMI PHYs. Currently it suppports
Qualcomm MSM8960 / APQ8064 platforms, other platforms will come later.
Signed-off-by: Dmitry Baryshkov
---
[...]
+{
+ unsigned int pixclk =
On 11/6/23 16:45, Neil Armstrong wrote:
Hi,
On 28/09/2023 13:35, Dmitry Baryshkov wrote:
From: Konrad Dybcio
Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there are
other connection paths:
- a path that connects rotator block to the DDR.
- a path that needs to be h
On 28.09.2023 13:16, Dmitry Baryshkov wrote:
> Add support for HDMI PHY on Qualcomm MSM8974 / APQ8074 platforms.
>
> Signed-off-by: Dmitry Baryshkov
> ---
I only have a few style comments (and timers-howto.txt fixes)
[...]
> +#define HDMI_8974_VCO_MAX_FREQ 18UL
> +#define
On 28.09.2023 13:16, Dmitry Baryshkov wrote:
> Add support for HDMI PHY on Qualcomm MSM8x60 / APQ8060 platforms.
>
> Signed-off-by: Dmitry Baryshkov
> ---
Do you have the PLL working locally? Would it make sense to ship them both?
Konrad
On 10/23/23 21:42, Rob Clark wrote:
On Mon, Oct 23, 2023 at 7:29 AM Konrad Dybcio wrote:
New GPUs still use the lower 2 bytes of the chip id (in whatever form
it comes) to signify silicon revision. Drop the warning that makes it
sound as if that was unintended.
Fixes: 90b593ce1c9e (&quo
On 10/7/23 01:43, Konrad Dybcio wrote:
On 4.10.2023 02:31, Dmitry Baryshkov wrote:
clk_rcg2_shared_ops implements support for the case of the RCG which
must not be completely turned off. However its design has one major
drawback: it doesn't allow us to properly implement the is_enabled
On 9/28/23 13:16, Dmitry Baryshkov wrote:
With the extp being the only "power" clock left, remove the surrounding
loops and handle the extp clock directly.
Signed-off-by: Dmitry Baryshkov
---Reviewed-by: Konrad Dybcio
Konrad
On 9/28/23 13:16, Dmitry Baryshkov wrote:
Signed-off-by: Dmitry Baryshkov
---
Reviewed-by: Konrad Dybcio
Konrad
On 9/28/23 13:16, Dmitry Baryshkov wrote:
In preparation to converting MSM HDMI driver to use PHY framework, which
requires phy_power_on() calls to be paired with phy_power_off(), add a
conditional call to msm_hdmi_phy_powerdown() before the call to
msm_hdmi_phy_powerup().
Signed-off-by:
On 10/23/23 22:20, Rob Clark wrote:
On Mon, Oct 23, 2023 at 12:56 PM Konrad Dybcio wrote:
On 10/23/23 21:42, Rob Clark wrote:
On Mon, Oct 23, 2023 at 7:29 AM Konrad Dybcio wrote:
New GPUs still use the lower 2 bytes of the chip id (in whatever form
it comes) to signify silicon
On 9/28/23 13:16, Dmitry Baryshkov wrote:
In preparation of reworking the HDMI mode setting, switch pre_enable and
post_disable callbacks to their atomic variants.
Signed-off-by: Dmitry Baryshkov
---
This looks good, but I'm far from knowledgeable in terms of drm, so:
Acked-by: Konrad
On 10/26/23 22:47, Dmitry Baryshkov wrote:
On Thu, 26 Oct 2023 at 21:57, Konrad Dybcio wrote:
On 10/7/23 01:43, Konrad Dybcio wrote:
On 4.10.2023 02:31, Dmitry Baryshkov wrote:
clk_rcg2_shared_ops implements support for the case of the RCG which
must not be completely turned off
-by: Konrad Dybcio
Konrad
On 9/28/23 13:16, Dmitry Baryshkov wrote:
Drop source files used by old HDMI PHY and HDMI PLL drivers.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi_phy.c | 216 ---
drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c | 51 --
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
On 9/28/23 13:16, Dmitry Baryshkov wrote:
Port Qualcomm QMP HDMI PHY to the generic PHY framework. Split the
generic part and the msm8996 part. When adding support for msm8992/4 and
msm8998 (which also employ QMP for HDMI PHY), one will have to provide
the PLL programming part only.
On 10/26/23 23:03, Dmitry Baryshkov wrote:
On Fri, 27 Oct 2023 at 00:00, Konrad Dybcio wrote:
On 9/28/23 13:16, Dmitry Baryshkov wrote:
Drop source files used by old HDMI PHY and HDMI PLL drivers.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi_phy.c | 216
Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 96 +--
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 451
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 1 +
drivers/gpu/drm
MESA_LOADER_DRIVER_OVERRIDE=zink kmscube
[1]
https://lore.kernel.org/linux-arm-msm/20230517-topic-a7xx_prep-v4-0-b16f273a9...@linaro.org/
[2] https://github.com/SoMainline/linux/commits/topic/a7xx_dt
[3] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217
Signed-off-by: Konrad Dybcio
Reviewed-by: Krzysztof Kozlowski
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
.../devicetree/bindings/display/msm/gmu.yaml | 40 +-
1 file changed, 39 insertions(+), 1 deletion(-)
diff --git a/Documentation/
-by: Krzysztof Kozlowski
Signed-off-by: Konrad Dybcio
---
Documentation/devicetree/bindings/display/msm/gmu.yaml | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml
b/Documentation/devicetree/bindings/display/msm/gmu.yaml
index 428eb138881a
Allow A7xx SKUs, such as the A730 GPU found on SM8450 and friends.
They use GMU for all things DVFS, just like most A6xx GPUs.
Reviewed-by: Krzysztof Kozlowski
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
Documentation
Add some missing definitions required for A7 support.
This may be substituted with a mesa header sync.
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 9 +
drivers/gpu/drm/msm
QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 15 +++
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 3 +++
2 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
b/drivers/gpu/drm/
Provide the necessary alternations to mostly support state dumping on
A7xx. Newer GPUs will probably require more changes here. Crashdumper
and debugbus remain untested.
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu
Add support for Adreno 730, also known as GEN7_0_x, found on SM8450.
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 126 -
drivers/gpu/drm/msm/adreno
# on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 88 +-
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 82 +---
drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 27
that can't receive data on its end of the bus.
Failing to do this will result in inexplicable GMU timeouts or worse.
This is a rather ugly hack which introduces a whole lot of latency.
Tested-by: Neil Armstrong # on SM8550-QRD
Tested-by: Dmitry Baryshkov # sm8450
Signed-off-by: Konrad Dybcio
On 26.09.2023 01:26, Richard Acayan wrote:
> The Snapdragon 670 uses similar clocks (with one frequency added) to the
> Snapdragon 845 but reports DPU revision 4.1. Add support for this DPU
> with configuration from the Pixel 3a downstream kernel.
>
> Since revision 4.0 is SDM845, reuse some
Commit e550ad0e5c3d ("drm/msm/dpu: fix DSC 1.2 block lengths") changed
the block length from a wrong value to another wrong value.
Use the correct one this time.
Fixes: e550ad0e5c3d ("drm/msm/dpu: fix DSC 1.2 block lengths")
Signed-off-by: Konrad Dybcio
---
drivers/g
Found a couple mistakes, this series attempts to fix it.
Signed-off-by: Konrad Dybcio
---
Konrad Dybcio (3):
drm/msm/dpu: Fix SC7280 PP length
drm/msm/dpu: Add missing DPU_DSC_OUTPUT_CTRL to SC7280
drm/msm/dpu: Fix SC7280 DSC block length
drivers/gpu/drm/msm/disp/dpu1/catalog
DPU_DSC_OUTPUT_CTRL should be enabled for all platforms with a CTL
CFG 1.0.0. SC7280 is one of them. Add it.
Fixes: 0d1b10c63346 ("drm/msm/dpu: add DSC 1.2 hw blocks for relevant chipsets")
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2
Commit 194347df5844 ("drm/msm/dpu: inline DSC_BLK and DSC_BLK_1_2
macros") unrolled a macro incorrectly. Fix that.
Fixes: 194347df5844 ("drm/msm/dpu: inline DSC_BLK and DSC_BLK_1_2 macros")
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc72
On 9/21/23 01:41, Abhinav Kumar wrote:
On 9/20/2023 3:46 PM, Konrad Dybcio wrote:
Commit 194347df5844 ("drm/msm/dpu: inline DSC_BLK and DSC_BLK_1_2
macros") unrolled a macro incorrectly. Fix that.
No, its correct from what i can tell.
Before inlining it was using PP_BLK_DI
On 9/21/23 02:01, Abhinav Kumar wrote:
On 9/20/2023 3:46 PM, Konrad Dybcio wrote:
DPU_DSC_OUTPUT_CTRL should be enabled for all platforms with a CTL
CFG 1.0.0. SC7280 is one of them. Add it.
sc7280 and all other chipsets using DSC 1.2 use dpu_hw_dsc_init_1_2 and
not dpu_hw_dsc_init
as it says on the can
drm/msm patches for Rob
arm64 patches for linux-arm-msm
for use with https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25408
tested on QCM6490 (SC7280-IOT) Fairphone FP5
Signed-off-by: Konrad Dybcio
---
Konrad Dybcio (7):
drm/msm/a6xx: Fix unknown speedbin
Some (many?) devices with A635 expect a ZAP shader to be loaded.
Set the file name to allow for that.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c
b/drivers/gpu/drm
Downstream calls this the "speedbin 1", but that number is already
occupied. Use index two.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c
b/drivers/gpu/drm/
Non-Chrome SC7280-family platforms ship a ZAP shader with the Adreno GPU.
Describe that and make sure it doesn't interfere with Chrome devices.
Signed-off-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi | 2 ++
arch/arm64/boot/dts/qcom/sc7280.dtsi | 10
tly always bound to fuseval == 0).
Fixes: c928a05e4415 ("drm/msm/adreno: Move speedbin mapping to device table")
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.
.
Fixes: 96c471970b7b ("arm64: dts: qcom: sc7280: Add gpu support")
Signed-off-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.
The SMMUs on sc7280 are cache-coherent. APPS_SMMU is marked as such,
mark the GPU one as well.
Signed-off-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
A643 (A635 speedbin 0xac) tops out at 812 MHz. Fill in the
opp-supported-hw appropriately.
Note that fuseval 0xac is referred to as speedbin 1 downstream, but
that was already in use upstream, so 2 was chosen instead.
Signed-off-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 12
On 26.09.2023 19:42, Danila Tikhonov wrote:
> SM7150 has 5 power levels which correspond to 5 speed-bin values: 0,
> 128, 146, 167, 172. Speed-bin value is calulated as FMAX/4.8MHz round up
> to zero decimal places.
>
> Also a618 on SM7150 uses a615 zapfw. Add a squashed version (.mbn).
>
> Add
On 26.09.2023 21:10, Danila Tikhonov wrote:
>
> I think you mean by name downstream dt - sdmmagpie-gpu.dtsi
>
> You can see the forked version of the mainline here:
> https://github.com/sm7150-mainline/linux/blob/next/arch/arm64/boot/dts/qcom/sm7150.dtsi
>
> All fdt that we got here, if it is
On 26.09.2023 20:24, Konrad Dybcio wrote:
> The SMMUs on sc7280 are cache-coherent. APPS_SMMU is marked as such,
> mark the GPU one as well.
>
> Signed-off-by: Konrad Dybcio
> ---
Fixes: 96c471970b7b ("arm64: dts: qcom: sc7280: Add gpu support")
Sorry.
Konrad
On 26.09.2023 20:24, Konrad Dybcio wrote:
> Non-Chrome SC7280-family platforms ship a ZAP shader with the Adreno GPU.
> Describe that and make sure it doesn't interfere with Chrome devices.
>
> Signed-off-by: Konrad Dybcio
> ---
> arch/arm64/boot/dts/qcom/sc7280-chrom
On 28.09.2023 13:16, Dmitry Baryshkov wrote:
> From: Sandor Yu
>
> Allow HDMI PHYs to be configured through the generic
> functions through a custom structure added to the generic union.
>
> The parameters added here are based on HDMI PHY
> implementation practices. The current set of
On 10/12/23 11:10, Dan Carpenter wrote:
Hello Konrad Dybcio,
The patch 88a0997f2f94: "drm/msm/a6xx: Send ACD state to QMP at GMU
resume" from Sep 25, 2023 (linux-next), leads to the following Smatch
static checker warning:
Thanks for the heads up, Dan!
Can you give my belo
On 4.10.2023 14:52, Bryan O'Donoghue wrote:
> On 04/10/2023 13:08, Dmitry Baryshkov wrote:
>> On Wed, 4 Oct 2023 at 12:27, Bryan O'Donoghue
>> wrote:
>>>
>>> On 04/10/2023 01:31, Dmitry Baryshkov wrote:
clk_rcg2_shared_ops implements support for the case of the RCG which
must not be
On 4.10.2023 02:31, Dmitry Baryshkov wrote:
> clk_rcg2_shared_ops implements support for the case of the RCG which
> must not be completely turned off. However its design has one major
> drawback: it doesn't allow us to properly implement the is_enabled
> callback, which causes different kinds of
On 10/16/23 22:22, Akhil P Oommen wrote:
On Tue, Sep 26, 2023 at 08:24:40PM +0200, Konrad Dybcio wrote:
GPU_SMMU SID 1 is meant for Adreno LPAC (Low Priority Async Compute).
On platforms that support it (in firmware), it is necessary to
describe that link, or Adreno register access
On 10/10/23 01:33, Richard Acayan wrote:
The Snapdragon 670 has a display subsystem for controlling and
outputting to the display. Add support for it in the device tree.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Richard Acayan
---
[...]
+ interconnects = <_noc
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