On 11/15/2018 12:33 AM, Koenig, Christian wrote:
Am 14.11.18 um 18:29 schrieb Sharat Masetty:
On 11/8/2018 8:11 PM, Koenig, Christian wrote:
Am 08.11.18 um 14:42 schrieb Sharat Masetty:
Hi Christian,
Can you please review this patch? It is a continuation of the
discussion at [1].
At
The current implementation of ascii85_encode() does not copy the encoded
buffer 'z' to the output buffer in case the input is zero. This patch
simply adds this missing piece. This makes it easier to use this
function to encode large buffers.
Signed-off-by: Sharat Masetty
---
inc
The ring substructure in msm_gpu_state is an extension of
msm_gpu_state_bo, so this patch changes the ring structure
to reuse the msm_gpu_state_bo as a base class, instead of
redefining the required variables.
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 20
The ringbuffer data to capture at crashtime can end up being large
sometimes, and the size can vary from being less than a page to the
full size of 32KB. So use the kvmalloc variant that perfectly fits the bill.
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 4
depends on the size of the data captured by the
driver. This is certainly not desirable and does not scale well with
large captures.
This patch encodes the buffer only once in the read path. With this there
is an immediate >10X speed improvement in crashstate save time.
Signed-off-by: Sharat Mase
In cases where the scheduler instance is used as a base object of another
driver object, it's not clear if the driver can call scheduler cleanup on the
fail path. So, Set the sched->thread to NULL, so that the driver can safely
call drm_sched_fini() during cleanup.
Signed-off-by: Sharat
patch also makes the job_list_lock IRQ safe.
Suggested-by: Christian Koenig
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/etnaviv/etnaviv_dump.c | 9 ++--
drivers/gpu/drm/scheduler/sched_main.c | 91 --
include/drm/gpu_scheduler.h| 4 ++
3 files
We are not really checking the state of the adreno_gpu_state_get()
function at the callers and in addition the state capture is mostly a
best effort service, so make the function return void.
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 4 +---
drivers/gpu/drm/msm
The gpu crashstate's base objects registers pointer can be NULL if the
target implementation decides to capture the register dump on its own.
This patch simply checks for NULL before dereferencing.
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 15 ++---
The gpu crashstate's base objects registers pointer can be NULL if the
target implementation decides to capture the register dump on its own.
This patch simply checks for NULL before dereferencing.
Signed-off-by: Sharat Masetty
---
Changes from v1:
Addressed comments from Jordan C
We are not really checking the state of the adreno_gpu_state_get()
function at the callers and in addition the state capture is mostly a
best effort service, so make the function return void.
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 4 +---
drivers/gpu/drm/msm
Build the GPU crashstate capture functions only if either of
CONFIG_DEBUG_FS, CONFIG_DEV_COREDUMP is defined.
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
Fix the cx debugbus related register configuration, to collect accurate
bus data during gpu snapshot. This helps with complete snapshot dump
and also complete proper GPU recovery.
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 24
1 file
Add GBIF register definitions required to implement a618
GPU revision
Signed-off-by: Sharat Masetty
---
rnndb/adreno/a6xx.xml | 26 ++
1 file changed, 26 insertions(+)
diff --git a/rnndb/adreno/a6xx.xml b/rnndb/adreno/a6xx.xml
index 747f071..2d2063a 100644
--- a/rnndb
Fix the cx debugbus related register configuration, to collect accurate
bus data during gpu snapshot. This helps with complete snapshot dump
and also complete proper GPU recovery.
Change-Id: I4f0ae3eb2dd5d24a88d805277fad212dda2d735e
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/adreno
: Sharat Masetty
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 52 +++-
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 24 +--
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 70 ++---
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 9 -
drivers/gpu/drm
This series and support to enable A618 GPU revision. Please review.
Sharat Masetty (5):
drm: msm: Add 618 gpu to the adreno gpu list
drm: msm: a6xx: Add support for A618
drm: msm: a6xx: Dump GBIF registers, debugbus in gpu state
drm: msm: a6xx: fix debug bus register configuration
arm
This patch adds Adreno 618 entry and its associated properties
to the gpulist entries.
Change-Id: Ie14ba09f32513ba6a6c882fda0d98ee1742b46d5
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu
This patch adds the required dt nodes and properties
to enabled A618 GPU.
Change-Id: I7491c4de654c4b84d03dbcf703532448b27d4147
Signed-off-by: Sharat Masetty
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 116 +++
1 file changed, 116 insertions(+)
diff --git a/arch
This patch adds the required dt nodes and properties
to enabled A618 GPU.
Signed-off-by: Sharat Masetty
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 116 +++
1 file changed, 116 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts
Add the relevant GBIF registers and the debug bus to the a6xx gpu
state. This comes in pretty handy when debugging GPU bus related
issues.
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 52 +++--
drivers/gpu/drm/msm/adreno
Add the relevant GBIF registers and the debug bus to the a6xx gpu
state. This comes in pretty handy when debugging GPU bus related
issues.
Change-Id: I224fda727012a456ccd28ca14caf9fcce236e629
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 52
This patch adds the required dt nodes and properties
to enabled A618 GPU.
Signed-off-by: Sharat Masetty
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 116 +++
1 file changed, 116 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts
This patch adds support for A618 GPU. Please review.
Sharat Masetty (5):
drm: msm: Add 618 gpu to the adreno gpu list
drm: msm: a6xx: Add support for A618
drm: msm: a6xx: Dump GBIF registers, debugbus in gpu state
drm: msm: a6xx: fix debug bus register configuration
arm: dts: sc7180
Fix the cx debugbus related register configuration, to collect accurate
bus data during gpu snapshot. This helps with complete snapshot dump
and also complete proper GPU recovery.
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 24
1 file
This patch adds Adreno 618 entry and its associated properties
to the gpulist entries.
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c
b/drivers/gpu/drm/msm
This patch adds support for enabling Graphics Bus Interface(GBIF)
used in multiple A6xx series chipets. Also makes changes to the
PDC/RSC sequencing specifically required for A618. This is needed
for proper interfacing with RPMH.
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/adreno
From: Jordan Crouse
Pass the propposed io_pgtable_cfg to the implementation specific
init_context() function to give the implementation an opportunity to
to modify it before it gets passed to io-pgtable.
Signed-off-by: Jordan Crouse
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm-smmu
io_pgtable_cfg to impl specific init_context
Sharat Masetty (3):
drm/msm: rearrange the gpu_rmw() function
drm/msm: Pass mmu features to generic layers
drm/msm/a6xx: Add support for using system cache(LLC)
Vivek Gautam (1):
iommu/arm-smmu: Add domain attribute for QCOM system cache
drivers/gpu/drm
supports.
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 2 +-
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 2 +-
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 2 +-
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 +-
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
drivers/gpu
The register read-modify-write construct is generic enough
that it can be used by other subsystems as needed, create
a more generic rmw() function and have the gpu_rmw() use
this new function.
Signed-off-by: Sharat Masetty
Reviewed-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.c | 8
From: Vivek Gautam
Add iommu domain attribute for using system cache aka last level
cache on QCOM SoCs by client drivers like GPU to set right
attributes for caching the hardware pagetables into the system cache.
Signed-off-by: Vivek Gautam
Co-developed-by: Sai Prakash Ranjan
Signed-off-by: Sa
larly DOMAIN_ATTR_QCOM_SYS_CACHE is another domain level attribute
used by the IOMMU driver to set the right attributes to cache the hardware
pagetables into the system cache.
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 122 +-
drivers/gpu/dr
From: Jordan Crouse
Pass the propposed io_pgtable_cfg to the implementation specific
init_context() function to give the implementation an opportunity to
to modify it before it gets passed to io-pgtable.
Signed-off-by: Jordan Crouse
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm-smmu
l.org/patchwork/patch/1165298/
Jordan Crouse (3):
iommu/arm-smmu: Pass io_pgtable_cfg to impl specific init_context
drm/msm: Attach the IOMMU device during initialization
drm/msm: Refactor address space initialization
Sharat Masetty (3):
drm: msm: a6xx: Properly free up the iommu objects
dr
From: Vivek Gautam
Add iommu domain attribute for using system cache aka last level
cache on QCOM SoCs by client drivers like GPU to set right
attributes for caching the hardware pagetables into the system cache.
Signed-off-by: Vivek Gautam
Co-developed-by: Sai Prakash Ranjan
Signed-off-by: Sa
The register read-modify-write construct is generic enough
that it can be used by other subsystems as needed, create
a more generic rmw() function and have the gpu_rmw() use
this new function.
Signed-off-by: Sharat Masetty
Reviewed-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.c | 8
initialization to
allow for future extensions like supporting split pagetables.
Signed-off-by: Jordan Crouse
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/adreno/a2xx_gpu.c| 16 ++
drivers/gpu/drm/msm/adreno/a3xx_gpu.c| 1 +
drivers/gpu/drm/msm/adreno/a4xx_gpu.c| 1
This patch calls the right function to destroy the iommu domain as well
as free the associated iommu structure there by facilitating proper
clean up of resources upon failure of creating an address space.
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
1 file
larly DOMAIN_ATTR_QCOM_SYS_CACHE is another domain level attribute
used by the IOMMU driver to set the right attributes to cache the hardware
pagetables into the system cache.
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 100 ++
drivers/gpu/dr
From: Jordan Crouse
Everywhere an IOMMU object is created by msm_gpu_create_address_space
the IOMMU device is attached immediately after. Instead of carrying around
the infrastructure to do the attach from the device specific code do it
directly in the msm_iommu_init() function. This gets it out
Add the relevant GBIF registers and the debug bus to the a6xx gpu
state. This comes in pretty handy when debugging GPU bus related
issues.
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 52 +++--
drivers/gpu/drm/msm/adreno
This patch adds support for enabling Graphics Bus Interface(GBIF)
used in multiple A6xx series chipets. Also makes changes to the
PDC/RSC sequencing specifically required for A618. This is needed
for proper interfacing with RPMH.
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/adreno
This patch adds Adreno 618 entry and its associated properties
to the gpulist entries.
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c
b/drivers/gpu/drm/msm
This patch adds the required dt nodes and properties
to enabled A618 GPU.
Signed-off-by: Sharat Masetty
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 103 +++
1 file changed, 103 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts
This patch adds the required dt nodes and properties
to enabled A618 GPU.
Signed-off-by: Sharat Masetty
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 102 +++
1 file changed, 102 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts
a new patch with its
dependencies listed. Also I will be sending a new patch for updating the
bindings documentation.
Sharat Masetty (1):
arm64: dts: qcom: sc7180: Add A618 gpu dt blob
arch/arm64/boot/dts/qcom/sc7180.dtsi | 102 +++
1 file ch
This patch adds the required dt nodes and properties
to enabled A618 GPU.
Signed-off-by: Sharat Masetty
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 102 +++
1 file changed, 102 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts
a new patch with its
dependencies listed. Also I will be sending a new patch for updating the
bindings documentation.
v4: Add GX_GDSC power domain binding for GMU
Sharat Masetty (1):
arm64: dts: qcom: sc7180: Add A618 gpu dt blob
Taniya Das (2):
dt-bindings: clk: qcom: Add support for GP
From: Taniya Das
In the cases where the GPU SW requires to use the GX GDSCR add
support for the same.
Signed-off-by: Taniya Das
---
include/dt-bindings/clock/qcom,gpucc-sc7180.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/clock/qcom,gpucc-sc7180.h
From: Taniya Das
Most of the time the CPU should not be touching the GX domain on the
GPU
except for a very special use case when the CPU needs to force the GX
headswitch off. Add a dummy enable function for the GX gdsc to simulate
success so that the pm_runtime reference counting is correct
a new patch with its
dependencies listed. Also I will be sending a new patch for updating the
bindings documentation.
v4: Add GX_GDSC power domain binding for GMU
v5: Change to a dummy GX_GDSC binding for faster landing
Sharat Masetty (1):
arm64: dts: qcom: sc7180: Add A618 gpu dt blob
ar
This patch adds the required dt nodes and properties
to enabled A618 GPU.
Signed-off-by: Sharat Masetty
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 102 +++
1 file changed, 102 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts
This patch adds the required dt nodes and properties
to enabled A618 GPU.
Signed-off-by: Sharat Masetty
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 102 +++
1 file changed, 102 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts
Rebased changes on top of Taniyas lastet post((e) in the list above) and
adding back the GX_GDSC binding.
Sharat Masetty (1):
arm64: dts: qcom: sc7180: Add A618 gpu dt blob
arch/arm64/boot/dts/qcom/sc7180.dtsi | 102 +++
1 file ch
This patch adds a clock definition needed for powering on the GPU TBUs
and the GPU TCU.
Signed-off-by: Sharat Masetty
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
b
Patch [1] adds a "mem_iface_clock" in the clocks list for smmu device.
This patch updates the yaml doc file for smmu by adding the definition
for this new clock.
1: https://patchwork.freedesktop.org/patch/352718/
Sharat Masetty (1):
dt-bindings: arm-smmu: update clocks and bindings
On 2/11/2020 2:51 AM, Doug Anderson wrote:
Hi,
On Sun, Feb 9, 2020 at 11:41 PM Sharat Masetty wrote:
This patch adds the required dt nodes and properties
to enabled A618 GPU.
Signed-off-by: Sharat Masetty
In v4 I added my tags [1]. Please keep them for future patches unless
something
On 2/21/2020 2:05 AM, Rob Herring wrote:
On Thu, 20 Feb 2020 13:42:22 +0530, Sharat Masetty wrote:
This patch adds a clock definition needed for powering on the GPU TBUs
and the GPU TCU.
Signed-off-by: Sharat Masetty
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 +++
1
On 2/26/2020 8:03 PM, Rob Herring wrote:
On Wed, Feb 26, 2020 at 5:17 AM Sharat Masetty wrote:
On 2/21/2020 2:05 AM, Rob Herring wrote:
On Thu, 20 Feb 2020 13:42:22 +0530, Sharat Masetty wrote:
This patch adds a clock definition needed for powering on the GPU TBUs
and the GPU TCU.
Signed
This patch disables interrupts in the GPU RBBM hang detect fault handler
before going to recovery.
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno
iumos/third_party/kernel/+/2097039/3
Sharat Masetty (5):
arm64: dts: qcom: sc7180: Add interconnect bindings for GPU
arm64: dts: qcom: sc7180: Add GPU DDR BW opp table
drm: msm: scale DDR BW along with GPU frequency
drm: msm: a6xx: Fix off by one error when setting GPU freq
dt-bindings: drm/ms
This patch adds support to parse the OPP tables attached the GPU device,
the main opp table and the DDR bandwidth opp table. Additionally, vote
for the GPU->DDR bandwidth when setting the GPU frequency by querying
the linked DDR BW opp to the GPU opp.
Signed-off-by: Sharat Masetty
---
driv
This patch adds the interconnect bindings to the GPU node. This enables
the GPU->DDR path bandwidth voting.
Signed-off-by: Sharat Masetty
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/
frequency.
Signed-off-by: Sharat Masetty
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 50 +++-
1 file changed, 49 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 51630dd..74b023b 100644
Update the documentation for listing the multiple optional GPU and the
DDR OPP tables to help enable DDR scaling.
Signed-off-by: Sharat Masetty
---
.../devicetree/bindings/display/msm/gpu.txt| 63 +-
1 file changed, 61 insertions(+), 2 deletions(-)
diff --git a
This patch fixes an error in the for loop, thereby allowing search on
the full list of possible GPU power levels.
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
b
On 3/31/2020 10:56 PM, Jordan Crouse wrote:
On Tue, Mar 31, 2020 at 01:25:51PM +0530, Sharat Masetty wrote:
This patch adds support to parse the OPP tables attached the GPU device,
the main opp table and the DDR bandwidth opp table. Additionally, vote
for the GPU->DDR bandwidth when sett
This patch adds a new compatible string for sc7180 and also an
additional clock listing needed to power the TBUs and the TCU.
Signed-off-by: Sharat Masetty
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation
On 4/29/2020 3:57 AM, Doug Anderson wrote:
Hi,
On Tue, Apr 28, 2020 at 4:39 AM Sharat Masetty wrote:
This patch adds a new compatible string for sc7180 and also an
additional clock listing needed to power the TBUs and the TCU.
Signed-off-by: Sharat Masetty
---
Documentation/devicetree
This patch adds a new compatible string for sc7180 and also an
additional clock listing needed to power the TBUs and the TCU.
Signed-off-by: Sharat Masetty
---
v2: Addressed review comments from Doug
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 8
1 file changed, 8
On 4/30/2020 11:51 PM, Doug Anderson wrote:
Hi,
On Thu, Apr 30, 2020 at 11:12 AM Jordan Crouse wrote:
On Thu, Apr 30, 2020 at 09:29:47AM +0530, Sharat Masetty wrote:
This patch adds a new compatible string for sc7180 and also an
additional clock listing needed to power the TBUs and the TCU
This patch adds the required dt nodes and properties
to enabled A618 GPU.
Signed-off-by: Sharat Masetty
---
* Remove GCC_DDRSS_GPU_AXI_CLK clock reference from gpu smmu node.
arch/arm64/boot/dts/qcom/sc7180.dtsi | 102 +++
1 file changed, 102 insertions(+)
diff
This patch simply adds a new compatible string for SC7180 platform.
Signed-off-by: Sharat Masetty
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
b/Documentation/devicetree
From: Sibi Sankar
Add and export 'dev_pm_opp_set_bw' to set the bandwidth
levels associated with an OPP for a given frequency.
Signed-off-by: Sibi Sankar
Signed-off-by: Sharat Masetty
---
drivers/opp/core.c | 43 +++
include/linux/pm_
This patch changes the plumbing to send the devfreq recommended opp rather
than the frequency. Also consolidate and rearrange the code in a6xx to set
the GPU frequency and the icc vote in preparation for the upcoming
changes for GPU->DDR scaling votes.
Signed-off-by: Sharat Masetty
---
driv
This patches replaces the previously used static DDR vote and uses
dev_pm_opp_set_bw() to scale GPU->DDR bandwidth along with scaling
GPU frequency.
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --gi
Add opp-peak-kBps bindings to the GPU opp table, listing the peak
GPU -> DDR bandwidth requirement for each opp level. This will be
used to scale the DDR bandwidth along with the GPU frequency dynamically.
Signed-off-by: Sharat Masetty
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 7 +++
This patch adds the interconnect bindings to the GPU node. This enables
the GPU->DDR path bandwidth voting.
Signed-off-by: Sharat Masetty
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/
hwork/cover/1230626/
[3]: https://lore.kernel.org/patchwork/cover/1240687/
Sharat Masetty (5):
arm64: dts: qcom: sc7180: Add interconnect bindings for GPU
arm64: dts: qcom: sc7180: Add opp-peak-kBps to GPU opp
drm: msm: a6xx: send opp instead of a frequency
drm: msm: a6xx: use dev_pm_opp_set_
Update documentation to list the gpu opp table bindings including the
newly added "opp-peak-kBps" needed for GPU-DDR bandwidth scaling.
Signed-off-by: Sharat Masetty
---
.../devicetree/bindings/display/msm/gpu.txt| 28 ++
1 file changed, 28 insertions(+)
+ more folks
On 5/18/2020 9:55 PM, Rob Clark wrote:
On Mon, May 18, 2020 at 7:23 AM Jordan Crouse wrote:
On Thu, May 14, 2020 at 04:24:18PM +0530, Sharat Masetty wrote:
This patches replaces the previously used static DDR vote and uses
dev_pm_opp_set_bw() to scale GPU->DDR bandwidth al
On 5/27/2020 9:08 PM, Rob Clark wrote:
On Wed, May 27, 2020 at 1:47 AM Sharat Masetty wrote:
+ more folks
On 5/18/2020 9:55 PM, Rob Clark wrote:
On Mon, May 18, 2020 at 7:23 AM Jordan Crouse wrote:
On Thu, May 14, 2020 at 04:24:18PM +0530, Sharat Masetty wrote:
This patches replaces the
t for SDM845 as well
but its not tested yet(WIP), but the SC7180 patches are well tested now.
[1] https://patchwork.freedesktop.org/series/75291/
[2]
https://kernel.googlesource.com/pub/scm/linux/kernel/git/vireshk/pm/+log/opp/linux-next/
[3] https://patchwork.kernel.org/patch/11590563/
Sharat Ma
-by: Sharat Masetty
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 23 ---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 8
drivers/gpu/drm/msm/msm_gpu.h | 2 --
3 files changed, 16 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
This patch changes the plumbing to send the devfreq recommended opp rather
than the frequency. Also consolidate and rearrange the code in a6xx to set
the GPU frequency and the icc vote in preparation for the upcoming
changes for GPU->DDR scaling votes.
Signed-off-by: Sharat Masetty
---
driv
This patch adds the interconnects property to the GPU node. This enables
the GPU->DDR path bandwidth voting.
Signed-off-by: Sharat Masetty
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/
Update documentation to list the gpu opp table bindings including the
newly added "opp-peak-kBps" needed for GPU-DDR bandwidth scaling.
Signed-off-by: Sharat Masetty
Acked-by: Rob Herring
---
.../devicetree/bindings/display/msm/gpu.txt| 28 ++
1 file c
Add opp-peak-kBps bindings to the GPU opp table, listing the peak
GPU -> DDR bandwidth requirement for each opp level. This will be
used to scale the DDR bandwidth along with the GPU frequency dynamically.
Signed-off-by: Sharat Masetty
Reviewed-by: Matthias Kaehlcke
---
arch/arm64/boot/
This patch adds the interconnects property for the gpu node and the
opp-peak-kBps property to the opps of the gpu opp table. This should
help enable DDR bandwidth scaling dynamically and proportionally to the
GPU frequency.
Signed-off-by: Sharat Masetty
---
arch/arm64/boot/dts/qcom/sdm845.dtsi
This patch fixes a possible memory leak in get_pages()
Prakash Kamliya (1):
drm/msm: fix leak in failed get_pages
drivers/gpu/drm/msm/msm_gem.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
--
1.9.1
___
Freedreno mailing lis
akash Kamliya
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/msm_gem.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
index 0776160..cb3d58d 100644
--- a/drivers/gpu/drm/msm/msm_gem.c
+++ b/dr
akash Kamliya
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/msm_gem.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
index 0776160..cb3d58d 100644
--- a/drivers/gpu/drm/msm/msm_gem.c
+++ b/dr
This patch fixes a possible memory leak in get_pages()
Prakash Kamliya (1):
drm/msm: fix leak in failed get_pages
drivers/gpu/drm/msm/msm_gem.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
--
1.9.1
___
Freedreno mailing lis
-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
index fb605a3..f0fd80e 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
vels, each with
different granularities and different switch-out--switch-in times. While this
patch only enables the first preemption level i.e. preemption at the ringbuffer
level, support for more finer grained preemption levels will follow after
more testing.
Sharat Masetty (4):
drm/msm: Add submit
This patch simply increases the number of available ringbuffers,
therefore enabling preemption.
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm
This patch adds a bit of infrastructure to give the different Adreno
targets the flexibility to setup the submitqueues per their needs.
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/msm_gpu.h | 7 +++
drivers/gpu/drm/msm/msm_submitqueue.c | 15 +--
2 files
-call level or a bin boundary level preemption. This patch
enables the basic preemption level, with more fine grained preemption
support to follow.
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 44
drivers/gpu
Add CP_SECURE_MODE and CP_SET_PSEUDO_REG opcodes needed for A6xx
hardware features.
Signed-off-by: Sharat Masetty
---
rnndb/adreno/adreno_pm4.xml | 5 +
1 file changed, 5 insertions(+)
diff --git a/rnndb/adreno/adreno_pm4.xml b/rnndb/adreno/adreno_pm4.xml
index 3621f07..c1a82da 100644
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