Re: [Freedreno] [PATCH 1/2] iommu/arm-smmu-qcom: Skip the TTBR1 quirk for db820c.

On Mon, Mar 29, 2021 at 7:47 AM Will Deacon wrote: > > On Fri, Mar 26, 2021 at 04:13:02PM -0700, Eric Anholt wrote: > > db820c wants to use the qcom smmu path to get HUPCF set (which keeps > > the GPU from wedging and then sometimes wedging the kernel after a > > page fau

[Freedreno] [PATCH 2/2] arm64: dts: msm8996: Mark the GPU's SMMU as an adreno one.

This enables the adreno-specific SMMU path that sets HUPCF so (user-managed) page faults don't wedge the GPU. Signed-off-by: Eric Anholt --- We've been seeing a flaky test per day or so in Mesa CI where the kernel gets wedged after an iommu fault turns into CP errors. With this patch, the CI

[Freedreno] [PATCH 1/2] iommu/arm-smmu-qcom: Skip the TTBR1 quirk for db820c.

db820c wants to use the qcom smmu path to get HUPCF set (which keeps the GPU from wedging and then sometimes wedging the kernel after a page fault), but it doesn't have separate pagetables support yet in drm/msm so we can't go all the way to the TTBR1 path. Signed-off-by: Eric Anholt --- We've

Re: [Freedreno] [PATCH] drm/msm: fix a6xx_gmu_clear_oob

Clean up GMU OOB set/clear handling") > > Signed-off-by: Jonathan Marek > > Thanks. I feel silly that I missed that. > > Reviewed-by: Jordan Crouse Yeah, oops. Reviewed-by: Eric Anholt ___ Freedreno mailing list Freedreno@l

[Freedreno] [PATCH v3 3/3] drm/msm: Clean up GMU OOB set/clear handling.

Now that the bug is fixed in the minimal way for stable, go make the code table-driven. Signed-off-by: Eric Anholt Reviewed-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 124 +- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 55 2 files changed

[Freedreno] [PATCH v3 1/3] drm/msm: Fix race of GPU init vs timestamp power management.

to it. Signed-off-by: Eric Anholt Fixes: 4b565ca5a2cb ("drm/msm: Add A6XX device support") Reviewed-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 25 ++--- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 8 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 ++-

[Freedreno] [PATCH v3 0/3] drm/msm: fix for "Timeout waiting for GMU OOB set GPU_SET: 0x0"

Updated commit messages over v2, no code changes. Eric Anholt (3): drm/msm: Fix race of GPU init vs timestamp power management. drm/msm: Fix races managing the OOB state for timestamp vs timestamps. drm/msm: Clean up GMU OOB set/clear handling. drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 105

[Freedreno] [PATCH v3 2/3] drm/msm: Fix races managing the OOB state for timestamp vs timestamps.

, the message seems to have completely gone away. Signed-off-by: Eric Anholt Fixes: 4b565ca5a2cb ("drm/msm: Add A6XX device support") Reviewed-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6x

Re: [Freedreno] [PATCH 1/3] drm/msm: Fix race of GPU init vs timestamp power management.

On Thu, Jan 28, 2021 at 10:52 AM Jordan Crouse wrote: > > On Wed, Jan 27, 2021 at 03:39:44PM -0800, Eric Anholt wrote: > > We were using the same force-poweron bit in the two codepaths, so they > > could race to have one of them lose GPU power early. > > > > Sign

[Freedreno] [PATCH 3/3 v2] drm/msm: Clean up GMU OOB set/clear handling.

Now that the bug is fixed in the minimal way for stable, go make the code table-driven. Signed-off-by: Eric Anholt --- Previous version hadn't been rebased off of a bit of debug code I had, so it wouldn't cleanly apply. drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 124

[Freedreno] [PATCH 1/3] drm/msm: Fix race of GPU init vs timestamp power management.

We were using the same force-poweron bit in the two codepaths, so they could race to have one of them lose GPU power early. Signed-off-by: Eric Anholt Cc: sta...@vger.kernel.org # v5.9 --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 25 ++--- drivers/gpu/drm/msm/adreno

[Freedreno] [PATCH 3/3] drm/msm: Clean up GMU OOB set/clear handling.

Now that the bug is fixed in the minimal way for stable, go make the code table-driven. Signed-off-by: Eric Anholt --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 124 +- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 55 2 files changed, 77 insertions(+), 102

[Freedreno] [PATCH 2/3] drm/msm: Fix races managing the OOB state for timestamp vs timestamps.

that we start many tests in parallel, and waiting for NFS to page in code probably means that lots of tests hit the same point of screen init at the same time). Signed-off-by: Eric Anholt Cc: sta...@vger.kernel.org # v5.9 --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 1 file changed, 4 insertions

[Freedreno] [PATCH 2/2] drm/msm: Quiet error during failure in optional resource mappings.

We don't expect to find vbif_nrt or regdma on cheza, but were clogging up dmesg with errors about it. Signed-off-by: Eric Anholt --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 4 ++-- drivers/gpu/drm/msm/msm_drv.c | 22 ++ drivers/gpu/drm/msm/msm_drv.h

[Freedreno] [PATCH 1/2] drm/msm: Garbage collect unused resource _len fields.

Nothing was using the lengths of these ioremaps. Signed-off-by: Eric Anholt --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 21 - drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 9 - 3 files changed, 31 deletions(-) diff

[Freedreno] [PATCH 1/2] drm/msm: Fix address space size after refactor.

: ccac7ce373c1 ("drm/msm: Refactor address space initialization") Signed-off-by: Eric Anholt --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_g

[Freedreno] [PATCH 2/2] drm/msm: Fix setup of a6xx create_address_space.

We don't want it under CONFIG_DRM_MSM_GPU_STATE, we need it all the time (like the other GPUs do). Fixes: ccac7ce373c1 ("drm/msm: Refactor address space initialization") Signed-off-by: Eric Anholt --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- 1 file changed, 1 insertion(+),

Re: [Freedreno] [PATCH v6 4/5] drm/msm: Refactor address space initialization

On Wed, Jun 17, 2020 at 1:16 PM Eric Anholt wrote: > > On Thu, Apr 9, 2020 at 4:34 PM Jordan Crouse wrote: > > > > Refactor how address space initialization works. Instead of having the > > address space function create the MMU object (and thus require separate but > &

Re: [Freedreno] [PATCH v6 4/5] drm/msm: Refactor address space initialization

On Thu, Apr 9, 2020 at 4:34 PM Jordan Crouse wrote: > > Refactor how address space initialization works. Instead of having the > address space function create the MMU object (and thus require separate but > equal functions for gpummu and iommu) use a single function and pass the > MMU struct in.

Re: [Freedreno] [PATCH v2] drm/msm: Check for powered down HW in the devfreq callbacks

r the suspend state and blindly call into the devfreq > callbacks that end up triggering hardware reads in the GPU driver. > > Call pm_runtime_get_if_in_use() in the gpu_busy() and gpu_set_freq() > callbacks to skip the hardware access if it isn't active. > > v2: Use

Re: [Freedreno] [PATCH] drm/msm: Check for powered down HW in the devfreq callbacks

On Fri, May 1, 2020 at 11:26 AM Jordan Crouse wrote: > > Writing to the devfreq sysfs nodes while the GPU is powered down can > result in a system crash (on a5xx) or a nasty GMU error (on a6xx): > > $ /sys/class/devfreq/500.gpu# echo 5 > min_freq > [ 104.841625] platform

Re: [Freedreno] [PATCH] drm/msm/a5xx: Always set an OPP supported hardware value

ch the default table entries but not > conflict with any possible real bin values. Also fix a small memory leak > and free the buffer allocated by nvmem_cell_read(). > > Signed-off-by: Jordan Crouse This does fix my warn at boot on db820c. Reviewed-by: Eric Anholt _

Re: [Freedreno] [PATCH 3/4] drm/msm: Use dma_resv locking wrappers

base.resv->lock, > > - >ticket); > > + ret = dma_resv_lock_slow_interruptible(msm_obj->base.resv, > > +>ticket); > > if (!ret) { > > submit->bos[contended].flags |= BO_LOCKED; > > slow_locked = contended; > > -- > > 2.24.0 > > Reviewed-by: Eric Anholt ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno

Re: [Freedreno] [PATCH] drm/msm/dpu: Add UBWC support for RGB8888 formats

y: Rob Clark Seems like a reasonable workaround to me, and permissible by our fourcc modifier rules ("you just have to have one way to address the pixels given a fourcc and a modifier"). Reviewed-by: Eric Anholt signature.asc Description: PGP signature ___

Re: [Freedreno] [PATCH 1/5] clk: inherit clocks enabled by bootloader

Rob Clark writes: > From: Rob Clark > > The goal here is to support inheriting a display setup by bootloader, > although there may also be some non-display related use-cases. > > Rough idea is to add a flag for clks and power domains that might > already be enabled when kernel starts, and which

Re: [Freedreno] [PATCH v2 1/5] drm: Add reservation_object to drm_gem_object

es_obj callback. > > With the addition, add a drm_gem_reservation_object_wait() helper > function for drivers to use in wait ioctls. 1, 4, 5 are: Reviewed-by: Eric Anholt signature.asc Description: PGP signature ___ Freedreno mailing list Freedreno@lis

Re: [Freedreno] [PATCH 5/5] drm: vc4: Switch to use drm_gem_object reservation_object

Rob Herring writes: > Now that the base struct drm_gem_object has a reservation_object, use it > and remove the private BO one. Reviewed-by: Eric Anholt signature.asc Description: PGP signature ___ Freedreno mailing list Fre

Re: [Freedreno] [PATCH 4/5] drm: v3d: Switch to use drm_gem_object reservation_object

Rob Herring writes: > Now that the base struct drm_gem_object has a reservation_object, use it > and remove the private BO one. > > Cc: Eric Anholt > Cc: Daniel Vetter > Cc: David Airlie > Cc: dri-de...@lists.freedesktop.org > Signed-off-by: Rob Herr

Re: [Freedreno] [Mesa-dev] [RFC 2/4] nir: Add a new ALU nir_op_imad

Eduardo Lima Mitev writes: > ir3 compiler has an integer multiply-add instruction (IMAD_S24) > that is used for different offset calculations in the backend. > Since we intend to move some of these calculations to NIR, we need > a new ALU op that can represent it. > --- >

Re: [Freedreno] [Mesa-dev] [RFC 1/4] nir: Add a new intrinsic 'load_image_stride'

Eduardo Lima Mitev writes: > This is an internal intrinsic intended to be injected by a > (freedreno-specific) 'lower_sampler_io' pass that will be introduced > later in this series; and consumed by ir3_compiler_nir. > > The intrinsic will load in SSA values for various constants > for images

Re: [Freedreno] [PATCH libdrm v2] libdrm: add msm drm uapi header

Tanmay Shah writes: > msm_drm.h file derived from drm-next kernel uapi header. > > Remove freedreno/msm/msm_drm.h to maintain only > one copy of msm_drm.h and change freedreno Makefile > accordingly. > > Signed-off-by: Tanmay Shah Looks like this is missing the meson.build update, and leaves a

Re: [Freedreno] [PATCH] drm/fourcc: add msm compressed format modifiers

This seems like a reasonable enough description. Reviewed-by: Eric Anholt signature.asc Description: PGP signature ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno

Re: [Freedreno] [Intel-gfx] [PATCH 01/10] include: Move ascii85 functions from i915 to linux/ascii85.h

Chris Wilson writes: > Quoting Jordan Crouse (2018-04-05 23:06:53) >> On Thu, Apr 05, 2018 at 04:00:47PM -0600, Jordan Crouse wrote: >> > The i915 DRM driver very cleverly used ascii85 encoding for their >> > GPU state file. Move the encode functions to a general header

[Freedreno] [PATCH v2 3/5] drm/msm: Reuse dma_fence_release.

If we follow the typical pattern of the base class being the first member, we can use the default dma_fence_free function. Signed-off-by: Eric Anholt <e...@anholt.net> Cc: Rob Clark <robdcl...@gmail.com> Cc: linux-arm-...@vger.kernel.org Cc: freedreno@lists.freedesktop.org --- dri

[Freedreno] [PATCH v2 1/5] drm/msm: Expose our reservation object when exporting a dmabuf.

Without this, polling on the dma-buf (and presumably other devices synchronizing against our rendering) would return immediately, even while the BO was busy. Signed-off-by: Eric Anholt <e...@anholt.net> Reviewed-by: Daniel Vetter <daniel.vet...@ffwll.ch> Cc: sta...@vger.kernel.org C

Re: [Freedreno] [PATCH 1/4] drm/msm: remove qcom, gpu-pwrlevels bindings

Rob Clark writes: > The plan is to use the OPP bindings. For now, remove the documentation > for qcom,gpu-pwrlevels, and make the driver fall back to a safe low > clock if the node is not present. > > Note that no upstream dtb use this node. For now we keep compatibility >